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authorAlejandro Soto <alejandro@34project.org>2022-11-07 19:04:39 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-07 19:04:39 -0600
commitc67a1007045a9bf0282c26da74149723c6a2941d (patch)
tree587140176ca929cdadc58866d072b69fc5da91c9 /rtl/core/arm810.sv
parentcc7ed6bd05b8143ed4250caf97798c8bbfc6b748 (diff)
Fix long combinational path between regs and fetch
Diffstat (limited to 'rtl/core/arm810.sv')
-rw-r--r--rtl/core/arm810.sv3
1 files changed, 1 insertions, 2 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 5525f95..d66ac72 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -21,7 +21,6 @@ module arm810
(
.branch(explicit_branch || wr_pc),
.flush(0), //TODO
- .target(wr_pc ? wr_value[31:2] : branch_target),
.addr(insn_addr),
.fetched(insn_ready),
.fetch_data(insn_data_rd),
@@ -92,7 +91,7 @@ module arm810
);
logic wr_pc;
- word rd_value_a, rd_value_b;
+ word rd_value_a, rd_value_b, wr_current;
core_regs regs
(