diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-18 13:19:55 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-18 13:19:55 -0600 |
| commit | 46eae9622ab6f1a39c6253dc0998e03c57513510 (patch) | |
| tree | f9eb98da738e00f16bf7493ea9a4061dec9645f9 /rtl/core/arm810.sv | |
| parent | 6d458ad9629268ecfc69881b4fb10dca0498fbd0 (diff) | |
Implement mode-translated memory accesses
Diffstat (limited to 'rtl/core/arm810.sv')
| -rw-r--r-- | rtl/core/arm810.sv | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 8ebabc1..1c9d449 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -77,6 +77,7 @@ module arm810 .branch(explicit_branch), .shifter(shifter_ctrl), .mem_addr(data_addr), + .mem_user(data_user), .mem_start(data_start), .mem_write(data_write), .mem_ready(data_ready), @@ -174,9 +175,11 @@ module arm810 ptr data_addr; word data_data_rd, data_data_wr, insn_data_rd; - logic data_start, data_write, data_ready, insn_ready, data_fault, insn_fault; logic[3:0] data_data_be; + logic data_start, data_write, data_ready, insn_ready, + data_fault, insn_fault, data_user; + core_mmu mmu ( .* |