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authorAlejandro Soto <alejandro@34project.org>2022-09-26 09:26:35 -0600
committerAlejandro Soto <alejandro@34project.org>2022-09-26 09:26:35 -0600
commitaf2f49f863deaeb6dc905bbb15701b50bc139873 (patch)
treee86dfc675f18ce49b91f4034788d1aaea4cbf2d3 /rtl/core/alu/alu.sv
parent14d06f0bc047ad79830890807bfe6195ba3de8ff (diff)
Implement ALU shifter
Diffstat (limited to 'rtl/core/alu/alu.sv')
-rw-r--r--rtl/core/alu/alu.sv14
1 files changed, 12 insertions, 2 deletions
diff --git a/rtl/core/alu/alu.sv b/rtl/core/alu/alu.sv
index 914b40e..f5a0487 100644
--- a/rtl/core/alu/alu.sv
+++ b/rtl/core/alu/alu.sv
@@ -5,7 +5,8 @@ module core_alu
(
input alu_control ctrl,
input logic[W - 1:0] a,
- b,
+ base,
+ input logic[7:0] shift,
input logic c_in,
output logic[W - 1:0] q,
@@ -14,12 +15,21 @@ module core_alu
);
logic c, v, swap, sub, and_not, c_shifter, c_add, v_add;
- logic[W - 1:0] swap_a, swap_b, neg_b, c_in_add, q_add, q_and, q_orr, q_xor;
+ logic[W - 1:0] b, swap_a, swap_b, neg_b, c_in_add, q_add, q_and, q_orr, q_xor;
assign swap_a = swap ? b : a;
assign swap_b = swap ? a : b;
assign neg_b = -swap_b;
+ core_alu_shifter #(.W(W)) shifter
+ (
+ .base(base),
+ .shift(shift),
+ .b(b),
+ .c(c_shifter),
+ .*
+ );
+
core_alu_add #(.W(W)) op_add
(
.a(swap_a),