Implement ALU

1 files changed, 20 insertions, 0 deletions

diff --git a/rtl/core/alu/add.sv b/rtl/core/alu/add.sv
new file mode 100644
index 0000000..12bd237
--- /dev/null
+++ b/rtl/core/alu/add.sv
@@ -0,0 +1,20 @@
+module core_alu_add
+#(parameter W=16)
+(
+	input  logic[W - 1:0] a,
+	                      b,
+	                      c_in,
+
+	output logic[W - 1:0] q,
+	output logic          c,
+	                      v
+);
+
+	logic sgn_a, sgn_b, sgn_q;
+	assign {sgn_a, sgn_b, sgn_q} = {a[W - 1], b[W - 1], q[W - 1]};
+
+	//TODO: No sirve el carry
+	assign {c, q} = {1'b0, a} + {1'b0, b} + {1'b0, c_in};
+	assign v = (sgn_a ~^ sgn_b) & (sgn_a ^ sgn_q);
+
+endmodule