rtl/cache: implement debug interface

4 files changed, 108 insertions, 10 deletions

diff --git a/rtl/cache/cache.sv b/rtl/cache/cache.sv
index 1b327b4..6d5a204 100644
--- a/rtl/cache/cache.sv
+++ b/rtl/cache/cache.sv
@@ -16,13 +16,12 @@ module cache
 	output logic[1:0] core_response,
 	output word       core_readdata,
 
-	//TODO
-	/*input  TODO/      dbg_address,
+	input  logic[2:0] dbg_address,
 	input  logic      dbg_read,
 	                  dbg_write,
 	input  word       dbg_writedata,
 	output logic      dbg_waitrequest,
-	output word       dbg_readdata,*/
+	output word       dbg_readdata,
 
 	input  logic      mem_waitrequest,
 	input  line       mem_readdata,
@@ -47,9 +46,6 @@ module cache
 	output logic      out_token_valid
 );
 
-	//TODO
-	//assign dbg_waitrequest = 1;
-
 	logic write_data, write_state;
 	line data_wr, data_rd;
 	addr_tag tag_wr, tag_rd;
@@ -63,7 +59,8 @@ module cache
 
 	word cache_mem_address;
 	line cache_mem_writedata;
-	logic cache_core_waitrequest, cache_mem_waitrequest, cache_mem_read, cache_mem_write;
+	logic cache_core_waitrequest, cache_mem_waitrequest, cache_mem_read, cache_mem_write,
+	      debug_ready;
 
 	cache_control #(.TOKEN_AT_RESET(TOKEN_AT_RESET)) control
 	(
@@ -105,4 +102,11 @@ module cache
 		.*
 	);
 
+	addr_index debug_index;
+
+	cache_debug debug
+	(
+		.*
+	);
+
 endmodule
diff --git a/rtl/cache/cache_control.sv b/rtl/cache/cache_control.sv
index 090fba4..46d4638 100644
--- a/rtl/cache/cache_control.sv
+++ b/rtl/cache/cache_control.sv
@@ -51,7 +51,11 @@ module cache_control
 	output word        mem_address,
 	output logic       mem_read,
 	                   mem_write,
-	output line        mem_writedata
+	output line        mem_writedata,
+
+	input  logic       dbg_write,
+	input  addr_index  debug_index,
+	output logic       debug_ready
 );
 
 	enum int unsigned
@@ -62,8 +66,8 @@ module cache_control
 		REPLY
 	} state, next_state;
 
-	logic accept_snoop, end_reply, in_hold_valid, last_hop, lock_line, locked,
-	      may_send, may_send_if_token_held, mem_begin, mem_end, mem_read_end,
+	logic accept_snoop, debug, end_reply, in_hold_valid, last_hop, lock_line,
+	      locked, may_send, may_send_if_token_held, mem_begin, mem_end, mem_read_end,
 	      mem_wait, out_stall, wait_reply, replace, retry, send, send_inval,
 	      send_read, snoop_hit, set_reply, unlock_line, writeback;
 
@@ -145,6 +149,9 @@ module cache_control
 
 				if (accept_snoop)
 					index_rd = in_hold.index;
+
+				if (debug)
+					index_rd = debug_index;
 			end
 
 			CORE: begin
@@ -321,6 +328,7 @@ module cache_control
 	end
 
 	always_comb begin
+		debug = 0;
 		next_state = ACCEPT;
 
 		unique case (state)
@@ -329,6 +337,8 @@ module cache_control
 					next_state = SNOOP;
 				else if (in_hold_valid && last_hop && in_hold.read)
 					next_state = REPLY;
+				else if (dbg_write && !debug_ready)
+					debug = 1;
 				else if ((core_read || core_write) && !wait_reply && (!locked || may_send))
 					next_state = CORE;
 
@@ -356,6 +366,8 @@ module cache_control
 
 			mem_read <= 0;
 			mem_write <= 0;
+
+			debug_ready <= 0;
 		end else begin
 			out_token.e0.tag <= core_tag;
 			out_token.e0.index <= core_index;
@@ -391,6 +403,8 @@ module cache_control
 				mem_read <= !writeback;
 				mem_write <= writeback;
 			end
+
+			debug_ready <= debug;
 		end
 
 	always_ff @(posedge clk) begin
diff --git a/rtl/cache/cache_debug.sv b/rtl/cache/cache_debug.sv
new file mode 100644
index 0000000..14b73e5
--- /dev/null
+++ b/rtl/cache/cache_debug.sv
@@ -0,0 +1,71 @@
+`include "cache/defs.sv"
+
+module cache_debug
+(
+	input  logic      clk,
+	                  rst_n,
+
+	input  logic[2:0] dbg_address,
+	input  logic      dbg_read,
+	input  word       dbg_writedata,
+	output logic      dbg_waitrequest,
+	output word       dbg_readdata,
+
+	input  logic      debug_ready,
+	input  addr_tag   tag_rd,
+	input  line       data_rd,
+	input  line_state state_rd,
+	output addr_index debug_index
+);
+
+	struct packed
+	{
+		logic[2:0] mbz_0;
+		addr_tag   tag;
+		addr_index index;
+		line_state state;
+		logic      cached,
+		           mbz_1;
+	} status;
+
+	line line_dump;
+	word word_dump, word_3, word_2, word_1, word_0;
+	addr_bits debug_addr_bits;
+
+	logic cached;
+	addr_tag tag;
+	addr_index index;
+	line_state state;
+
+	assign debug_index = debug_addr_bits.index;
+	assign dbg_readdata = dbg_address[2] ? word_dump : status;
+	assign dbg_waitrequest = !debug_ready && !dbg_read;
+
+	assign status.tag = tag;
+	assign status.index = index;
+	assign status.state = state;
+	assign status.mbz_0 = 3'b000;
+	assign status.mbz_1 = 0;
+	assign status.cached = cached;
+	assign debug_addr_bits = dbg_writedata;
+
+	assign {word_3, word_2, word_1, word_0} = line_dump;
+
+	always_comb
+		unique case (dbg_address[1:0])
+			2'b00: word_dump = word_0;
+			2'b01: word_dump = word_1;
+			2'b10: word_dump = word_2;
+			2'b11: word_dump = word_3;
+		endcase
+
+	always @(posedge clk)
+		if (debug_ready) begin
+			tag <= tag_rd;
+			index <= debug_addr_bits.index;
+			state <= state_rd;
+			cached <= !(|debug_addr_bits.io);
+			line_dump <= data_rd;
+		end
+
+endmodule
diff --git a/rtl/cache/defs.sv b/rtl/cache/defs.sv
index e21e587..0546c4d 100644
--- a/rtl/cache/defs.sv
+++ b/rtl/cache/defs.sv
@@ -28,6 +28,15 @@ typedef logic[15:0] addr_tag;
 typedef logic[2:0]  addr_io_region;
 typedef logic[26:0] addr_cacheable;
 
+typedef struct packed
+{
+	addr_io_region io;
+	addr_tag       tag;
+	addr_index     index;
+	addr_offset    offset;
+	addr_mbz       mbz;
+} addr_bits;
+
 typedef enum logic[1:0]
 {
 	INVALID,