rtl/perf: implement performance unit

3 files changed, 14 insertions, 2 deletions

diff --git a/rtl/cache/cache_control.sv b/rtl/cache/cache_control.sv
index b31b6a8..64b4ce1 100644
--- a/rtl/cache/cache_control.sv
+++ b/rtl/cache/cache_control.sv
@@ -80,7 +80,7 @@ module cache_control
 
 	assign mem_end = (mem_read || mem_write) && !mem_waitrequest;
 	assign mem_wait = (mem_read || mem_write) && mem_waitrequest;
-	assign mem_address = {3'b000, mem_tag, mem_index, 4'b0000};
+	assign mem_address = {`IO_CACHED, mem_tag, mem_index, 4'b0000};
 	assign mem_read_end = mem_read && !mem_waitrequest;
 
 	/* Desbloquear la línea hasta que la request del core termine garantiza
diff --git a/rtl/cache/defs.sv b/rtl/cache/defs.sv
index 24ab9ea..2c7550f 100644
--- a/rtl/cache/defs.sv
+++ b/rtl/cache/defs.sv
@@ -7,11 +7,13 @@ typedef logic[15:0]  line_be;
 
 // Tamaño de una línea de cache
 typedef logic[127:0] line;
+typedef logic[27:0]  line_ptr;
 
 // Choca con typedef en core/uarch.sv
 `ifndef WORD_DEFINED
 typedef logic[29:0] ptr;
 typedef logic[31:0] word;
+typedef logic[15:0] hword;
 `define WORD_DEFINED
 `endif
 
@@ -36,6 +38,8 @@ typedef logic[12:0] addr_tag;
 typedef logic[2:0]  addr_io_region;
 typedef logic[26:0] addr_cacheable;
 
+`define IO_CACHED 3'b000
+
 typedef struct packed
 {
 	addr_io_region io;
@@ -68,6 +72,14 @@ typedef struct packed
 	line       data;
 } ring_req;
 
+typedef struct packed
+{
+	logic[1:0] ttl;
+	logic      read,
+	           inval,
+	           reply;
+} perf_sample;
+
 `define TTL_END 2'b00
 `define TTL_MAX 2'b11
 
diff --git a/rtl/cache/routing.sv b/rtl/cache/routing.sv
index 78f1be0..4119a7f 100644
--- a/rtl/cache/routing.sv
+++ b/rtl/cache/routing.sv
@@ -63,7 +63,7 @@ module cache_routing
 	 * Entonces si los bits de IO son distintos de 0, se sabe que no es
 	 * una dirección cached
 	 */
-	assign cached = io == 3'b000;
+	assign cached = io == `IO_CACHED;
 	// Se afirma si cache quiere hacer un read o write de memoria
 	assign cache_mem = cache_mem_read || cache_mem_write;