rtl/cache: implement debug interface

1 files changed, 11 insertions, 7 deletions

diff --git a/rtl/cache/cache.sv b/rtl/cache/cache.sv
index 1b327b4..6d5a204 100644
--- a/rtl/cache/cache.sv
+++ b/rtl/cache/cache.sv
@@ -16,13 +16,12 @@ module cache
 	output logic[1:0] core_response,
 	output word       core_readdata,
 
-	//TODO
-	/*input  TODO/      dbg_address,
+	input  logic[2:0] dbg_address,
 	input  logic      dbg_read,
 	                  dbg_write,
 	input  word       dbg_writedata,
 	output logic      dbg_waitrequest,
-	output word       dbg_readdata,*/
+	output word       dbg_readdata,
 
 	input  logic      mem_waitrequest,
 	input  line       mem_readdata,
@@ -47,9 +46,6 @@ module cache
 	output logic      out_token_valid
 );
 
-	//TODO
-	//assign dbg_waitrequest = 1;
-
 	logic write_data, write_state;
 	line data_wr, data_rd;
 	addr_tag tag_wr, tag_rd;
@@ -63,7 +59,8 @@ module cache
 
 	word cache_mem_address;
 	line cache_mem_writedata;
-	logic cache_core_waitrequest, cache_mem_waitrequest, cache_mem_read, cache_mem_write;
+	logic cache_core_waitrequest, cache_mem_waitrequest, cache_mem_read, cache_mem_write,
+	      debug_ready;
 
 	cache_control #(.TOKEN_AT_RESET(TOKEN_AT_RESET)) control
 	(
@@ -105,4 +102,11 @@ module cache
 		.*
 	);
 
+	addr_index debug_index;
+
+	cache_debug debug
+	(
+		.*
+	);
+
 endmodule