diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-09-18 17:16:46 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-09-18 17:16:46 -0600 |
| commit | 503957e2883e754fc8424c420c3d9838bd639ed3 (patch) | |
| tree | f4b0bad5928fee6a43b73f246df875e14b3f6728 /rtl/bus | |
| parent | 54544911601351465a6a887a045f3baddcb90dc6 (diff) | |
Fix memory simulation
Diffstat (limited to 'rtl/bus')
| -rw-r--r-- | rtl/bus/master.sv | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv index 5d8c3a8..d350d80 100644 --- a/rtl/bus/master.sv +++ b/rtl/bus/master.sv @@ -26,6 +26,7 @@ module bus_master } state; assign data_rd = avl_readdata; + assign avl_byteenable = 4'b1111; always_ff @(posedge clk) unique case(state) REQUEST: if(start) begin @@ -33,6 +34,7 @@ module bus_master avl_read <= ~write; avl_write <= write; avl_writedata <= data_rw; + state <= WAIT; end WAIT: if(~avl_waitrequest) begin |