platform: implement SMP controller

1 files changed, 112 insertions, 4 deletions

diff --git a/platform.qsys b/platform.qsys
index b66adb2..7190777 100644
--- a/platform.qsys
+++ b/platform.qsys
@@ -206,6 +206,22 @@
          type = "String";
       }
    }
+   element platform
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element platform
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
    element pll_0
    {
       datum _sortIndex
@@ -214,6 +230,14 @@
          type = "int";
       }
    }
+   element smp_0
+   {
+      datum _sortIndex
+      {
+         value = "27";
+         type = "int";
+      }
+   }
    element switches
    {
       datum _sortIndex
@@ -294,7 +318,6 @@
    type="conduit"
    dir="end" />
  <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
- <interface name="cpu_0_mp" internal="cpu_0.mp" type="conduit" dir="end" />
  <interface name="cpu_0_mp_1" internal="cpu_0.mp_1" />
  <interface name="memory" internal="hps_0.memory" type="conduit" dir="end" />
  <interface
@@ -370,13 +393,13 @@
  <module name="cpu_0" kind="core" version="1.0" enabled="1">
   <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="1" />
  </module>
- <module name="cpu_1" kind="core" version="1.0" enabled="0">
+ <module name="cpu_1" kind="core" version="1.0" enabled="1">
   <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" />
  </module>
- <module name="cpu_2" kind="core" version="1.0" enabled="0">
+ <module name="cpu_2" kind="core" version="1.0" enabled="1">
   <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" />
  </module>
- <module name="cpu_3" kind="core" version="1.0" enabled="0">
+ <module name="cpu_3" kind="core" version="1.0" enabled="1">
   <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" />
  </module>
  <module name="hps_0" kind="altera_hps" version="20.1" enabled="1">
@@ -1217,6 +1240,7 @@
   <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
   <parameter name="gui_use_locked" value="false" />
  </module>
+ <module name="smp_0" kind="smp" version="1.0" enabled="1" />
  <module name="switches" kind="altera_avalon_pio" version="20.1" enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
   <parameter name="bitModifyingOutReg" value="false" />
@@ -1370,6 +1394,11 @@
   <parameter name="baseAddress" value="0x30070000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="smp_0.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x30140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="buttons.s1">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x30050000" />
@@ -1409,6 +1438,21 @@
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection kind="avalon" version="20.1" start="cpu_3.master" end="cache_3.core">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="20.1" start="cpu_2.master" end="cache_2.core">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="20.1" start="cpu_1.master" end="cache_1.core">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="avalon"
    version="20.1"
@@ -1530,6 +1574,7 @@
    start="pll_0.outclk0"
    end="hps_0.f2h_sdram0_clock" />
  <connection kind="clock" version="20.1" start="pll_0.outclk1" end="mm_bridge.clk" />
+ <connection kind="clock" version="20.1" start="pll_0.outclk1" end="smp_0.clock" />
  <connection
    kind="clock"
    version="20.1"
@@ -1558,6 +1603,21 @@
  <connection
    kind="clock"
    version="20.1"
+   start="pll_0.outclk1"
+   end="cpu_3.clock_sink" />
+ <connection
+   kind="clock"
+   version="20.1"
+   start="pll_0.outclk1"
+   end="cpu_2.clock_sink" />
+ <connection
+   kind="clock"
+   version="20.1"
+   start="pll_0.outclk1"
+   end="cpu_1.clock_sink" />
+ <connection
+   kind="clock"
+   version="20.1"
    start="sys_sdram_pll_0.sys_clk"
    end="vram.clk" />
  <connection
@@ -1581,6 +1641,34 @@
    version="20.1"
    start="video_pll_0.vga_clk"
    end="pixfifo.clock_stream_out" />
+ <connection kind="conduit" version="20.1" start="cpu_0.smp" end="smp_0.cpu_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection kind="conduit" version="20.1" start="cpu_1.smp" end="smp_0.cpu_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection kind="conduit" version="20.1" start="cpu_2.smp" end="smp_0.cpu_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection kind="conduit" version="20.1" start="cpu_3.smp" end="smp_0.cpu_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="interrupt"
    version="20.1"
@@ -1681,6 +1769,26 @@
  <connection
    kind="reset"
    version="20.1"
+   start="clk_0.clk_reset"
+   end="cpu_3.reset_sink" />
+ <connection
+   kind="reset"
+   version="20.1"
+   start="clk_0.clk_reset"
+   end="cpu_2.reset_sink" />
+ <connection
+   kind="reset"
+   version="20.1"
+   start="clk_0.clk_reset"
+   end="cpu_1.reset_sink" />
+ <connection
+   kind="reset"
+   version="20.1"
+   start="clk_0.clk_reset"
+   end="smp_0.reset_sink" />
+ <connection
+   kind="reset"
+   version="20.1"
    start="sys_sdram_pll_0.reset_source"
    end="vram.reset" />
  <connection