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| author | Alejandro Soto <alejandro@34project.org> | 2024-02-20 11:09:23 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-02-20 11:12:23 -0600 |
| commit | 49c6d9ed78a5ce67eaa6edb40c3dacd956ebca75 (patch) | |
| tree | 5aac580779b90144a174015024a4551cebe17265 /mk/verilator.mk | |
| parent | a9ba2e1d3e0bee4f7534b29f266d122567d6dd42 (diff) | |
mk: implement support for quartus synthesis
Diffstat (limited to '')
| -rw-r--r-- | mk/verilator.mk | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/mk/verilator.mk b/mk/verilator.mk index 56d8783..2692863 100644 --- a/mk/verilator.mk +++ b/mk/verilator.mk @@ -17,10 +17,7 @@ endef define target/sim/setup $(setup_verilator_target) - $$(call target_var,vl_main) := $$(strip $$(call core_paths,$$(rule_top),vl_main)) - ifeq (,$$(vl_main)) - $$(error core '$$(rule_top)' does not define vl_main) - endif + $$(call target_var,vl_main) := $$(strip $$(call require_core_paths,$$(rule_top),vl_main)) endef define target/sim/rules @@ -123,8 +120,8 @@ endef verilator_src_args = \ $(strip \ - $(let rtl_top,$(core_info/$(rule_top)/rtl_top), \ - $(if $(rtl_top),--top $(rtl_top),$(error core '$(rule_top)' must define rtl_top)) \ + $(let rtl_top,$(call require_core_var,$(rule_top),rtl_top), \ + --top $(rtl_top) \ $(foreach dep,$(dep_tree/$(rule_top)), \ $(let prefix,$(core_info/$(dep)/workdir)/, \ $(foreach rtl_dir,$(call core_paths,$(dep),rtl_dirs), \ @@ -132,6 +129,5 @@ verilator_src_args = \ $(foreach include_dir,$(call core_paths,$(dep),rtl_include_dirs), \ -I$(include_dir)) \ $(foreach src_file,$(call core_paths,$(dep),rtl_files) $(call core_paths,$(dep),vl_files), \ - $(src_file)))) \ - $(if $(core_info/$(rule_top)/rtl_files),,$(rtl_top))) \ + $(src_file))))) \ $(if $(vl_main),$(vl_main),$(error $$(vl_main) not defined by target '$(rule_target)'))) |