rtl/gfx: synchronize clock with SDRAM

9 files changed, 747 insertions, 462 deletions

diff --git a/ip/ip_fp_mul.qip b/ip/ip_fp_mul.qip
index f6114d9..845398a 100644
--- a/ip/ip_fp_mul.qip
+++ b/ip/ip_fp_mul.qip
@@ -35,8 +35,8 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MTA=::TWFudGlzc2E="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MTA=::ZnBfbWFuX2Rlcml2ZWQ="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg="
-set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0"
-set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::NA==::VGFyZ2V0"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MjAw::VGFyZ2V0"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Mg==::VGFyZ2V0"
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::ZnJlcXVlbmN5::R29hbA=="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ=="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ=="
@@ -52,8 +52,8 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg=="
-set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MTA4::ZnJlcXVlbmN5X2ZlZWRiYWNr"
-set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::Mw==::bGF0ZW5jeV9mZWVkYmFjaw=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::NQ==::bGF0ZW5jeV9mZWVkYmFjaw=="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl"
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA=="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50"
@@ -69,7 +69,7 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MQ==::TXVsdGlwbGllcw=="
-set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MTE5::TFVUcw=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MTQ0::TFVUcw=="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw=="
 set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ=="
diff --git a/ip/ip_fp_mul.v b/ip/ip_fp_mul.v
index 22fa2bb..d8f0e67 100644
--- a/ip/ip_fp_mul.v
+++ b/ip/ip_fp_mul.v
@@ -63,8 +63,8 @@ endmodule
 // Retrieval info: 	<generic name="fp_exp" value="5" />
 // Retrieval info: 	<generic name="fp_man" value="10" />
 // Retrieval info: 	<generic name="exponent_width" value="23" />
-// Retrieval info: 	<generic name="frequency_target" value="100" />
-// Retrieval info: 	<generic name="latency_target" value="4" />
+// Retrieval info: 	<generic name="frequency_target" value="200" />
+// Retrieval info: 	<generic name="latency_target" value="2" />
 // Retrieval info: 	<generic name="performance_goal" value="frequency" />
 // Retrieval info: 	<generic name="rounding_mode" value="nearest with tie breaking away from zero" />
 // Retrieval info: 	<generic name="faithful_rounding" value="true" />
diff --git a/ip/ip_fp_mul/ip_fp_mul_0002.vhd b/ip/ip_fp_mul/ip_fp_mul_0002.vhd
index 582906b..443f819 100644
--- a/ip/ip_fp_mul/ip_fp_mul_0002.vhd
+++ b/ip/ip_fp_mul/ip_fp_mul_0002.vhd
@@ -16,7 +16,7 @@
 -- ---------------------------------------------------------------------------
 
 -- VHDL created from ip_fp_mul_0002
--- VHDL created on Sat Oct 21 14:27:40 2023
+-- VHDL created on Wed Oct 25 23:48:20 2023
 
 
 library IEEE;
@@ -67,6 +67,7 @@ architecture normal of ip_fp_mul_0002 is
     signal fracXIsZero_uid17_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal fracXIsNotZero_uid18_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal excI_x_uid19_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal excN_x_uid20_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excN_x_uid20_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal invExpXIsMax_uid21_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal InvExpXIsZero_uid22_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
@@ -80,6 +81,7 @@ architecture normal of ip_fp_mul_0002 is
     signal fracXIsZero_uid31_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal fracXIsNotZero_uid32_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal excI_y_uid33_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal excN_y_uid34_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excN_y_uid34_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal invExpXIsMax_uid35_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal InvExpXIsZero_uid36_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
@@ -123,18 +125,27 @@ architecture normal of ip_fp_mul_0002 is
     signal expOvf_uid64_fpMulTest_b : STD_LOGIC_VECTOR (10 downto 0);
     signal expOvf_uid64_fpMulTest_o : STD_LOGIC_VECTOR (10 downto 0);
     signal expOvf_uid64_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
+    signal excXZAndExcYZ_uid65_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excXZAndExcYZ_uid65_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal excXZAndExcYR_uid66_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excXZAndExcYR_uid66_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal excYZAndExcXR_uid67_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excYZAndExcXR_uid67_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal excZC3_uid68_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excZC3_uid68_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal excRZero_uid69_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal excXIAndExcYI_uid70_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excXIAndExcYI_uid70_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal excXRAndExcYI_uid71_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excXRAndExcYI_uid71_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal excYRAndExcXI_uid72_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal excYRAndExcXI_uid72_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal ExcROvfAndInReg_uid73_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal ExcROvfAndInReg_uid73_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal excRInf_uid74_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal excYZAndExcXI_uid75_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal excXZAndExcYI_uid76_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal ZeroTimesInf_uid77_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
     signal ZeroTimesInf_uid77_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal excRNaN_uid78_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
     signal concExc_uid79_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
@@ -166,17 +177,19 @@ architecture normal of ip_fp_mul_0002 is
     signal prodXY_uid94_prod_uid47_fpMulTest_cma_q : STD_LOGIC_VECTOR (21 downto 0);
     signal prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 : std_logic;
     signal prodXY_uid94_prod_uid47_fpMulTest_cma_ena1 : std_logic;
-    signal redist0_expRPreExcExt_uid60_fpMulTest_b_1_q : STD_LOGIC_VECTOR (8 downto 0);
-    signal redist1_fracRPreExc_uid59_fpMulTest_b_1_q : STD_LOGIC_VECTOR (9 downto 0);
-    signal redist2_signR_uid48_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
-    signal redist3_fracXIsZero_uid31_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
-    signal redist4_expXIsMax_uid30_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
-    signal redist5_excZ_y_uid29_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
-    signal redist6_fracXIsZero_uid17_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
-    signal redist7_expXIsMax_uid16_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
-    signal redist8_excZ_x_uid15_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
-    signal redist9_expY_uid7_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0);
-    signal redist10_expX_uid6_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0);
+    signal redist0_expRPreExc_uid61_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0);
+    signal redist1_expRPreExcExt_uid60_fpMulTest_b_1_q : STD_LOGIC_VECTOR (8 downto 0);
+    signal redist2_fracRPreExc_uid59_fpMulTest_b_2_q : STD_LOGIC_VECTOR (9 downto 0);
+    signal redist3_normalizeBit_uid49_fpMulTest_b_1_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal redist4_signR_uid48_fpMulTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal redist5_fracXIsZero_uid31_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal redist6_expXIsMax_uid30_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal redist7_excZ_y_uid29_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal redist8_fracXIsZero_uid17_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal redist9_expXIsMax_uid16_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal redist10_excZ_x_uid15_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+    signal redist11_expY_uid7_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0);
+    signal redist12_expX_uid6_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0);
 
 begin
 
@@ -193,10 +206,10 @@ begin
     GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
     PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_qi, xout => fracXIsZero_uid17_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- redist6_fracXIsZero_uid17_fpMulTest_q_3(DELAY,103)
-    redist6_fracXIsZero_uid17_fpMulTest_q_3 : dspba_delay
-    GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
-    PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist6_fracXIsZero_uid17_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset );
+    -- redist8_fracXIsZero_uid17_fpMulTest_q_4(DELAY,105)
+    redist8_fracXIsZero_uid17_fpMulTest_q_4 : dspba_delay
+    GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
+    PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist8_fracXIsZero_uid17_fpMulTest_q_4_q, ena => en(0), clk => clk, aclr => areset );
 
     -- cstAllOWE_uid10_fpMulTest(CONSTANT,9)
     cstAllOWE_uid10_fpMulTest_q <= "11111";
@@ -204,24 +217,24 @@ begin
     -- expX_uid6_fpMulTest(BITSELECT,5)@0
     expX_uid6_fpMulTest_b <= a(14 downto 10);
 
-    -- redist10_expX_uid6_fpMulTest_b_1(DELAY,107)
-    redist10_expX_uid6_fpMulTest_b_1 : dspba_delay
+    -- redist12_expX_uid6_fpMulTest_b_1(DELAY,109)
+    redist12_expX_uid6_fpMulTest_b_1 : dspba_delay
     GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" )
-    PORT MAP ( xin => expX_uid6_fpMulTest_b, xout => redist10_expX_uid6_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
+    PORT MAP ( xin => expX_uid6_fpMulTest_b, xout => redist12_expX_uid6_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
 
     -- expXIsMax_uid16_fpMulTest(LOGICAL,15)@1 + 1
-    expXIsMax_uid16_fpMulTest_qi <= "1" WHEN redist10_expX_uid6_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0";
+    expXIsMax_uid16_fpMulTest_qi <= "1" WHEN redist12_expX_uid6_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0";
     expXIsMax_uid16_fpMulTest_delay : dspba_delay
     GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
     PORT MAP ( xin => expXIsMax_uid16_fpMulTest_qi, xout => expXIsMax_uid16_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- redist7_expXIsMax_uid16_fpMulTest_q_2(DELAY,104)
-    redist7_expXIsMax_uid16_fpMulTest_q_2 : dspba_delay
-    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
-    PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist7_expXIsMax_uid16_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset );
+    -- redist9_expXIsMax_uid16_fpMulTest_q_3(DELAY,106)
+    redist9_expXIsMax_uid16_fpMulTest_q_3 : dspba_delay
+    GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
+    PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist9_expXIsMax_uid16_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excI_x_uid19_fpMulTest(LOGICAL,18)@3
-    excI_x_uid19_fpMulTest_q <= redist7_expXIsMax_uid16_fpMulTest_q_2_q and redist6_fracXIsZero_uid17_fpMulTest_q_3_q;
+    -- excI_x_uid19_fpMulTest(LOGICAL,18)@4
+    excI_x_uid19_fpMulTest_q <= redist9_expXIsMax_uid16_fpMulTest_q_3_q and redist8_fracXIsZero_uid17_fpMulTest_q_4_q;
 
     -- cstAllZWE_uid12_fpMulTest(CONSTANT,11)
     cstAllZWE_uid12_fpMulTest_q <= "00000";
@@ -229,24 +242,24 @@ begin
     -- expY_uid7_fpMulTest(BITSELECT,6)@0
     expY_uid7_fpMulTest_b <= b(14 downto 10);
 
-    -- redist9_expY_uid7_fpMulTest_b_1(DELAY,106)
-    redist9_expY_uid7_fpMulTest_b_1 : dspba_delay
+    -- redist11_expY_uid7_fpMulTest_b_1(DELAY,108)
+    redist11_expY_uid7_fpMulTest_b_1 : dspba_delay
     GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" )
-    PORT MAP ( xin => expY_uid7_fpMulTest_b, xout => redist9_expY_uid7_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
+    PORT MAP ( xin => expY_uid7_fpMulTest_b, xout => redist11_expY_uid7_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
 
     -- excZ_y_uid29_fpMulTest(LOGICAL,28)@1 + 1
-    excZ_y_uid29_fpMulTest_qi <= "1" WHEN redist9_expY_uid7_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0";
+    excZ_y_uid29_fpMulTest_qi <= "1" WHEN redist11_expY_uid7_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0";
     excZ_y_uid29_fpMulTest_delay : dspba_delay
     GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
     PORT MAP ( xin => excZ_y_uid29_fpMulTest_qi, xout => excZ_y_uid29_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- redist5_excZ_y_uid29_fpMulTest_q_2(DELAY,102)
-    redist5_excZ_y_uid29_fpMulTest_q_2 : dspba_delay
-    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
-    PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist5_excZ_y_uid29_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset );
+    -- redist7_excZ_y_uid29_fpMulTest_q_3(DELAY,104)
+    redist7_excZ_y_uid29_fpMulTest_q_3 : dspba_delay
+    GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist7_excZ_y_uid29_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@3
-    excYZAndExcXI_uid75_fpMulTest_q <= redist5_excZ_y_uid29_fpMulTest_q_2_q and excI_x_uid19_fpMulTest_q;
+    -- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@4
+    excYZAndExcXI_uid75_fpMulTest_q <= redist7_excZ_y_uid29_fpMulTest_q_3_q and excI_x_uid19_fpMulTest_q;
 
     -- frac_y_uid28_fpMulTest(BITSELECT,27)@0
     frac_y_uid28_fpMulTest_b <= b(9 downto 0);
@@ -257,58 +270,67 @@ begin
     GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
     PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_qi, xout => fracXIsZero_uid31_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- redist3_fracXIsZero_uid31_fpMulTest_q_3(DELAY,100)
-    redist3_fracXIsZero_uid31_fpMulTest_q_3 : dspba_delay
-    GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
-    PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist3_fracXIsZero_uid31_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset );
+    -- redist5_fracXIsZero_uid31_fpMulTest_q_4(DELAY,102)
+    redist5_fracXIsZero_uid31_fpMulTest_q_4 : dspba_delay
+    GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
+    PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist5_fracXIsZero_uid31_fpMulTest_q_4_q, ena => en(0), clk => clk, aclr => areset );
 
     -- expXIsMax_uid30_fpMulTest(LOGICAL,29)@1 + 1
-    expXIsMax_uid30_fpMulTest_qi <= "1" WHEN redist9_expY_uid7_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0";
+    expXIsMax_uid30_fpMulTest_qi <= "1" WHEN redist11_expY_uid7_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0";
     expXIsMax_uid30_fpMulTest_delay : dspba_delay
     GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
     PORT MAP ( xin => expXIsMax_uid30_fpMulTest_qi, xout => expXIsMax_uid30_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- redist4_expXIsMax_uid30_fpMulTest_q_2(DELAY,101)
-    redist4_expXIsMax_uid30_fpMulTest_q_2 : dspba_delay
-    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
-    PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist4_expXIsMax_uid30_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset );
+    -- redist6_expXIsMax_uid30_fpMulTest_q_3(DELAY,103)
+    redist6_expXIsMax_uid30_fpMulTest_q_3 : dspba_delay
+    GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
+    PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist6_expXIsMax_uid30_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excI_y_uid33_fpMulTest(LOGICAL,32)@3
-    excI_y_uid33_fpMulTest_q <= redist4_expXIsMax_uid30_fpMulTest_q_2_q and redist3_fracXIsZero_uid31_fpMulTest_q_3_q;
+    -- excI_y_uid33_fpMulTest(LOGICAL,32)@4
+    excI_y_uid33_fpMulTest_q <= redist6_expXIsMax_uid30_fpMulTest_q_3_q and redist5_fracXIsZero_uid31_fpMulTest_q_4_q;
 
     -- excZ_x_uid15_fpMulTest(LOGICAL,14)@1 + 1
-    excZ_x_uid15_fpMulTest_qi <= "1" WHEN redist10_expX_uid6_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0";
+    excZ_x_uid15_fpMulTest_qi <= "1" WHEN redist12_expX_uid6_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0";
     excZ_x_uid15_fpMulTest_delay : dspba_delay
     GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
     PORT MAP ( xin => excZ_x_uid15_fpMulTest_qi, xout => excZ_x_uid15_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- redist8_excZ_x_uid15_fpMulTest_q_2(DELAY,105)
-    redist8_excZ_x_uid15_fpMulTest_q_2 : dspba_delay
-    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
-    PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist8_excZ_x_uid15_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset );
+    -- redist10_excZ_x_uid15_fpMulTest_q_3(DELAY,107)
+    redist10_excZ_x_uid15_fpMulTest_q_3 : dspba_delay
+    GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist10_excZ_x_uid15_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@3
-    excXZAndExcYI_uid76_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and excI_y_uid33_fpMulTest_q;
+    -- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@4
+    excXZAndExcYI_uid76_fpMulTest_q <= redist10_excZ_x_uid15_fpMulTest_q_3_q and excI_y_uid33_fpMulTest_q;
 
-    -- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@3
-    ZeroTimesInf_uid77_fpMulTest_q <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q;
+    -- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@4 + 1
+    ZeroTimesInf_uid77_fpMulTest_qi <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q;
+    ZeroTimesInf_uid77_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => ZeroTimesInf_uid77_fpMulTest_qi, xout => ZeroTimesInf_uid77_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@3
-    fracXIsNotZero_uid32_fpMulTest_q <= not (redist3_fracXIsZero_uid31_fpMulTest_q_3_q);
+    -- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@4
+    fracXIsNotZero_uid32_fpMulTest_q <= not (redist5_fracXIsZero_uid31_fpMulTest_q_4_q);
 
-    -- excN_y_uid34_fpMulTest(LOGICAL,33)@3
-    excN_y_uid34_fpMulTest_q <= redist4_expXIsMax_uid30_fpMulTest_q_2_q and fracXIsNotZero_uid32_fpMulTest_q;
+    -- excN_y_uid34_fpMulTest(LOGICAL,33)@4 + 1
+    excN_y_uid34_fpMulTest_qi <= redist6_expXIsMax_uid30_fpMulTest_q_3_q and fracXIsNotZero_uid32_fpMulTest_q;
+    excN_y_uid34_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excN_y_uid34_fpMulTest_qi, xout => excN_y_uid34_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@3
-    fracXIsNotZero_uid18_fpMulTest_q <= not (redist6_fracXIsZero_uid17_fpMulTest_q_3_q);
+    -- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@4
+    fracXIsNotZero_uid18_fpMulTest_q <= not (redist8_fracXIsZero_uid17_fpMulTest_q_4_q);
 
-    -- excN_x_uid20_fpMulTest(LOGICAL,19)@3
-    excN_x_uid20_fpMulTest_q <= redist7_expXIsMax_uid16_fpMulTest_q_2_q and fracXIsNotZero_uid18_fpMulTest_q;
+    -- excN_x_uid20_fpMulTest(LOGICAL,19)@4 + 1
+    excN_x_uid20_fpMulTest_qi <= redist9_expXIsMax_uid16_fpMulTest_q_3_q and fracXIsNotZero_uid18_fpMulTest_q;
+    excN_x_uid20_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excN_x_uid20_fpMulTest_qi, xout => excN_x_uid20_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excRNaN_uid78_fpMulTest(LOGICAL,77)@3
+    -- excRNaN_uid78_fpMulTest(LOGICAL,77)@5
     excRNaN_uid78_fpMulTest_q <= excN_x_uid20_fpMulTest_q or excN_y_uid34_fpMulTest_q or ZeroTimesInf_uid77_fpMulTest_q;
 
-    -- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@3
+    -- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@5
     invExcRNaN_uid90_fpMulTest_q <= not (excRNaN_uid78_fpMulTest_q);
 
     -- signY_uid9_fpMulTest(BITSELECT,8)@0
@@ -323,13 +345,13 @@ begin
     GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
     PORT MAP ( xin => signR_uid48_fpMulTest_qi, xout => signR_uid48_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- redist2_signR_uid48_fpMulTest_q_3(DELAY,99)
-    redist2_signR_uid48_fpMulTest_q_3 : dspba_delay
-    GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
-    PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist2_signR_uid48_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset );
+    -- redist4_signR_uid48_fpMulTest_q_5(DELAY,101)
+    redist4_signR_uid48_fpMulTest_q_5 : dspba_delay
+    GENERIC MAP ( width => 1, depth => 4, reset_kind => "ASYNC" )
+    PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist4_signR_uid48_fpMulTest_q_5_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- signRPostExc_uid91_fpMulTest(LOGICAL,90)@3
-    signRPostExc_uid91_fpMulTest_q <= redist2_signR_uid48_fpMulTest_q_3_q and invExcRNaN_uid90_fpMulTest_q;
+    -- signRPostExc_uid91_fpMulTest(LOGICAL,90)@5
+    signRPostExc_uid91_fpMulTest_q <= redist4_signR_uid48_fpMulTest_q_5_q and invExcRNaN_uid90_fpMulTest_q;
 
     -- GND(CONSTANT,0)
     GND_q <= "0";
@@ -382,18 +404,23 @@ begin
     -- normalizeBit_uid49_fpMulTest(BITSELECT,48)@2
     normalizeBit_uid49_fpMulTest_b <= STD_LOGIC_VECTOR(osig_uid95_prod_uid47_fpMulTest_b(12 downto 12));
 
+    -- redist3_normalizeBit_uid49_fpMulTest_b_1(DELAY,100)
+    redist3_normalizeBit_uid49_fpMulTest_b_1 : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => normalizeBit_uid49_fpMulTest_b, xout => redist3_normalizeBit_uid49_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
+
     -- VCC(CONSTANT,1)
     VCC_q <= "1";
 
-    -- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@2
-    roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & normalizeBit_uid49_fpMulTest_b & cstZeroWF_uid11_fpMulTest_q & VCC_q;
+    -- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@3
+    roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & redist3_normalizeBit_uid49_fpMulTest_b_1_q & cstZeroWF_uid11_fpMulTest_q & VCC_q;
 
     -- biasInc_uid45_fpMulTest(CONSTANT,44)
     biasInc_uid45_fpMulTest_q <= "0001111";
 
     -- expSum_uid44_fpMulTest(ADD,43)@1 + 1
-    expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & redist10_expX_uid6_fpMulTest_b_1_q);
-    expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & redist9_expY_uid7_fpMulTest_b_1_q);
+    expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & redist12_expX_uid6_fpMulTest_b_1_q);
+    expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & redist11_expY_uid7_fpMulTest_b_1_q);
     expSum_uid44_fpMulTest_clkproc: PROCESS (clk, areset)
     BEGIN
         IF (areset = '1') THEN
@@ -406,10 +433,19 @@ begin
     END PROCESS;
     expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(5 downto 0);
 
-    -- expSumMBias_uid46_fpMulTest(SUB,45)@2
+    -- expSumMBias_uid46_fpMulTest(SUB,45)@2 + 1
     expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000" & expSum_uid44_fpMulTest_q));
     expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((8 downto 7 => biasInc_uid45_fpMulTest_q(6)) & biasInc_uid45_fpMulTest_q));
-    expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b));
+    expSumMBias_uid46_fpMulTest_clkproc: PROCESS (clk, areset)
+    BEGIN
+        IF (areset = '1') THEN
+            expSumMBias_uid46_fpMulTest_o <= (others => '0');
+        ELSIF (clk'EVENT AND clk = '1') THEN
+            IF (en = "1") THEN
+                expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b));
+            END IF;
+        END IF;
+    END PROCESS;
     expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(7 downto 0);
 
     -- fracRPostNormHigh_uid51_fpMulTest(BITSELECT,50)@2
@@ -420,102 +456,137 @@ begin
     fracRPostNormLow_uid52_fpMulTest_in <= osig_uid95_prod_uid47_fpMulTest_b(10 downto 0);
     fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(10 downto 0);
 
-    -- fracRPostNorm_uid53_fpMulTest(MUX,52)@2
+    -- fracRPostNorm_uid53_fpMulTest(MUX,52)@2 + 1
     fracRPostNorm_uid53_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b;
-    fracRPostNorm_uid53_fpMulTest_combproc: PROCESS (fracRPostNorm_uid53_fpMulTest_s, en, fracRPostNormLow_uid52_fpMulTest_b, fracRPostNormHigh_uid51_fpMulTest_b)
+    fracRPostNorm_uid53_fpMulTest_clkproc: PROCESS (clk, areset)
     BEGIN
-        CASE (fracRPostNorm_uid53_fpMulTest_s) IS
-            WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b;
-            WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b;
-            WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
-        END CASE;
+        IF (areset = '1') THEN
+            fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
+        ELSIF (clk'EVENT AND clk = '1') THEN
+            IF (en = "1") THEN
+                CASE (fracRPostNorm_uid53_fpMulTest_s) IS
+                    WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b;
+                    WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b;
+                    WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
+                END CASE;
+            END IF;
+        END IF;
     END PROCESS;
 
-    -- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@2
+    -- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@3
     expFracPreRound_uid55_fpMulTest_q <= expSumMBias_uid46_fpMulTest_q & fracRPostNorm_uid53_fpMulTest_q;
 
-    -- expFracRPostRounding_uid58_fpMulTest(ADD,57)@2
+    -- expFracRPostRounding_uid58_fpMulTest(ADD,57)@3
     expFracRPostRounding_uid58_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((20 downto 19 => expFracPreRound_uid55_fpMulTest_q(18)) & expFracPreRound_uid55_fpMulTest_q));
     expFracRPostRounding_uid58_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("00000000" & roundBitAndNormalizationOp_uid57_fpMulTest_q));
     expFracRPostRounding_uid58_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid58_fpMulTest_a) + SIGNED(expFracRPostRounding_uid58_fpMulTest_b));
     expFracRPostRounding_uid58_fpMulTest_q <= expFracRPostRounding_uid58_fpMulTest_o(19 downto 0);
 
-    -- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@2
+    -- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@3
     expRPreExcExt_uid60_fpMulTest_b <= STD_LOGIC_VECTOR(expFracRPostRounding_uid58_fpMulTest_q(19 downto 11));
 
-    -- redist0_expRPreExcExt_uid60_fpMulTest_b_1(DELAY,97)
-    redist0_expRPreExcExt_uid60_fpMulTest_b_1 : dspba_delay
+    -- redist1_expRPreExcExt_uid60_fpMulTest_b_1(DELAY,98)
+    redist1_expRPreExcExt_uid60_fpMulTest_b_1 : dspba_delay
     GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" )
-    PORT MAP ( xin => expRPreExcExt_uid60_fpMulTest_b, xout => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
+    PORT MAP ( xin => expRPreExcExt_uid60_fpMulTest_b, xout => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- expRPreExc_uid61_fpMulTest(BITSELECT,60)@3
-    expRPreExc_uid61_fpMulTest_in <= redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(4 downto 0);
+    -- expRPreExc_uid61_fpMulTest(BITSELECT,60)@4
+    expRPreExc_uid61_fpMulTest_in <= redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(4 downto 0);
     expRPreExc_uid61_fpMulTest_b <= expRPreExc_uid61_fpMulTest_in(4 downto 0);
 
-    -- expOvf_uid64_fpMulTest(COMPARE,63)@3
-    expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist0_expRPreExcExt_uid60_fpMulTest_b_1_q));
+    -- redist0_expRPreExc_uid61_fpMulTest_b_1(DELAY,97)
+    redist0_expRPreExc_uid61_fpMulTest_b_1 : dspba_delay
+    GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => expRPreExc_uid61_fpMulTest_b, xout => redist0_expRPreExc_uid61_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
+
+    -- expOvf_uid64_fpMulTest(COMPARE,63)@4
+    expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist1_expRPreExcExt_uid60_fpMulTest_b_1_q));
     expOvf_uid64_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000000" & cstAllOWE_uid10_fpMulTest_q));
     expOvf_uid64_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid64_fpMulTest_a) - SIGNED(expOvf_uid64_fpMulTest_b));
     expOvf_uid64_fpMulTest_n(0) <= not (expOvf_uid64_fpMulTest_o(10));
 
-    -- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@3
-    invExpXIsMax_uid35_fpMulTest_q <= not (redist4_expXIsMax_uid30_fpMulTest_q_2_q);
+    -- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@4
+    invExpXIsMax_uid35_fpMulTest_q <= not (redist6_expXIsMax_uid30_fpMulTest_q_3_q);
 
-    -- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@3
-    InvExpXIsZero_uid36_fpMulTest_q <= not (redist5_excZ_y_uid29_fpMulTest_q_2_q);
+    -- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@4
+    InvExpXIsZero_uid36_fpMulTest_q <= not (redist7_excZ_y_uid29_fpMulTest_q_3_q);
 
-    -- excR_y_uid37_fpMulTest(LOGICAL,36)@3
+    -- excR_y_uid37_fpMulTest(LOGICAL,36)@4
     excR_y_uid37_fpMulTest_q <= InvExpXIsZero_uid36_fpMulTest_q and invExpXIsMax_uid35_fpMulTest_q;
 
-    -- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@3
-    invExpXIsMax_uid21_fpMulTest_q <= not (redist7_expXIsMax_uid16_fpMulTest_q_2_q);
+    -- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@4
+    invExpXIsMax_uid21_fpMulTest_q <= not (redist9_expXIsMax_uid16_fpMulTest_q_3_q);
 
-    -- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@3
-    InvExpXIsZero_uid22_fpMulTest_q <= not (redist8_excZ_x_uid15_fpMulTest_q_2_q);
+    -- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@4
+    InvExpXIsZero_uid22_fpMulTest_q <= not (redist10_excZ_x_uid15_fpMulTest_q_3_q);
 
-    -- excR_x_uid23_fpMulTest(LOGICAL,22)@3
+    -- excR_x_uid23_fpMulTest(LOGICAL,22)@4
     excR_x_uid23_fpMulTest_q <= InvExpXIsZero_uid22_fpMulTest_q and invExpXIsMax_uid21_fpMulTest_q;
 
-    -- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@3
-    ExcROvfAndInReg_uid73_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n;
+    -- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@4 + 1
+    ExcROvfAndInReg_uid73_fpMulTest_qi <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n;
+    ExcROvfAndInReg_uid73_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => ExcROvfAndInReg_uid73_fpMulTest_qi, xout => ExcROvfAndInReg_uid73_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@3
-    excYRAndExcXI_uid72_fpMulTest_q <= excR_y_uid37_fpMulTest_q and excI_x_uid19_fpMulTest_q;
+    -- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@4 + 1
+    excYRAndExcXI_uid72_fpMulTest_qi <= excR_y_uid37_fpMulTest_q and excI_x_uid19_fpMulTest_q;
+    excYRAndExcXI_uid72_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excYRAndExcXI_uid72_fpMulTest_qi, xout => excYRAndExcXI_uid72_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@3
-    excXRAndExcYI_uid71_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excI_y_uid33_fpMulTest_q;
+    -- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@4 + 1
+    excXRAndExcYI_uid71_fpMulTest_qi <= excR_x_uid23_fpMulTest_q and excI_y_uid33_fpMulTest_q;
+    excXRAndExcYI_uid71_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excXRAndExcYI_uid71_fpMulTest_qi, xout => excXRAndExcYI_uid71_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@3
-    excXIAndExcYI_uid70_fpMulTest_q <= excI_x_uid19_fpMulTest_q and excI_y_uid33_fpMulTest_q;
+    -- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@4 + 1
+    excXIAndExcYI_uid70_fpMulTest_qi <= excI_x_uid19_fpMulTest_q and excI_y_uid33_fpMulTest_q;
+    excXIAndExcYI_uid70_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excXIAndExcYI_uid70_fpMulTest_qi, xout => excXIAndExcYI_uid70_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excRInf_uid74_fpMulTest(LOGICAL,73)@3
+    -- excRInf_uid74_fpMulTest(LOGICAL,73)@5
     excRInf_uid74_fpMulTest_q <= excXIAndExcYI_uid70_fpMulTest_q or excXRAndExcYI_uid71_fpMulTest_q or excYRAndExcXI_uid72_fpMulTest_q or ExcROvfAndInReg_uid73_fpMulTest_q;
 
-    -- expUdf_uid62_fpMulTest(COMPARE,61)@3
+    -- expUdf_uid62_fpMulTest(COMPARE,61)@4
     expUdf_uid62_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0000000000" & GND_q));
-    expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist0_expRPreExcExt_uid60_fpMulTest_b_1_q));
+    expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist1_expRPreExcExt_uid60_fpMulTest_b_1_q));
     expUdf_uid62_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid62_fpMulTest_a) - SIGNED(expUdf_uid62_fpMulTest_b));
     expUdf_uid62_fpMulTest_n(0) <= not (expUdf_uid62_fpMulTest_o(10));
 
-    -- excZC3_uid68_fpMulTest(LOGICAL,67)@3
-    excZC3_uid68_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n;
+    -- excZC3_uid68_fpMulTest(LOGICAL,67)@4 + 1
+    excZC3_uid68_fpMulTest_qi <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n;
+    excZC3_uid68_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excZC3_uid68_fpMulTest_qi, xout => excZC3_uid68_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@3
-    excYZAndExcXR_uid67_fpMulTest_q <= redist5_excZ_y_uid29_fpMulTest_q_2_q and excR_x_uid23_fpMulTest_q;
+    -- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@4 + 1
+    excYZAndExcXR_uid67_fpMulTest_qi <= redist7_excZ_y_uid29_fpMulTest_q_3_q and excR_x_uid23_fpMulTest_q;
+    excYZAndExcXR_uid67_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excYZAndExcXR_uid67_fpMulTest_qi, xout => excYZAndExcXR_uid67_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@3
-    excXZAndExcYR_uid66_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and excR_y_uid37_fpMulTest_q;
+    -- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@4 + 1
+    excXZAndExcYR_uid66_fpMulTest_qi <= redist10_excZ_x_uid15_fpMulTest_q_3_q and excR_y_uid37_fpMulTest_q;
+    excXZAndExcYR_uid66_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excXZAndExcYR_uid66_fpMulTest_qi, xout => excXZAndExcYR_uid66_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@3
-    excXZAndExcYZ_uid65_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and redist5_excZ_y_uid29_fpMulTest_q_2_q;
+    -- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@4 + 1
+    excXZAndExcYZ_uid65_fpMulTest_qi <= redist10_excZ_x_uid15_fpMulTest_q_3_q and redist7_excZ_y_uid29_fpMulTest_q_3_q;
+    excXZAndExcYZ_uid65_fpMulTest_delay : dspba_delay
+    GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+    PORT MAP ( xin => excXZAndExcYZ_uid65_fpMulTest_qi, xout => excXZAndExcYZ_uid65_fpMulTest_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- excRZero_uid69_fpMulTest(LOGICAL,68)@3
+    -- excRZero_uid69_fpMulTest(LOGICAL,68)@5
     excRZero_uid69_fpMulTest_q <= excXZAndExcYZ_uid65_fpMulTest_q or excXZAndExcYR_uid66_fpMulTest_q or excYZAndExcXR_uid67_fpMulTest_q or excZC3_uid68_fpMulTest_q;
 
-    -- concExc_uid79_fpMulTest(BITJOIN,78)@3
+    -- concExc_uid79_fpMulTest(BITJOIN,78)@5
     concExc_uid79_fpMulTest_q <= excRNaN_uid78_fpMulTest_q & excRInf_uid74_fpMulTest_q & excRZero_uid69_fpMulTest_q;
 
-    -- excREnc_uid80_fpMulTest(LOOKUP,79)@3
+    -- excREnc_uid80_fpMulTest(LOOKUP,79)@5
     excREnc_uid80_fpMulTest_combproc: PROCESS (concExc_uid79_fpMulTest_q)
     BEGIN
         -- Begin reserved scope level
@@ -534,13 +605,13 @@ begin
         -- End reserved scope level
     END PROCESS;
 
-    -- expRPostExc_uid89_fpMulTest(MUX,88)@3
+    -- expRPostExc_uid89_fpMulTest(MUX,88)@5
     expRPostExc_uid89_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
-    expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, en, cstAllZWE_uid12_fpMulTest_q, expRPreExc_uid61_fpMulTest_b, cstAllOWE_uid10_fpMulTest_q)
+    expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, en, cstAllZWE_uid12_fpMulTest_q, redist0_expRPreExc_uid61_fpMulTest_b_1_q, cstAllOWE_uid10_fpMulTest_q)
     BEGIN
         CASE (expRPostExc_uid89_fpMulTest_s) IS
             WHEN "00" => expRPostExc_uid89_fpMulTest_q <= cstAllZWE_uid12_fpMulTest_q;
-            WHEN "01" => expRPostExc_uid89_fpMulTest_q <= expRPreExc_uid61_fpMulTest_b;
+            WHEN "01" => expRPostExc_uid89_fpMulTest_q <= redist0_expRPreExc_uid61_fpMulTest_b_1_q;
             WHEN "10" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
             WHEN "11" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
             WHEN OTHERS => expRPostExc_uid89_fpMulTest_q <= (others => '0');
@@ -550,32 +621,32 @@ begin
     -- oneFracRPostExc2_uid81_fpMulTest(CONSTANT,80)
     oneFracRPostExc2_uid81_fpMulTest_q <= "0000000001";
 
-    -- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@2
+    -- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@3
     fracRPreExc_uid59_fpMulTest_in <= expFracRPostRounding_uid58_fpMulTest_q(10 downto 0);
     fracRPreExc_uid59_fpMulTest_b <= fracRPreExc_uid59_fpMulTest_in(10 downto 1);
 
-    -- redist1_fracRPreExc_uid59_fpMulTest_b_1(DELAY,98)
-    redist1_fracRPreExc_uid59_fpMulTest_b_1 : dspba_delay
-    GENERIC MAP ( width => 10, depth => 1, reset_kind => "ASYNC" )
-    PORT MAP ( xin => fracRPreExc_uid59_fpMulTest_b, xout => redist1_fracRPreExc_uid59_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset );
+    -- redist2_fracRPreExc_uid59_fpMulTest_b_2(DELAY,99)
+    redist2_fracRPreExc_uid59_fpMulTest_b_2 : dspba_delay
+    GENERIC MAP ( width => 10, depth => 2, reset_kind => "ASYNC" )
+    PORT MAP ( xin => fracRPreExc_uid59_fpMulTest_b, xout => redist2_fracRPreExc_uid59_fpMulTest_b_2_q, ena => en(0), clk => clk, aclr => areset );
 
-    -- fracRPostExc_uid84_fpMulTest(MUX,83)@3
+    -- fracRPostExc_uid84_fpMulTest(MUX,83)@5
     fracRPostExc_uid84_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
-    fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, en, cstZeroWF_uid11_fpMulTest_q, redist1_fracRPreExc_uid59_fpMulTest_b_1_q, oneFracRPostExc2_uid81_fpMulTest_q)
+    fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, en, cstZeroWF_uid11_fpMulTest_q, redist2_fracRPreExc_uid59_fpMulTest_b_2_q, oneFracRPostExc2_uid81_fpMulTest_q)
     BEGIN
         CASE (fracRPostExc_uid84_fpMulTest_s) IS
             WHEN "00" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
-            WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= redist1_fracRPreExc_uid59_fpMulTest_b_1_q;
+            WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= redist2_fracRPreExc_uid59_fpMulTest_b_2_q;
             WHEN "10" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
             WHEN "11" => fracRPostExc_uid84_fpMulTest_q <= oneFracRPostExc2_uid81_fpMulTest_q;
             WHEN OTHERS => fracRPostExc_uid84_fpMulTest_q <= (others => '0');
         END CASE;
     END PROCESS;
 
-    -- R_uid92_fpMulTest(BITJOIN,91)@3
+    -- R_uid92_fpMulTest(BITJOIN,91)@5
     R_uid92_fpMulTest_q <= signRPostExc_uid91_fpMulTest_q & expRPostExc_uid89_fpMulTest_q & fracRPostExc_uid84_fpMulTest_q;
 
-    -- xOut(GPOUT,4)@3
+    -- xOut(GPOUT,4)@5
     q <= R_uid92_fpMulTest_q;
 
 END normal;
diff --git a/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl b/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl
index ed471bb..e597209 100644
--- a/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl
+++ b/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2023.10.21.20:27:56
+# ACDS 20.1 720 linux 2023.10.26.05:48:33
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
diff --git a/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh b/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh
index e4268b4..dd6a06c 100755
--- a/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh
+++ b/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2023.10.21.20:27:56
+# ACDS 20.1 720 linux 2023.10.26.05:48:33
 
 # ----------------------------------------
 # ncsim - auto-generated simulation script
@@ -106,7 +106,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2023.10.21.20:27:56
+# ACDS 20.1 720 linux 2023.10.26.05:48:33
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="ip_fp_mul"
diff --git a/ip/ip_fp_mul_sim/ip_fp_mul.vo b/ip/ip_fp_mul_sim/ip_fp_mul.vo
index a9b9007..6101c63 100644
--- a/ip/ip_fp_mul_sim/ip_fp_mul.vo
+++ b/ip/ip_fp_mul_sim/ip_fp_mul.vo
@@ -27,7 +27,7 @@
 
 //synopsys translate_off
 
-//synthesis_resources = lut 87 mux21 11 oper_add 5 oper_mult 1 oper_mux 17 
+//synthesis_resources = lut 141 mux21 11 oper_add 5 oper_mult 1 oper_mux 17 
 `timescale 1 ps / 1 ps
 module  ip_fp_mul
 	( 
@@ -44,19 +44,68 @@ module  ip_fp_mul
 	input   [0:0]  en;
 	output   [15:0]  q;
 
+	reg	n00i;
+	reg	n00l;
+	reg	n01i;
+	reg	n01l;
+	reg	n01O;
 	reg	n0ii;
+	reg	n0iiO;
 	reg	n0il;
+	reg	n0ili;
+	reg	n0ill;
+	reg	n0ilO;
 	reg	n0iO;
+	reg	n0iOi;
+	reg	n0iOl;
+	reg	n0iOO;
+	reg	n0l0i;
+	reg	n0l0l;
+	reg	n0l0O;
+	reg	n0l1i;
+	reg	n0l1l;
+	reg	n0l1O;
 	reg	n0li;
+	reg	n0lii;
+	reg	n0lil;
+	reg	n0liO;
 	reg	n0ll;
+	reg	n0lli;
+	reg	n0lll;
+	reg	n0llO;
+	reg	n0lOi;
+	reg	n0lOl;
+	reg	n0lOO;
+	reg	n0O0i;
+	reg	n0O0l;
+	reg	n0O0O;
+	reg	n0O1i;
+	reg	n0O1l;
+	reg	n0O1O;
 	reg	n0Oi;
+	reg	n0Oii;
+	reg	n0Oil;
+	reg	n0OiO;
 	reg	n0Ol;
+	reg	n0Oli;
+	reg	n0Oll;
+	reg	n0OlO;
 	reg	n0OO;
+	reg	n0OOi;
+	reg	n0OOl;
+	reg	n0OOO;
+	reg	n11i;
 	reg	n1i;
 	reg	n1O;
+	reg	n1Oi;
+	reg	n1Ol;
+	reg	n1OO;
 	reg	ni00i;
 	reg	ni00l;
 	reg	ni00O;
+	reg	ni01i;
+	reg	ni01l;
+	reg	ni01O;
 	reg	ni0i;
 	reg	ni0ii;
 	reg	ni0il;
@@ -69,9 +118,24 @@ module  ip_fp_mul
 	reg	ni0Oi;
 	reg	ni0Ol;
 	reg	ni0OO;
+	reg	ni10i;
+	reg	ni10l;
+	reg	ni10O;
+	reg	ni11i;
+	reg	ni11l;
+	reg	ni11O;
 	reg	ni1i;
+	reg	ni1ii;
+	reg	ni1il;
+	reg	ni1iO;
 	reg	ni1l;
+	reg	ni1li;
+	reg	ni1ll;
+	reg	ni1lO;
 	reg	ni1O;
+	reg	ni1Oi;
+	reg	ni1Ol;
+	reg	ni1OO;
 	reg	nii0i;
 	reg	nii0l;
 	reg	nii0O;
@@ -89,29 +153,9 @@ module  ip_fp_mul
 	reg	niiO;
 	reg	niiOi;
 	reg	niiOl;
-	reg	niiOO;
-	reg	nil0i;
-	reg	nil0l;
-	reg	nil0O;
-	reg	nil1i;
-	reg	nil1l;
-	reg	nil1O;
 	reg	nili;
-	reg	nilii;
-	reg	nilil;
-	reg	niliO;
 	reg	nill;
-	reg	nilli;
-	reg	nilll;
-	reg	nillO;
 	reg	nilO;
-	reg	nilOi;
-	reg	nilOl;
-	reg	nilOO;
-	reg	niO0i;
-	reg	niO1i;
-	reg	niO1l;
-	reg	niO1O;
 	reg	niOi;
 	reg	niOl;
 	reg	niOO;
@@ -125,78 +169,136 @@ module  ip_fp_mul
 	reg	nlil;
 	reg	nliO;
 	reg	nlli;
+	reg	nllil;
 	reg	nlll;
 	reg	nllO;
+	reg	nlO0O;
 	reg	nlOi;
+	reg	nlOii;
+	reg	nlOil;
+	reg	nlOiO;
 	reg	nlOl;
+	reg	nlOli;
+	reg	nlOll;
 	reg	nlOlO;
 	reg	nlOO;
+	reg	nlOOi;
+	reg	nlOOl;
+	reg	nlOOO;
 	wire	wire_n1l_ENA;
-	wire	wire_n00i_dataout;
-	wire	wire_n00l_dataout;
-	wire	wire_n01i_dataout;
-	wire	wire_n01l_dataout;
-	wire	wire_n01O_dataout;
+	wire	wire_n10i_dataout;
+	wire	wire_n10l_dataout;
+	wire	wire_n10O_dataout;
+	wire	wire_n11l_dataout;
+	wire	wire_n11O_dataout;
+	wire	wire_n1ii_dataout;
+	wire	wire_n1il_dataout;
+	wire	wire_n1iO_dataout;
 	wire	wire_n1li_dataout;
 	wire	wire_n1ll_dataout;
 	wire	wire_n1lO_dataout;
-	wire	wire_n1Oi_dataout;
-	wire	wire_n1Ol_dataout;
-	wire	wire_n1OO_dataout;
 	wire  [9:0]   wire_n00O_o;
 	wire  [5:0]   wire_n0lO_o;
-	wire  [11:0]   wire_n1il_o;
-	wire  [20:0]   wire_n1iO_o;
-	wire  [11:0]   wire_nlOll_o;
+	wire  [11:0]   wire_nllii_o;
+	wire  [11:0]   wire_nlO0i_o;
+	wire  [20:0]   wire_nlO0l_o;
 	wire  [21:0]   wire_n0i_o;
-	wire  wire_nll0i_o;
-	wire  wire_nll0l_o;
-	wire  wire_nll0O_o;
-	wire  wire_nll1l_o;
-	wire  wire_nll1O_o;
-	wire  wire_nllii_o;
-	wire  wire_nllil_o;
-	wire  wire_nlliO_o;
-	wire  wire_nllli_o;
-	wire  wire_nllll_o;
-	wire  wire_nlllO_o;
-	wire  wire_nllOi_o;
-	wire  wire_nllOl_o;
-	wire  wire_nllOO_o;
-	wire  wire_nlO1i_o;
-	wire  wire_nlO1l_o;
-	wire  wire_nlO1O_o;
-	wire  ni01i;
-	wire  ni10i;
-	wire  ni10l;
-	wire  ni10O;
-	wire  ni11l;
-	wire  ni11O;
-	wire  ni1ii;
-	wire  ni1il;
-	wire  ni1iO;
-	wire  ni1li;
-	wire  ni1ll;
-	wire  ni1lO;
-	wire  ni1Oi;
-	wire  ni1Ol;
-	wire  ni1OO;
+	wire  wire_nl0lO_o;
+	wire  wire_nl0Oi_o;
+	wire  wire_nl0Ol_o;
+	wire  wire_nl0OO_o;
+	wire  wire_nli0i_o;
+	wire  wire_nli0l_o;
+	wire  wire_nli0O_o;
+	wire  wire_nli1i_o;
+	wire  wire_nli1l_o;
+	wire  wire_nli1O_o;
+	wire  wire_nliii_o;
+	wire  wire_nliil_o;
+	wire  wire_nliiO_o;
+	wire  wire_nlili_o;
+	wire  wire_nlill_o;
+	wire  wire_nlilO_o;
+	wire  wire_nliOi_o;
+	wire  n00il;
+	wire  n00iO;
+	wire  n00li;
+	wire  n00ll;
+	wire  n00lO;
+	wire  n00Oi;
+	wire  n00Ol;
+	wire  n00OO;
+	wire  n0i0i;
+	wire  n0i0l;
+	wire  n0i0O;
+	wire  n0i1i;
+	wire  n0i1l;
+	wire  n0i1O;
 
 	initial
 	begin
+		n00i = 0;
+		n00l = 0;
+		n01i = 0;
+		n01l = 0;
+		n01O = 0;
 		n0ii = 0;
+		n0iiO = 0;
 		n0il = 0;
+		n0ili = 0;
+		n0ill = 0;
+		n0ilO = 0;
 		n0iO = 0;
+		n0iOi = 0;
+		n0iOl = 0;
+		n0iOO = 0;
+		n0l0i = 0;
+		n0l0l = 0;
+		n0l0O = 0;
+		n0l1i = 0;
+		n0l1l = 0;
+		n0l1O = 0;
 		n0li = 0;
+		n0lii = 0;
+		n0lil = 0;
+		n0liO = 0;
 		n0ll = 0;
+		n0lli = 0;
+		n0lll = 0;
+		n0llO = 0;
+		n0lOi = 0;
+		n0lOl = 0;
+		n0lOO = 0;
+		n0O0i = 0;
+		n0O0l = 0;
+		n0O0O = 0;
+		n0O1i = 0;
+		n0O1l = 0;
+		n0O1O = 0;
 		n0Oi = 0;
+		n0Oii = 0;
+		n0Oil = 0;
+		n0OiO = 0;
 		n0Ol = 0;
+		n0Oli = 0;
+		n0Oll = 0;
+		n0OlO = 0;
 		n0OO = 0;
+		n0OOi = 0;
+		n0OOl = 0;
+		n0OOO = 0;
+		n11i = 0;
 		n1i = 0;
 		n1O = 0;
+		n1Oi = 0;
+		n1Ol = 0;
+		n1OO = 0;
 		ni00i = 0;
 		ni00l = 0;
 		ni00O = 0;
+		ni01i = 0;
+		ni01l = 0;
+		ni01O = 0;
 		ni0i = 0;
 		ni0ii = 0;
 		ni0il = 0;
@@ -209,9 +311,24 @@ module  ip_fp_mul
 		ni0Oi = 0;
 		ni0Ol = 0;
 		ni0OO = 0;
+		ni10i = 0;
+		ni10l = 0;
+		ni10O = 0;
+		ni11i = 0;
+		ni11l = 0;
+		ni11O = 0;
 		ni1i = 0;
+		ni1ii = 0;
+		ni1il = 0;
+		ni1iO = 0;
 		ni1l = 0;
+		ni1li = 0;
+		ni1ll = 0;
+		ni1lO = 0;
 		ni1O = 0;
+		ni1Oi = 0;
+		ni1Ol = 0;
+		ni1OO = 0;
 		nii0i = 0;
 		nii0l = 0;
 		nii0O = 0;
@@ -229,29 +346,9 @@ module  ip_fp_mul
 		niiO = 0;
 		niiOi = 0;
 		niiOl = 0;
-		niiOO = 0;
-		nil0i = 0;
-		nil0l = 0;
-		nil0O = 0;
-		nil1i = 0;
-		nil1l = 0;
-		nil1O = 0;
 		nili = 0;
-		nilii = 0;
-		nilil = 0;
-		niliO = 0;
 		nill = 0;
-		nilli = 0;
-		nilll = 0;
-		nillO = 0;
 		nilO = 0;
-		nilOi = 0;
-		nilOl = 0;
-		nilOO = 0;
-		niO0i = 0;
-		niO1i = 0;
-		niO1l = 0;
-		niO1O = 0;
 		niOi = 0;
 		niOl = 0;
 		niOO = 0;
@@ -265,30 +362,89 @@ module  ip_fp_mul
 		nlil = 0;
 		nliO = 0;
 		nlli = 0;
+		nllil = 0;
 		nlll = 0;
 		nllO = 0;
+		nlO0O = 0;
 		nlOi = 0;
+		nlOii = 0;
+		nlOil = 0;
+		nlOiO = 0;
 		nlOl = 0;
+		nlOli = 0;
+		nlOll = 0;
 		nlOlO = 0;
 		nlOO = 0;
+		nlOOi = 0;
+		nlOOl = 0;
+		nlOOO = 0;
 	end
 	always @ ( posedge clk or  posedge areset)
 	begin
 		if (areset == 1'b1) 
 		begin
+			n00i <= 0;
+			n00l <= 0;
+			n01i <= 0;
+			n01l <= 0;
+			n01O <= 0;
 			n0ii <= 0;
+			n0iiO <= 0;
 			n0il <= 0;
+			n0ili <= 0;
+			n0ill <= 0;
+			n0ilO <= 0;
 			n0iO <= 0;
+			n0iOi <= 0;
+			n0iOl <= 0;
+			n0iOO <= 0;
+			n0l0i <= 0;
+			n0l0l <= 0;
+			n0l0O <= 0;
+			n0l1i <= 0;
+			n0l1l <= 0;
+			n0l1O <= 0;
 			n0li <= 0;
+			n0lii <= 0;
+			n0lil <= 0;
+			n0liO <= 0;
 			n0ll <= 0;
+			n0lli <= 0;
+			n0lll <= 0;
+			n0llO <= 0;
+			n0lOi <= 0;
+			n0lOl <= 0;
+			n0lOO <= 0;
+			n0O0i <= 0;
+			n0O0l <= 0;
+			n0O0O <= 0;
+			n0O1i <= 0;
+			n0O1l <= 0;
+			n0O1O <= 0;
 			n0Oi <= 0;
+			n0Oii <= 0;
+			n0Oil <= 0;
+			n0OiO <= 0;
 			n0Ol <= 0;
+			n0Oli <= 0;
+			n0Oll <= 0;
+			n0OlO <= 0;
 			n0OO <= 0;
+			n0OOi <= 0;
+			n0OOl <= 0;
+			n0OOO <= 0;
+			n11i <= 0;
 			n1i <= 0;
 			n1O <= 0;
+			n1Oi <= 0;
+			n1Ol <= 0;
+			n1OO <= 0;
 			ni00i <= 0;
 			ni00l <= 0;
 			ni00O <= 0;
+			ni01i <= 0;
+			ni01l <= 0;
+			ni01O <= 0;
 			ni0i <= 0;
 			ni0ii <= 0;
 			ni0il <= 0;
@@ -301,9 +457,24 @@ module  ip_fp_mul
 			ni0Oi <= 0;
 			ni0Ol <= 0;
 			ni0OO <= 0;
+			ni10i <= 0;
+			ni10l <= 0;
+			ni10O <= 0;
+			ni11i <= 0;
+			ni11l <= 0;
+			ni11O <= 0;
 			ni1i <= 0;
+			ni1ii <= 0;
+			ni1il <= 0;
+			ni1iO <= 0;
 			ni1l <= 0;
+			ni1li <= 0;
+			ni1ll <= 0;
+			ni1lO <= 0;
 			ni1O <= 0;
+			ni1Oi <= 0;
+			ni1Ol <= 0;
+			ni1OO <= 0;
 			nii0i <= 0;
 			nii0l <= 0;
 			nii0O <= 0;
@@ -321,29 +492,9 @@ module  ip_fp_mul
 			niiO <= 0;
 			niiOi <= 0;
 			niiOl <= 0;
-			niiOO <= 0;
-			nil0i <= 0;
-			nil0l <= 0;
-			nil0O <= 0;
-			nil1i <= 0;
-			nil1l <= 0;
-			nil1O <= 0;
 			nili <= 0;
-			nilii <= 0;
-			nilil <= 0;
-			niliO <= 0;
 			nill <= 0;
-			nilli <= 0;
-			nilll <= 0;
-			nillO <= 0;
 			nilO <= 0;
-			nilOi <= 0;
-			nilOl <= 0;
-			nilOO <= 0;
-			niO0i <= 0;
-			niO1i <= 0;
-			niO1l <= 0;
-			niO1O <= 0;
 			niOi <= 0;
 			niOl <= 0;
 			niOO <= 0;
@@ -357,89 +508,143 @@ module  ip_fp_mul
 			nlil <= 0;
 			nliO <= 0;
 			nlli <= 0;
+			nllil <= 0;
 			nlll <= 0;
 			nllO <= 0;
+			nlO0O <= 0;
 			nlOi <= 0;
+			nlOii <= 0;
+			nlOil <= 0;
+			nlOiO <= 0;
 			nlOl <= 0;
+			nlOli <= 0;
+			nlOll <= 0;
 			nlOlO <= 0;
 			nlOO <= 0;
+			nlOOi <= 0;
+			nlOOl <= 0;
+			nlOOO <= 0;
 		end
 		else if  (wire_n1l_ENA == 1'b1) 
 		begin
+			n00i <= wire_n00O_o[8];
+			n00l <= wire_n0lO_o[0];
+			n01i <= wire_n00O_o[5];
+			n01l <= wire_n00O_o[6];
+			n01O <= wire_n00O_o[7];
 			n0ii <= wire_n0lO_o[1];
+			n0iiO <= n00Oi;
 			n0il <= wire_n0lO_o[2];
+			n0ili <= n0ill;
+			n0ill <= n0ilO;
+			n0ilO <= n0iiO;
 			n0iO <= wire_n0lO_o[3];
+			n0iOi <= a[10];
+			n0iOl <= a[11];
+			n0iOO <= a[12];
+			n0l0i <= n0l0l;
+			n0l0l <= n0l1O;
+			n0l0O <= b[10];
+			n0l1i <= a[13];
+			n0l1l <= a[14];
+			n0l1O <= n00lO;
 			n0li <= wire_n0lO_o[4];
+			n0lii <= b[11];
+			n0lil <= b[12];
+			n0liO <= b[13];
 			n0ll <= wire_n0lO_o[5];
+			n0lli <= b[14];
+			n0lll <= n00ll;
+			n0llO <= n0lOi;
+			n0lOi <= n0lll;
+			n0lOl <= n00li;
+			n0lOO <= n0O1i;
+			n0O0i <= n0O0l;
+			n0O0l <= n0O1O;
+			n0O0O <= n00il;
+			n0O1i <= n0O1l;
+			n0O1l <= n0lOl;
+			n0O1O <= n00iO;
 			n0Oi <= wire_n0i_o[9];
+			n0Oii <= n0Oil;
+			n0Oil <= n0O0O;
+			n0OiO <= ((n0i0O & n0llO) | (n0i0l & n0Oii));
 			n0Ol <= wire_n0i_o[10];
+			n0Oli <= ((~ n0lOO) & n0O0i);
+			n0Oll <= ((~ n0ili) & n0l0i);
+			n0OlO <= (a[15] ^ b[15]);
 			n0OO <= wire_n0i_o[11];
+			n0OOi <= n0OOl;
+			n0OOl <= n0OOO;
+			n0OOO <= ni11i;
+			n11i <= wire_n00O_o[1];
 			n1i <= a[9];
-			n1O <= ni1Oi;
-			ni00i <= ni1ii;
-			ni00l <= ni00O;
-			ni00O <= ni00i;
+			n1O <= n0i1O;
+			n1Oi <= wire_n00O_o[2];
+			n1Ol <= wire_n00O_o[3];
+			n1OO <= wire_n00O_o[4];
+			ni00i <= (n0i0l & n0i1i);
+			ni00l <= (n0i0O & n0i0l);
+			ni00O <= ((~ wire_nllii_o[11]) & (n0i1l & n0i1i));
+			ni01i <= ni1ii;
+			ni01l <= ((~ wire_nlO0i_o[11]) & (n0i1l & n0i1i));
+			ni01O <= (n0i0O & n0i1l);
 			ni0i <= wire_n0i_o[15];
-			ni0ii <= a[10];
-			ni0il <= a[11];
-			ni0iO <= a[12];
+			ni0ii <= (n0i1i & n0llO);
+			ni0il <= (n0i1l & n0Oii);
+			ni0iO <= (n0llO & n0Oii);
 			ni0l <= wire_n0i_o[16];
-			ni0li <= a[13];
-			ni0ll <= a[14];
-			ni0lO <= ni10O;
+			ni0li <= nii0l;
+			ni0ll <= nii0O;
+			ni0lO <= niiii;
 			ni0O <= wire_n0i_o[17];
-			ni0Oi <= ni0lO;
-			ni0Ol <= b[10];
-			ni0OO <= b[11];
+			ni0Oi <= niiil;
+			ni0Ol <= niiiO;
+			ni0OO <= niili;
+			ni10i <= wire_nlO0l_o[12];
+			ni10l <= wire_nlO0l_o[13];
+			ni10O <= wire_nlO0l_o[14];
+			ni11i <= n0OlO;
+			ni11l <= nili;
+			ni11O <= wire_nlO0l_o[11];
 			ni1i <= wire_n0i_o[12];
+			ni1ii <= wire_nlO0l_o[15];
+			ni1il <= wire_nlO0l_o[16];
+			ni1iO <= wire_nlO0l_o[17];
 			ni1l <= wire_n0i_o[13];
+			ni1li <= wire_nlO0l_o[18];
+			ni1ll <= wire_nlO0l_o[19];
+			ni1lO <= ni11O;
 			ni1O <= wire_n0i_o[14];
-			nii0i <= ni10l;
-			nii0l <= nii0i;
-			nii0O <= ni10i;
-			nii1i <= b[12];
-			nii1l <= b[13];
-			nii1O <= b[14];
+			ni1Oi <= ni10i;
+			ni1Ol <= ni10l;
+			ni1OO <= ni10O;
+			nii0i <= niiOl;
+			nii0l <= wire_nlO0l_o[1];
+			nii0O <= wire_nlO0l_o[2];
+			nii1i <= niill;
+			nii1l <= niilO;
+			nii1O <= niiOi;
 			niii <= wire_n0i_o[18];
-			niiii <= niiil;
-			niiil <= nii0O;
-			niiiO <= ni11O;
+			niiii <= wire_nlO0l_o[3];
+			niiil <= wire_nlO0l_o[4];
+			niiiO <= wire_nlO0l_o[5];
 			niil <= wire_n0i_o[19];
-			niili <= niiiO;
-			niill <= ni11l;
-			niilO <= niill;
+			niili <= wire_nlO0l_o[6];
+			niill <= wire_nlO0l_o[7];
+			niilO <= wire_nlO0l_o[8];
 			niiO <= wire_n0i_o[20];
-			niiOi <= (a[15] ^ b[15]);
-			niiOl <= niiOO;
-			niiOO <= niiOi;
-			nil0i <= wire_n1iO_o[14];
-			nil0l <= wire_n1iO_o[15];
-			nil0O <= wire_n1iO_o[16];
-			nil1i <= wire_n1iO_o[11];
-			nil1l <= wire_n1iO_o[12];
-			nil1O <= wire_n1iO_o[13];
+			niiOi <= wire_nlO0l_o[9];
+			niiOl <= wire_nlO0l_o[10];
 			nili <= wire_n0i_o[21];
-			nilii <= wire_n1iO_o[17];
-			nilil <= wire_n1iO_o[18];
-			niliO <= wire_n1iO_o[19];
 			nill <= b[0];
-			nilli <= wire_n1iO_o[1];
-			nilll <= wire_n1iO_o[2];
-			nillO <= wire_n1iO_o[3];
 			nilO <= b[1];
-			nilOi <= wire_n1iO_o[4];
-			nilOl <= wire_n1iO_o[5];
-			nilOO <= wire_n1iO_o[6];
-			niO0i <= wire_n1iO_o[10];
-			niO1i <= wire_n1iO_o[7];
-			niO1l <= wire_n1iO_o[8];
-			niO1O <= wire_n1iO_o[9];
 			niOi <= b[2];
 			niOl <= b[3];
 			niOO <= b[4];
 			nl0i <= b[8];
 			nl0l <= b[9];
-			nl0O <= ni1Oi;
+			nl0O <= n0i1O;
 			nl1i <= b[5];
 			nl1l <= b[6];
 			nl1O <= b[7];
@@ -447,30 +652,40 @@ module  ip_fp_mul
 			nlil <= a[1];
 			nliO <= a[2];
 			nlli <= a[3];
+			nllil <= wire_n11l_dataout;
 			nlll <= a[4];
 			nllO <= a[5];
+			nlO0O <= wire_n11O_dataout;
 			nlOi <= a[6];
+			nlOii <= wire_n10i_dataout;
+			nlOil <= wire_n10l_dataout;
+			nlOiO <= wire_n10O_dataout;
 			nlOl <= a[7];
-			nlOlO <= wire_n0lO_o[0];
+			nlOli <= wire_n1ii_dataout;
+			nlOll <= wire_n1il_dataout;
+			nlOlO <= wire_n1iO_dataout;
 			nlOO <= a[8];
+			nlOOi <= wire_n1li_dataout;
+			nlOOl <= wire_n1ll_dataout;
+			nlOOO <= wire_n1lO_dataout;
 		end
 	end
 	assign
 		wire_n1l_ENA = en[0];
-	assign		wire_n00i_dataout = ((~ nili) === 1'b1) ? niii : niil;
-	assign		wire_n00l_dataout = ((~ nili) === 1'b1) ? niil : niiO;
-	assign		wire_n01i_dataout = ((~ nili) === 1'b1) ? ni0i : ni0l;
-	assign		wire_n01l_dataout = ((~ nili) === 1'b1) ? ni0l : ni0O;
-	assign		wire_n01O_dataout = ((~ nili) === 1'b1) ? ni0O : niii;
-	assign		wire_n1li_dataout = ((~ nili) === 1'b1) ? n0Oi : n0Ol;
-	assign		wire_n1ll_dataout = ((~ nili) === 1'b1) ? n0Ol : n0OO;
-	assign		wire_n1lO_dataout = ((~ nili) === 1'b1) ? n0OO : ni1i;
-	assign		wire_n1Oi_dataout = ((~ nili) === 1'b1) ? ni1i : ni1l;
-	assign		wire_n1Ol_dataout = ((~ nili) === 1'b1) ? ni1l : ni1O;
-	assign		wire_n1OO_dataout = ((~ nili) === 1'b1) ? ni1O : ni0i;
+	assign		wire_n10i_dataout = ((~ nili) === 1'b1) ? n0OO : ni1i;
+	assign		wire_n10l_dataout = ((~ nili) === 1'b1) ? ni1i : ni1l;
+	assign		wire_n10O_dataout = ((~ nili) === 1'b1) ? ni1l : ni1O;
+	assign		wire_n11l_dataout = ((~ nili) === 1'b1) ? n0Oi : n0Ol;
+	assign		wire_n11O_dataout = ((~ nili) === 1'b1) ? n0Ol : n0OO;
+	assign		wire_n1ii_dataout = ((~ nili) === 1'b1) ? ni1O : ni0i;
+	assign		wire_n1il_dataout = ((~ nili) === 1'b1) ? ni0i : ni0l;
+	assign		wire_n1iO_dataout = ((~ nili) === 1'b1) ? ni0l : ni0O;
+	assign		wire_n1li_dataout = ((~ nili) === 1'b1) ? ni0O : niii;
+	assign		wire_n1ll_dataout = ((~ nili) === 1'b1) ? niii : niil;
+	assign		wire_n1lO_dataout = ((~ nili) === 1'b1) ? niil : niiO;
 	oper_add   n00O
 	( 
-	.a({{3{1'b0}}, n0ll, n0li, n0iO, n0il, n0ii, nlOlO, 1'b1}),
+	.a({{3{1'b0}}, n0ll, n0li, n0iO, n0il, n0ii, n00l, 1'b1}),
 	.b({{5{1'b1}}, {4{1'b0}}, 1'b1}),
 	.cin(1'b0),
 	.cout(),
@@ -482,8 +697,8 @@ module  ip_fp_mul
 		n00O.width_o = 10;
 	oper_add   n0lO
 	( 
-	.a({1'b0, ni0ll, ni0li, ni0iO, ni0il, ni0ii}),
-	.b({1'b0, nii1O, nii1l, nii1i, ni0OO, ni0Ol}),
+	.a({1'b0, n0l1l, n0l1i, n0iOO, n0iOl, n0iOi}),
+	.b({1'b0, n0lli, n0liO, n0lil, n0lii, n0l0O}),
 	.cin(1'b0),
 	.cout(),
 	.o(wire_n0lO_o));
@@ -492,42 +707,42 @@ module  ip_fp_mul
 		n0lO.width_a = 6,
 		n0lO.width_b = 6,
 		n0lO.width_o = 6;
-	oper_add   n1il
+	oper_add   nllii
 	( 
-	.a({{3{niliO}}, nilil, nilii, nil0O, nil0l, nil0i, nil1O, nil1l, nil1i, 1'b1}),
-	.b({{6{1'b1}}, {5{1'b0}}, 1'b1}),
+	.a({{3{(~ ni1ll)}}, (~ ni1li), (~ ni1iO), (~ ni1il), (~ ni1ii), (~ ni10O), (~ ni10l), (~ ni10i), (~ ni11O), 1'b1}),
+	.b({{11{1'b0}}, 1'b1}),
 	.cin(1'b0),
 	.cout(),
-	.o(wire_n1il_o));
+	.o(wire_nllii_o));
 	defparam
-		n1il.sgate_representation = 0,
-		n1il.width_a = 12,
-		n1il.width_b = 12,
-		n1il.width_o = 12;
-	oper_add   n1iO
+		nllii.sgate_representation = 0,
+		nllii.width_a = 12,
+		nllii.width_b = 12,
+		nllii.width_o = 12;
+	oper_add   nlO0i
 	( 
-	.a({{2{wire_n00O_o[8]}}, wire_n00O_o[8:1], wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout, wire_n1li_dataout}),
-	.b({{9{1'b0}}, nili, {10{1'b0}}, 1'b1}),
+	.a({{3{ni1ll}}, ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni10i, ni11O, 1'b1}),
+	.b({{6{1'b1}}, {5{1'b0}}, 1'b1}),
 	.cin(1'b0),
 	.cout(),
-	.o(wire_n1iO_o));
+	.o(wire_nlO0i_o));
 	defparam
-		n1iO.sgate_representation = 0,
-		n1iO.width_a = 21,
-		n1iO.width_b = 21,
-		n1iO.width_o = 21;
-	oper_add   nlOll
+		nlO0i.sgate_representation = 0,
+		nlO0i.width_a = 12,
+		nlO0i.width_b = 12,
+		nlO0i.width_o = 12;
+	oper_add   nlO0l
 	( 
-	.a({{3{(~ niliO)}}, (~ nilil), (~ nilii), (~ nil0O), (~ nil0l), (~ nil0i), (~ nil1O), (~ nil1l), (~ nil1i), 1'b1}),
-	.b({{11{1'b0}}, 1'b1}),
+	.a({{3{n00i}}, n01O, n01l, n01i, n1OO, n1Ol, n1Oi, n11i, nlOOO, nlOOl, nlOOi, nlOlO, nlOll, nlOli, nlOiO, nlOil, nlOii, nlO0O, nllil}),
+	.b({{9{1'b0}}, ni11l, {10{1'b0}}, 1'b1}),
 	.cin(1'b0),
 	.cout(),
-	.o(wire_nlOll_o));
+	.o(wire_nlO0l_o));
 	defparam
-		nlOll.sgate_representation = 0,
-		nlOll.width_a = 12,
-		nlOll.width_b = 12,
-		nlOll.width_o = 12;
+		nlO0l.sgate_representation = 0,
+		nlO0l.width_a = 21,
+		nlO0l.width_b = 21,
+		nlO0l.width_o = 21;
 	oper_mult   n0i
 	( 
 	.a({n1O, n1i, nlOO, nlOl, nlOi, nllO, nlll, nlli, nliO, nlil, nlii}),
@@ -538,159 +753,158 @@ module  ip_fp_mul
 		n0i.width_a = 11,
 		n0i.width_b = 11,
 		n0i.width_o = 22;
-	oper_mux   nll0i
+	oper_mux   nl0lO
 	( 
-	.data({{2{1'b0}}, nillO, 1'b0}),
-	.o(wire_nll0i_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({1'b1, 1'b0, ni0li, 1'b0}),
+	.o(wire_nl0lO_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nll0i.width_data = 4,
-		nll0i.width_sel = 2;
-	oper_mux   nll0l
+		nl0lO.width_data = 4,
+		nl0lO.width_sel = 2;
+	oper_mux   nl0Oi
 	( 
-	.data({{2{1'b0}}, nilOi, 1'b0}),
-	.o(wire_nll0l_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, ni0ll, 1'b0}),
+	.o(wire_nl0Oi_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nll0l.width_data = 4,
-		nll0l.width_sel = 2;
-	oper_mux   nll0O
+		nl0Oi.width_data = 4,
+		nl0Oi.width_sel = 2;
+	oper_mux   nl0Ol
 	( 
-	.data({{2{1'b0}}, nilOl, 1'b0}),
-	.o(wire_nll0O_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, ni0lO, 1'b0}),
+	.o(wire_nl0Ol_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nll0O.width_data = 4,
-		nll0O.width_sel = 2;
-	oper_mux   nll1l
+		nl0Ol.width_data = 4,
+		nl0Ol.width_sel = 2;
+	oper_mux   nl0OO
 	( 
-	.data({1'b1, 1'b0, nilli, 1'b0}),
-	.o(wire_nll1l_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, ni0Oi, 1'b0}),
+	.o(wire_nl0OO_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nll1l.width_data = 4,
-		nll1l.width_sel = 2;
-	oper_mux   nll1O
+		nl0OO.width_data = 4,
+		nl0OO.width_sel = 2;
+	oper_mux   nli0i
 	( 
-	.data({{2{1'b0}}, nilll, 1'b0}),
-	.o(wire_nll1O_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, nii1l, 1'b0}),
+	.o(wire_nli0i_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nll1O.width_data = 4,
-		nll1O.width_sel = 2;
-	oper_mux   nllii
+		nli0i.width_data = 4,
+		nli0i.width_sel = 2;
+	oper_mux   nli0l
 	( 
-	.data({{2{1'b0}}, nilOO, 1'b0}),
-	.o(wire_nllii_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, nii1O, 1'b0}),
+	.o(wire_nli0l_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nllii.width_data = 4,
-		nllii.width_sel = 2;
-	oper_mux   nllil
+		nli0l.width_data = 4,
+		nli0l.width_sel = 2;
+	oper_mux   nli0O
 	( 
-	.data({{2{1'b0}}, niO1i, 1'b0}),
-	.o(wire_nllil_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, nii0i, 1'b0}),
+	.o(wire_nli0O_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nllil.width_data = 4,
-		nllil.width_sel = 2;
-	oper_mux   nlliO
+		nli0O.width_data = 4,
+		nli0O.width_sel = 2;
+	oper_mux   nli1i
 	( 
-	.data({{2{1'b0}}, niO1l, 1'b0}),
-	.o(wire_nlliO_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, ni0Ol, 1'b0}),
+	.o(wire_nli1i_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nlliO.width_data = 4,
-		nlliO.width_sel = 2;
-	oper_mux   nllli
+		nli1i.width_data = 4,
+		nli1i.width_sel = 2;
+	oper_mux   nli1l
 	( 
-	.data({{2{1'b0}}, niO1O, 1'b0}),
-	.o(wire_nllli_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, ni0OO, 1'b0}),
+	.o(wire_nli1l_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nllli.width_data = 4,
-		nllli.width_sel = 2;
-	oper_mux   nllll
+		nli1l.width_data = 4,
+		nli1l.width_sel = 2;
+	oper_mux   nli1O
 	( 
-	.data({{2{1'b0}}, niO0i, 1'b0}),
-	.o(wire_nllll_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b0}}, nii1i, 1'b0}),
+	.o(wire_nli1O_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nllll.width_data = 4,
-		nllll.width_sel = 2;
-	oper_mux   nlllO
+		nli1O.width_data = 4,
+		nli1O.width_sel = 2;
+	oper_mux   nliii
 	( 
-	.data({{2{1'b1}}, nil1i, 1'b0}),
-	.o(wire_nlllO_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b1}}, ni1lO, 1'b0}),
+	.o(wire_nliii_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nlllO.width_data = 4,
-		nlllO.width_sel = 2;
-	oper_mux   nllOi
+		nliii.width_data = 4,
+		nliii.width_sel = 2;
+	oper_mux   nliil
 	( 
-	.data({{2{1'b1}}, nil1l, 1'b0}),
-	.o(wire_nllOi_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b1}}, ni1Oi, 1'b0}),
+	.o(wire_nliil_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nllOi.width_data = 4,
-		nllOi.width_sel = 2;
-	oper_mux   nllOl
+		nliil.width_data = 4,
+		nliil.width_sel = 2;
+	oper_mux   nliiO
 	( 
-	.data({{2{1'b1}}, nil1O, 1'b0}),
-	.o(wire_nllOl_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b1}}, ni1Ol, 1'b0}),
+	.o(wire_nliiO_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nllOl.width_data = 4,
-		nllOl.width_sel = 2;
-	oper_mux   nllOO
+		nliiO.width_data = 4,
+		nliiO.width_sel = 2;
+	oper_mux   nlili
 	( 
-	.data({{2{1'b1}}, nil0i, 1'b0}),
-	.o(wire_nllOO_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b1}}, ni1OO, 1'b0}),
+	.o(wire_nlili_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nllOO.width_data = 4,
-		nllOO.width_sel = 2;
-	oper_mux   nlO1i
+		nlili.width_data = 4,
+		nlili.width_sel = 2;
+	oper_mux   nlill
 	( 
-	.data({{2{1'b1}}, nil0l, 1'b0}),
-	.o(wire_nlO1i_o),
-	.sel({wire_nlO1O_o, wire_nlO1l_o}));
+	.data({{2{1'b1}}, ni01i, 1'b0}),
+	.o(wire_nlill_o),
+	.sel({wire_nliOi_o, wire_nlilO_o}));
 	defparam
-		nlO1i.width_data = 4,
-		nlO1i.width_sel = 2;
-	oper_mux   nlO1l
+		nlill.width_data = 4,
+		nlill.width_sel = 2;
+	oper_mux   nlilO
 	( 
 	.data({{3{1'b0}}, 1'b1}),
-	.o(wire_nlO1l_o),
-	.sel({ni1iO, ni1il}));
+	.o(wire_nlilO_o),
+	.sel({n00OO, n00Ol}));
 	defparam
-		nlO1l.width_data = 4,
-		nlO1l.width_sel = 2;
-	oper_mux   nlO1O
+		nlilO.width_data = 4,
+		nlilO.width_sel = 2;
+	oper_mux   nliOi
 	( 
 	.data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}}),
-	.o(wire_nlO1O_o),
-	.sel({ni1Ol, ni1iO, ni1il}));
+	.o(wire_nliOi_o),
+	.sel({n0i0i, n00OO, n00Ol}));
 	defparam
-		nlO1O.width_data = 8,
-		nlO1O.width_sel = 3;
+		nliOi.width_data = 8,
+		nliOi.width_sel = 3;
 	assign
-		ni01i = (ni00l & ni0Oi),
-		ni10i = ((((((((((~ b[0]) & (~ b[1])) & (~ b[2])) & (~ b[3])) & (~ b[4])) & (~ b[5])) & (~ b[6])) & (~ b[7])) & (~ b[8])) & (~ b[9])),
-		ni10l = (((((~ nii1O) & (~ nii1l)) & (~ nii1i)) & (~ ni0OO)) & (~ ni0Ol)),
-		ni10O = ((((ni0ll & ni0li) & ni0iO) & ni0il) & ni0ii),
-		ni11l = (((((~ ni0ll) & (~ ni0li)) & (~ ni0iO)) & (~ ni0il)) & (~ ni0ii)),
-		ni11O = ((((nii1O & nii1l) & nii1i) & ni0OO) & ni0Ol),
-		ni1ii = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])),
-		ni1il = ((ni1li & (~ wire_nlOll_o[11])) | ((ni1ll & nii0l) | ((ni1lO & niilO) | (nii0l & niilO)))),
-		ni1iO = (((~ wire_n1il_o[11]) & ni1li) | ((ni01i & ni1lO) | ((ni1OO & ni1ll) | (ni01i & ni1OO)))),
-		ni1li = (ni1lO & ni1ll),
-		ni1ll = ((~ ni0Oi) & (~ niilO)),
-		ni1lO = ((~ nii0l) & (~ niili)),
-		ni1Oi = 1'b1,
-		ni1Ol = (((ni01i & nii0l) | (ni1OO & niilO)) | (((~ niiii) & niili) | ((~ ni00l) & ni0Oi))),
-		ni1OO = (niiii & niili),
-		q = {((~ ni1Ol) & niiOl), wire_nlO1i_o, wire_nllOO_o, wire_nllOl_o, wire_nllOi_o, wire_nlllO_o, wire_nllll_o, wire_nllli_o, wire_nlliO_o, wire_nllil_o, wire_nllii_o, wire_nll0O_o, wire_nll0l_o, wire_nll0i_o, wire_nll1O_o, wire_nll1l_o};
+		n00il = (((((~ n0l1l) & (~ n0l1i)) & (~ n0iOO)) & (~ n0iOl)) & (~ n0iOi)),
+		n00iO = ((((n0lli & n0liO) & n0lil) & n0lii) & n0l0O),
+		n00li = ((((((((((~ b[0]) & (~ b[1])) & (~ b[2])) & (~ b[3])) & (~ b[4])) & (~ b[5])) & (~ b[6])) & (~ b[7])) & (~ b[8])) & (~ b[9])),
+		n00ll = (((((~ n0lli) & (~ n0liO)) & (~ n0lil)) & (~ n0lii)) & (~ n0l0O)),
+		n00lO = ((((n0l1l & n0l1i) & n0iOO) & n0iOl) & n0iOi),
+		n00Oi = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])),
+		n00Ol = (((ni0il | ni0iO) | ni0ii) | ni00O),
+		n00OO = (((ni00i | ni00l) | ni01O) | ni01l),
+		n0i0i = ((n0Oli | n0Oll) | n0OiO),
+		n0i0l = (n0lOO & n0O0i),
+		n0i0O = (n0ili & n0l0i),
+		n0i1i = ((~ n0l0i) & (~ n0Oii)),
+		n0i1l = ((~ n0llO) & (~ n0O0i)),
+		n0i1O = 1'b1,
+		q = {((~ n0i0i) & n0OOi), wire_nlill_o, wire_nlili_o, wire_nliiO_o, wire_nliil_o, wire_nliii_o, wire_nli0O_o, wire_nli0l_o, wire_nli0i_o, wire_nli1O_o, wire_nli1l_o, wire_nli1i_o, wire_nl0OO_o, wire_nl0Ol_o, wire_nl0Oi_o, wire_nl0lO_o};
 endmodule //ip_fp_mul
 //synopsys translate_on
 //VALID FILE
diff --git a/ip/ip_fp_mul_sim/mentor/msim_setup.tcl b/ip/ip_fp_mul_sim/mentor/msim_setup.tcl
index 14c829b..7cd5cfa 100644
--- a/ip/ip_fp_mul_sim/mentor/msim_setup.tcl
+++ b/ip/ip_fp_mul_sim/mentor/msim_setup.tcl
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2023.10.21.20:27:56
+# ACDS 20.1 720 linux 2023.10.26.05:48:32
 
 # ----------------------------------------
 # Initialize variables
diff --git a/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh b/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh
index 6bf2ad9..57f942b 100755
--- a/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh
+++ b/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2023.10.21.20:27:56
+# ACDS 20.1 720 linux 2023.10.26.05:48:33
 
 # ----------------------------------------
 # vcs - auto-generated simulation script
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2023.10.21.20:27:56
+# ACDS 20.1 720 linux 2023.10.26.05:48:33
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="ip_fp_mul"
diff --git a/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh
index 8f56686..fb41af0 100755
--- a/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh
+++ b/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2023.10.21.20:27:56
+# ACDS 20.1 720 linux 2023.10.26.05:48:33
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,7 +107,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2023.10.21.20:27:56
+# ACDS 20.1 720 linux 2023.10.26.05:48:33
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="ip_fp_mul"