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authorAlejandro Soto <alejandro@34project.org>2023-10-20 22:59:27 -0600
committerAlejandro Soto <alejandro@34project.org>2023-10-20 23:10:55 -0600
commit1b5eeb9a949272232ff543f684c7be62d31d0d40 (patch)
tree67e4e7b20f0d38b675058bbb32690ab782369d68 /ip/ip_fp_mul
parent8eba2720083d49bf6550efb35f32c8fbdd2ef975 (diff)
ip: add ip_fp_add, ip_fp_mul
Diffstat (limited to '')
-rw-r--r--ip/ip_fp_mul.cmp10
-rw-r--r--ip/ip_fp_mul.qip86
-rw-r--r--ip/ip_fp_mul.sip6
-rw-r--r--ip/ip_fp_mul.spd6
-rw-r--r--ip/ip_fp_mul.v92
-rw-r--r--ip/ip_fp_mul/dspba_library.vhd377
-rw-r--r--ip/ip_fp_mul/dspba_library_package.vhd72
-rw-r--r--ip/ip_fp_mul/ip_fp_mul_0002.vhd679
-rw-r--r--ip/ip_fp_mul_sim.f1
-rw-r--r--ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl278
-rw-r--r--ip/ip_fp_mul_sim/cadence/cds.lib19
-rw-r--r--ip/ip_fp_mul_sim/cadence/hdl.var2
-rwxr-xr-xip/ip_fp_mul_sim/cadence/ncsim_setup.sh195
-rw-r--r--ip/ip_fp_mul_sim/ip_fp_mul.vo1592
-rw-r--r--ip/ip_fp_mul_sim/mentor/msim_setup.tcl272
-rwxr-xr-xip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh152
-rw-r--r--ip/ip_fp_mul_sim/synopsys/vcsmx/synopsys_sim.setup13
-rwxr-xr-xip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh195
18 files changed, 4047 insertions, 0 deletions
diff --git a/ip/ip_fp_mul.cmp b/ip/ip_fp_mul.cmp
new file mode 100644
index 0000000..f2c0a07
--- /dev/null
+++ b/ip/ip_fp_mul.cmp
@@ -0,0 +1,10 @@
+ component ip_fp_mul is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ areset : in std_logic := 'X'; -- reset
+ a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
+ b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
+ q : out std_logic_vector(31 downto 0) -- q
+ );
+ end component ip_fp_mul;
+
diff --git a/ip/ip_fp_mul.qip b/ip/ip_fp_mul.qip
new file mode 100644
index 0000000..043d6a2
--- /dev/null
+++ b/ip/ip_fp_mul.qip
@@ -0,0 +1,86 @@
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_TOOL_NAME "altera_fp_functions"
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "ip_fp_mul" -name MISC_FILE [file join $::quartus(qip_path) "ip_fp_mul.cmp"]
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_COMPONENT_NAME "aXBfZnBfbXVs"
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_COMPONENT_DISPLAY_NAME "RlBfRlVOQ1RJT05TIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "ip_fp_mul" -library "ip_fp_mul" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_NAME "aXBfZnBfbXVsXzAwMDI="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_DISPLAY_NAME "RlBfRlVOQ1RJT05TIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05fRkFNSUxZ::QVJJVEg=::RmFtaWx5"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "QVJJVEhfZnVuY3Rpb24=::TVVM::TmFtZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Q09OVkVSVF9mdW5jdGlvbg==::RlhQX0ZQ::TmFtZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "QUxMX2Z1bmN0aW9u::QURE::TmFtZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "RVhQX0xPR19mdW5jdGlvbg==::RVhQRQ==::TmFtZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "VFJJR19mdW5jdGlvbg==::U0lO::TmFtZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Q09NUEFSRV9mdW5jdGlvbg==::TUlO::TmFtZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Uk9PVFNfZnVuY3Rpb24=::U1FSVA==::TmFtZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZGZ1bmN0aW9u::TVVM::ZGVyaXZlZGZ1bmN0aW9u"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::Rm9ybWF0"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::OA==::RXhwb25lbnQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::OA==::ZnBfZXhwX2Rlcml2ZWQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MjM=::TWFudGlzc2E="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MjM=::ZnBfbWFuX2Rlcml2ZWQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MjAw::VGFyZ2V0"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Mg==::VGFyZ2V0"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::ZnJlcXVlbmN5::R29hbA=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "dXNlX3JvdW5kaW5nX21vZGU=::dHJ1ZQ==::dXNlX3JvdW5kaW5nX21vZGU="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZmFpdGhmdWxfcm91bmRpbmc=::dHJ1ZQ==::UmVsYXggcm91bmRpbmcgdG8gcm91bmQgdXAgb3IgZG93biB0byByZWR1Y2UgcmVzb3VyY2UgdXNhZ2U="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::ZmFsc2U=::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZGl2aWRlX3R5cGU=::MA==::TWV0aG9k"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0X3NpZ25hbF9lbmFibGU=::ZmFsc2U=::VXNlIFNlbGVjdCBTaWduYWw="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2NhbGVfYnlfcGk=::ZmFsc2U=::UmVwcmVzZW50IGFuZ2xlIGFzIG11bHRpcGxlIG9mIFBp"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2lucHV0cw==::Mg==::SW5wdXQgVmVjdG9yIERpbWVuc2lvbg=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "dHJpZ19ub19yYW5nZV9yZWR1Y3Rpb24=::ZmFsc2U=::SW5wdXRzIGFyZSB3aXRoaW4gcmFuZ2UgLTJwaSB0byArMnBp"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cmVwb3J0X3Jlc291cmNlc190b194bWw=::ZmFsc2U=::cmVwb3J0X3Jlc291cmNlc190b194bWw="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::Ng==::bGF0ZW5jeV9mZWVkYmFjaw=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cF9kZXJpdmVk::OA==::ZnBfb3V0X2V4cF9kZXJpdmVk"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbg==::MjM=::T3V0cHV0IE1hbnRpc3Nh"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbl9kZXJpdmVk::OA==::ZnBfb3V0X21hbl9kZXJpdmVk"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZm9ybWF0::c2luZ2xl::SW5wdXQgRm9ybWF0"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhw::OA==::SW5wdXQgRXhwb25lbnQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhwX2Rlcml2ZWQ=::OA==::ZnBfaW5fZXhwX2Rlcml2ZWQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFu::MjM=::SW5wdXQgTWFudGlzc2E="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFuX2Rlcml2ZWQ=::OA==::ZnBfaW5fbWFuX2Rlcml2ZWQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2hhcmRfZnA=::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::Mg==::TXVsdGlwbGllcw=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MjQ2::TFVUcw=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ=="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=::Nw==::c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU="
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "dmFsaWRhdGlvbl9mYWlsZWQ=::ZmFsc2U=::dmFsaWRhdGlvbl9mYWlsZWQ="
+
+set_global_assignment -library "ip_fp_mul" -name VERILOG_FILE [file join $::quartus(qip_path) "ip_fp_mul.v"]
+set_global_assignment -library "ip_fp_mul" -name VHDL_FILE [file join $::quartus(qip_path) "ip_fp_mul/dspba_library_package.vhd"]
+set_global_assignment -library "ip_fp_mul" -name VHDL_FILE [file join $::quartus(qip_path) "ip_fp_mul/dspba_library.vhd"]
+set_global_assignment -library "ip_fp_mul" -name VHDL_FILE [file join $::quartus(qip_path) "ip_fp_mul/ip_fp_mul_0002.vhd"]
+
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_TOOL_NAME "altera_fp_functions"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_TOOL_ENV "mwpim"
diff --git a/ip/ip_fp_mul.sip b/ip/ip_fp_mul.sip
new file mode 100644
index 0000000..3971fde
--- /dev/null
+++ b/ip/ip_fp_mul.sip
@@ -0,0 +1,6 @@
+set_global_assignment -entity "ip_fp_mul" -library "lib_ip_fp_mul" -name IP_TOOL_NAME "altera_fp_functions"
+set_global_assignment -entity "ip_fp_mul" -library "lib_ip_fp_mul" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "ip_fp_mul" -library "lib_ip_fp_mul" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_ip_fp_mul" -name SPD_FILE [file join $::quartus(sip_path) "ip_fp_mul.spd"]
+
+set_global_assignment -library "lib_ip_fp_mul" -name MISC_FILE [file join $::quartus(sip_path) "ip_fp_mul_sim/ip_fp_mul.vo"]
diff --git a/ip/ip_fp_mul.spd b/ip/ip_fp_mul.spd
new file mode 100644
index 0000000..3e1d3ed
--- /dev/null
+++ b/ip/ip_fp_mul.spd
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file path="ip_fp_mul_sim/ip_fp_mul.vo" type="VERILOG" />
+ <topLevel name="ip_fp_mul" />
+ <deviceFamily name="cyclonev" />
+</simPackage>
diff --git a/ip/ip_fp_mul.v b/ip/ip_fp_mul.v
new file mode 100644
index 0000000..9585ce3
--- /dev/null
+++ b/ip/ip_fp_mul.v
@@ -0,0 +1,92 @@
+// megafunction wizard: %FP_FUNCTIONS Intel FPGA IP v20.1%
+// GENERATION: XML
+// ip_fp_mul.v
+
+// Generated using ACDS version 20.1 720
+
+`timescale 1 ps / 1 ps
+module ip_fp_mul (
+ input wire clk, // clk.clk
+ input wire areset, // areset.reset
+ input wire [31:0] a, // a.a
+ input wire [31:0] b, // b.b
+ output wire [31:0] q // q.q
+ );
+
+ ip_fp_mul_0002 ip_fp_mul_inst (
+ .clk (clk), // clk.clk
+ .areset (areset), // areset.reset
+ .a (a), // a.a
+ .b (b), // b.b
+ .q (q) // q.q
+ );
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+// Generated by Altera MegaWizard Launcher Utility version 1.0
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+// Copyright (C) 1991-2023 Altera Corporation
+// Any megafunction design, and related net list (encrypted or decrypted),
+// support information, device programming or simulation file, and any other
+// associated documentation or information provided by Altera or a partner
+// under Altera's Megafunction Partnership Program may be used only to
+// program PLD devices (but not masked PLD devices) from Altera. Any other
+// use of such megafunction design, net list, support information, device
+// programming or simulation file, or any other related documentation or
+// information is prohibited for any other purpose, including, but not
+// limited to modification, reverse engineering, de-compiling, or use with
+// any other silicon devices, unless such use is explicitly licensed under
+// a separate agreement with Altera or a megafunction partner. Title to
+// the intellectual property, including patents, copyrights, trademarks,
+// trade secrets, or maskworks, embodied in any such megafunction design,
+// net list, support information, device programming or simulation file, or
+// any other related documentation or information provided by Altera or a
+// megafunction partner, remains with Altera, the megafunction partner, or
+// their respective licensors. No other licenses, including any licenses
+// needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_fp_functions" version="20.1" >
+// Retrieval info: <generic name="FUNCTION_FAMILY" value="ARITH" />
+// Retrieval info: <generic name="ARITH_function" value="MUL" />
+// Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
+// Retrieval info: <generic name="ALL_function" value="ADD" />
+// Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
+// Retrieval info: <generic name="TRIG_function" value="SIN" />
+// Retrieval info: <generic name="COMPARE_function" value="MIN" />
+// Retrieval info: <generic name="ROOTS_function" value="SQRT" />
+// Retrieval info: <generic name="fp_format" value="single" />
+// Retrieval info: <generic name="fp_exp" value="8" />
+// Retrieval info: <generic name="fp_man" value="23" />
+// Retrieval info: <generic name="exponent_width" value="23" />
+// Retrieval info: <generic name="frequency_target" value="200" />
+// Retrieval info: <generic name="latency_target" value="2" />
+// Retrieval info: <generic name="performance_goal" value="frequency" />
+// Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
+// Retrieval info: <generic name="faithful_rounding" value="true" />
+// Retrieval info: <generic name="gen_enable" value="false" />
+// Retrieval info: <generic name="divide_type" value="0" />
+// Retrieval info: <generic name="select_signal_enable" value="false" />
+// Retrieval info: <generic name="scale_by_pi" value="false" />
+// Retrieval info: <generic name="number_of_inputs" value="2" />
+// Retrieval info: <generic name="trig_no_range_reduction" value="false" />
+// Retrieval info: <generic name="report_resources_to_xml" value="false" />
+// Retrieval info: <generic name="fxpt_width" value="32" />
+// Retrieval info: <generic name="fxpt_fraction" value="0" />
+// Retrieval info: <generic name="fxpt_sign" value="1" />
+// Retrieval info: <generic name="fp_out_format" value="single" />
+// Retrieval info: <generic name="fp_out_exp" value="8" />
+// Retrieval info: <generic name="fp_out_man" value="23" />
+// Retrieval info: <generic name="fp_in_format" value="single" />
+// Retrieval info: <generic name="fp_in_exp" value="8" />
+// Retrieval info: <generic name="fp_in_man" value="23" />
+// Retrieval info: <generic name="enable_hard_fp" value="true" />
+// Retrieval info: <generic name="manual_dsp_planning" value="true" />
+// Retrieval info: <generic name="forceRegisters" value="1111" />
+// Retrieval info: <generic name="selected_device_family" value="Cyclone V" />
+// Retrieval info: <generic name="selected_device_speedgrade" value="7" />
+// Retrieval info: </instance>
+// IPFS_FILES : ip_fp_mul.vo
+// RELATED_FILES: ip_fp_mul.v, dspba_library_package.vhd, dspba_library.vhd, ip_fp_mul_0002.vhd
diff --git a/ip/ip_fp_mul/dspba_library.vhd b/ip/ip_fp_mul/dspba_library.vhd
new file mode 100644
index 0000000..c38c661
--- /dev/null
+++ b/ip/ip_fp_mul/dspba_library.vhd
@@ -0,0 +1,377 @@
+-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files any of the foregoing device programming or simulation files), and
+-- any associated documentation or information are expressly subject to the
+-- terms and conditions of the Intel FPGA Software License Agreement,
+-- Intel MegaCore Function License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for the sole
+-- purpose of programming logic devices manufactured by Intel and sold by
+-- Intel or its authorized distributors. Please refer to the applicable
+-- agreement for further details.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use work.dspba_library_package.all;
+
+entity dspba_delay is
+ generic (
+ width : natural := 8;
+ depth : natural := 1;
+ reset_high : std_logic := '1';
+ reset_kind : string := "ASYNC"
+ );
+ port (
+ clk : in std_logic;
+ aclr : in std_logic;
+ ena : in std_logic := '1';
+ xin : in std_logic_vector(width-1 downto 0);
+ xout : out std_logic_vector(width-1 downto 0)
+ );
+end dspba_delay;
+
+architecture delay of dspba_delay is
+ type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
+ signal delay_signals : delay_array;
+begin
+ delay_signals(depth) <= xin;
+
+ delay_block: if 0 < depth generate
+ begin
+ delay_loop: for i in depth-1 downto 0 generate
+ begin
+ async_reset: if reset_kind = "ASYNC" generate
+ process(clk, aclr)
+ begin
+ if aclr=reset_high then
+ delay_signals(i) <= (others => '0');
+ elsif clk'event and clk='1' then
+ if ena='1' then
+ delay_signals(i) <= delay_signals(i + 1);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ sync_reset: if reset_kind = "SYNC" generate
+ process(clk)
+ begin
+ if clk'event and clk='1' then
+ if aclr=reset_high then
+ delay_signals(i) <= (others => '0');
+ elsif ena='1' then
+ delay_signals(i) <= delay_signals(i + 1);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ no_reset: if reset_kind = "NONE" generate
+ process(clk)
+ begin
+ if clk'event and clk='1' then
+ if ena='1' then
+ delay_signals(i) <= delay_signals(i + 1);
+ end if;
+ end if;
+ end process;
+ end generate;
+ end generate;
+ end generate;
+
+ xout <= delay_signals(0);
+end delay;
+
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.dspba_library_package.all;
+
+entity dspba_sync_reg is
+ generic (
+ width1 : natural := 8;
+ init_value : std_logic_vector;
+ width2 : natural := 8;
+ depth : natural := 2;
+ pulse_multiplier : natural := 1;
+ counter_width : natural := 8;
+ reset1_high : std_logic := '1';
+ reset2_high : std_logic := '1';
+ reset_kind : string := "ASYNC"
+ );
+ port (
+ clk1 : in std_logic;
+ aclr1 : in std_logic;
+ ena : in std_logic_vector(0 downto 0);
+ xin : in std_logic_vector(width1-1 downto 0);
+ xout : out std_logic_vector(width1-1 downto 0);
+ clk2 : in std_logic;
+ aclr2 : in std_logic;
+ sxout : out std_logic_vector(width2-1 downto 0)
+ );
+end entity;
+
+architecture sync_reg of dspba_sync_reg is
+ type bit_array is array (depth-1 downto 0) of std_logic;
+
+ signal iclk_enable : std_logic;
+ signal iclk_data : std_logic_vector(width1-1 downto 0);
+ signal oclk_data : std_logic_vector(width2-1 downto 0);
+
+ -- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
+ -- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis
+ signal sync_regs : bit_array;
+ attribute altera_attribute : string;
+ attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
+
+ signal oclk_enable : std_logic;
+
+ constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
+
+ signal counter : UNSIGNED(counter_width-1 downto 0);
+ signal ena_internal : std_logic;
+begin
+ oclk_enable <= sync_regs(depth-1);
+
+ no_multiplication: if pulse_multiplier=1 generate
+ ena_internal <= ena(0);
+ end generate;
+
+ async_reset: if reset_kind="ASYNC" generate
+
+ multiply_ena: if pulse_multiplier>1 generate
+ ena_internal <= '1' when counter>0 else ena(0);
+ process (clk1, aclr1)
+ begin
+ if aclr1=reset1_high then
+ counter <= (others => '0');
+ elsif clk1'event and clk1='1' then
+ if counter>0 then
+ if counter=pulse_multiplier-1 then
+ counter <= (others => '0');
+ else
+ counter <= counter + TO_UNSIGNED(1, counter_width);
+ end if;
+ else
+ if ena(0)='1' then
+ counter <= TO_UNSIGNED(1, counter_width);
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk1, aclr1)
+ begin
+ if aclr1=reset1_high then
+ iclk_enable <= '0';
+ iclk_data <= init_value_internal;
+ elsif clk1'event and clk1='1' then
+ iclk_enable <= ena_internal;
+ if ena(0)='1' then
+ iclk_data <= xin;
+ end if;
+ end if;
+ end process;
+
+ sync_reg_loop: for i in 0 to depth-1 generate
+ process (clk2, aclr2)
+ begin
+ if aclr2=reset2_high then
+ sync_regs(i) <= '0';
+ elsif clk2'event and clk2='1' then
+ if i>0 then
+ sync_regs(i) <= sync_regs(i-1);
+ else
+ sync_regs(i) <= iclk_enable;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk2, aclr2)
+ begin
+ if aclr2=reset2_high then
+ oclk_data <= init_value_internal(width2-1 downto 0);
+ elsif clk2'event and clk2='1' then
+ if oclk_enable='1' then
+ oclk_data <= iclk_data(width2-1 downto 0);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ sync_reset: if reset_kind="SYNC" generate
+
+ multiply_ena: if pulse_multiplier>1 generate
+ ena_internal <= '1' when counter>0 else ena(0);
+ process (clk1)
+ begin
+ if clk1'event and clk1='1' then
+ if aclr1=reset1_high then
+ counter <= (others => '0');
+ else
+ if counter>0 then
+ if counter=pulse_multiplier-1 then
+ counter <= (others => '0');
+ else
+ counter <= counter + TO_UNSIGNED(1, counter_width);
+ end if;
+ else
+ if ena(0)='1' then
+ counter <= TO_UNSIGNED(1, counter_width);
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk1)
+ begin
+ if clk1'event and clk1='1' then
+ if aclr1=reset1_high then
+ iclk_enable <= '0';
+ iclk_data <= init_value_internal;
+ else
+ iclk_enable <= ena_internal;
+ if ena(0)='1' then
+ iclk_data <= xin;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ sync_reg_loop: for i in 0 to depth-1 generate
+ process (clk2)
+ begin
+ if clk2'event and clk2='1' then
+ if aclr2=reset2_high then
+ sync_regs(i) <= '0';
+ else
+ if i>0 then
+ sync_regs(i) <= sync_regs(i-1);
+ else
+ sync_regs(i) <= iclk_enable;
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk2)
+ begin
+ if clk2'event and clk2='1' then
+ if aclr2=reset2_high then
+ oclk_data <= init_value_internal(width2-1 downto 0);
+ elsif oclk_enable='1' then
+ oclk_data <= iclk_data(width2-1 downto 0);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ none_reset: if reset_kind="NONE" generate
+
+ multiply_ena: if pulse_multiplier>1 generate
+ ena_internal <= '1' when counter>0 else ena(0);
+ process (clk1, aclr1)
+ begin
+ if clk1'event and clk1='1' then
+ if counter>0 then
+ if counter=pulse_multiplier-1 then
+ counter <= (others => '0');
+ else
+ counter <= counter + TO_UNSIGNED(1, counter_width);
+ end if;
+ else
+ if ena(0)='1' then
+ counter <= TO_UNSIGNED(1, counter_width);
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk1)
+ begin
+ if clk1'event and clk1='1' then
+ iclk_enable <= ena_internal;
+ if ena(0)='1' then
+ iclk_data <= xin;
+ end if;
+ end if;
+ end process;
+
+ sync_reg_loop: for i in 0 to depth-1 generate
+ process (clk2)
+ begin
+ if clk2'event and clk2='1' then
+ if i>0 then
+ sync_regs(i) <= sync_regs(i-1);
+ else
+ sync_regs(i) <= iclk_enable;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ process (clk2)
+ begin
+ if clk2'event and clk2='1' then
+ if oclk_enable='1' then
+ oclk_data <= iclk_data(width2-1 downto 0);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ xout <= iclk_data;
+ sxout <= oclk_data;
+
+end sync_reg;
+
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dspba_pipe is
+ generic(
+ num_bits : positive := 8;
+ num_stages : natural := 0;
+ init_value : std_logic := 'X'
+ );
+ port(
+ clk: in std_logic;
+ d : in std_logic_vector(num_bits-1 downto 0);
+ q : out std_logic_vector(num_bits-1 downto 0)
+ );
+end entity dspba_pipe;
+
+architecture rtl of dspba_pipe is
+ attribute altera_attribute : string;
+ attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off";
+
+ type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0);
+ signal stage_array : stage_array_type := (others => (others => init_value));
+begin
+ stage_array(0) <= d;
+
+ g_pipe : for i in 1 to num_stages generate
+ p_stage : process (clk) is
+ begin
+ if rising_edge(clk) then
+ stage_array(i) <= stage_array(i-1);
+ end if;
+ end process p_stage;
+ end generate g_pipe;
+
+ q <= stage_array(num_stages);
+
+end rtl;
+
diff --git a/ip/ip_fp_mul/dspba_library_package.vhd b/ip/ip_fp_mul/dspba_library_package.vhd
new file mode 100644
index 0000000..d03bca8
--- /dev/null
+++ b/ip/ip_fp_mul/dspba_library_package.vhd
@@ -0,0 +1,72 @@
+-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files any of the foregoing device programming or simulation files), and
+-- any associated documentation or information are expressly subject to the
+-- terms and conditions of the Intel FPGA Software License Agreement,
+-- Intel MegaCore Function License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for the sole
+-- purpose of programming logic devices manufactured by Intel and sold by
+-- Intel or its authorized distributors. Please refer to the applicable
+-- agreement for further details.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package dspba_library_package is
+
+ component dspba_delay is
+ generic (
+ width : natural := 8;
+ depth : natural := 1;
+ reset_high : std_logic := '1';
+ reset_kind : string := "ASYNC"
+ );
+ port (
+ clk : in std_logic;
+ aclr : in std_logic;
+ ena : in std_logic := '1';
+ xin : in std_logic_vector(width-1 downto 0);
+ xout : out std_logic_vector(width-1 downto 0)
+ );
+ end component;
+
+ component dspba_sync_reg is
+ generic (
+ width1 : natural := 8;
+ width2 : natural := 8;
+ depth : natural := 2;
+ init_value : std_logic_vector;
+ pulse_multiplier : natural := 1;
+ counter_width : natural := 8;
+ reset1_high : std_logic := '1';
+ reset2_high : std_logic := '1';
+ reset_kind : string := "ASYNC"
+ );
+ port (
+ clk1 : in std_logic;
+ aclr1 : in std_logic;
+ ena : in std_logic_vector(0 downto 0);
+ xin : in std_logic_vector(width1-1 downto 0);
+ xout : out std_logic_vector(width1-1 downto 0);
+ clk2 : in std_logic;
+ aclr2 : in std_logic;
+ sxout : out std_logic_vector(width2-1 downto 0)
+ );
+ end component;
+
+ component dspba_pipe is
+ generic(
+ num_bits : positive;
+ num_stages : natural;
+ init_value : std_logic := 'X'
+ );
+ port(
+ clk: in std_logic;
+ d : in std_logic_vector(num_bits-1 downto 0);
+ q : out std_logic_vector(num_bits-1 downto 0)
+ );
+ end component dspba_pipe;
+
+end dspba_library_package;
diff --git a/ip/ip_fp_mul/ip_fp_mul_0002.vhd b/ip/ip_fp_mul/ip_fp_mul_0002.vhd
new file mode 100644
index 0000000..456a1b5
--- /dev/null
+++ b/ip/ip_fp_mul/ip_fp_mul_0002.vhd
@@ -0,0 +1,679 @@
+-- -------------------------------------------------------------------------
+-- High Level Design Compiler for Intel(R) FPGAs Version 20.1 (Release Build #720)
+-- Quartus Prime development tool and MATLAB/Simulink Interface
+--
+-- Legal Notice: Copyright 2020 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files any of the foregoing (including device programming or simulation
+-- files), and any associated documentation or information are expressly
+-- subject to the terms and conditions of the Intel FPGA Software License
+-- Agreement, Intel MegaCore Function License Agreement, or other applicable
+-- license agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by Intel
+-- and sold by Intel or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+-- ---------------------------------------------------------------------------
+
+-- VHDL created from ip_fp_mul_0002
+-- VHDL created on Fri Oct 20 22:55:53 2023
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+use IEEE.MATH_REAL.all;
+use std.TextIO.all;
+use work.dspba_library_package.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.altera_syncram;
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+entity ip_fp_mul_0002 is
+ port (
+ a : in std_logic_vector(31 downto 0); -- float32_m23
+ b : in std_logic_vector(31 downto 0); -- float32_m23
+ q : out std_logic_vector(31 downto 0); -- float32_m23
+ clk : in std_logic;
+ areset : in std_logic
+ );
+end ip_fp_mul_0002;
+
+architecture normal of ip_fp_mul_0002 is
+
+ attribute altera_attribute : string;
+ attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
+
+ signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal expX_uid6_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
+ signal expY_uid7_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
+ signal signX_uid8_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
+ signal signY_uid9_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
+ signal cstAllOWE_uid10_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
+ signal cstZeroWF_uid11_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
+ signal cstAllZWE_uid12_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
+ signal frac_x_uid14_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
+ signal excZ_x_uid15_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excZ_x_uid15_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal expXIsMax_uid16_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal expXIsMax_uid16_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsZero_uid17_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsZero_uid17_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsNotZero_uid18_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsNotZero_uid18_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excI_x_uid19_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excI_x_uid19_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excN_x_uid20_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal invExpXIsMax_uid21_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal InvExpXIsZero_uid22_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excR_x_uid23_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excR_x_uid23_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal frac_y_uid28_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
+ signal excZ_y_uid29_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excZ_y_uid29_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal expXIsMax_uid30_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal expXIsMax_uid30_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsZero_uid31_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsZero_uid31_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsNotZero_uid32_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracXIsNotZero_uid32_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excI_y_uid33_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excI_y_uid33_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excN_y_uid34_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal invExpXIsMax_uid35_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal InvExpXIsZero_uid36_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excR_y_uid37_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excR_y_uid37_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal ofracX_uid40_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
+ signal ofracY_uid43_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
+ signal expSum_uid44_fpMulTest_a : STD_LOGIC_VECTOR (8 downto 0);
+ signal expSum_uid44_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
+ signal expSum_uid44_fpMulTest_o : STD_LOGIC_VECTOR (8 downto 0);
+ signal expSum_uid44_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
+ signal biasInc_uid45_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0);
+ signal expSumMBias_uid46_fpMulTest_a : STD_LOGIC_VECTOR (11 downto 0);
+ signal expSumMBias_uid46_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
+ signal expSumMBias_uid46_fpMulTest_o : STD_LOGIC_VECTOR (11 downto 0);
+ signal expSumMBias_uid46_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0);
+ signal signR_uid48_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal signR_uid48_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal normalizeBit_uid49_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracRPostNormHigh_uid51_fpMulTest_in : STD_LOGIC_VECTOR (24 downto 0);
+ signal fracRPostNormHigh_uid51_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
+ signal fracRPostNormLow_uid52_fpMulTest_in : STD_LOGIC_VECTOR (23 downto 0);
+ signal fracRPostNormLow_uid52_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
+ signal fracRPostNorm_uid53_fpMulTest_s : STD_LOGIC_VECTOR (0 downto 0);
+ signal fracRPostNorm_uid53_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
+ signal expFracPreRound_uid55_fpMulTest_q : STD_LOGIC_VECTOR (34 downto 0);
+ signal roundBitAndNormalizationOp_uid57_fpMulTest_q : STD_LOGIC_VECTOR (25 downto 0);
+ signal expFracRPostRounding_uid58_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0);
+ signal expFracRPostRounding_uid58_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0);
+ signal expFracRPostRounding_uid58_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0);
+ signal expFracRPostRounding_uid58_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0);
+ signal fracRPreExc_uid59_fpMulTest_in : STD_LOGIC_VECTOR (23 downto 0);
+ signal fracRPreExc_uid59_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
+ signal expRPreExcExt_uid60_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
+ signal expRPreExc_uid61_fpMulTest_in : STD_LOGIC_VECTOR (7 downto 0);
+ signal expRPreExc_uid61_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
+ signal expUdf_uid62_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
+ signal expUdf_uid62_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
+ signal expUdf_uid62_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
+ signal expUdf_uid62_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
+ signal expOvf_uid64_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
+ signal expOvf_uid64_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
+ signal expOvf_uid64_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
+ signal expOvf_uid64_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
+ signal excXZAndExcYZ_uid65_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excXZAndExcYR_uid66_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excYZAndExcXR_uid67_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excZC3_uid68_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excRZero_uid69_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excXIAndExcYI_uid70_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excXRAndExcYI_uid71_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excYRAndExcXI_uid72_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal ExcROvfAndInReg_uid73_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excRInf_uid74_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excYZAndExcXI_uid75_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excXZAndExcYI_uid76_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal ZeroTimesInf_uid77_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal excRNaN_uid78_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal excRNaN_uid78_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal concExc_uid79_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
+ signal excREnc_uid80_fpMulTest_q : STD_LOGIC_VECTOR (1 downto 0);
+ signal oneFracRPostExc2_uid81_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
+ signal fracRPostExc_uid84_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
+ signal fracRPostExc_uid84_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
+ signal expRPostExc_uid89_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
+ signal expRPostExc_uid89_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
+ signal invExcRNaN_uid90_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal signRPostExc_uid91_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
+ signal signRPostExc_uid91_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal R_uid92_fpMulTest_q : STD_LOGIC_VECTOR (31 downto 0);
+ signal osig_uid95_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (25 downto 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_reset : std_logic;
+ type prodXY_uid94_prod_uid47_fpMulTest_cma_a0type is array(NATURAL range <>) of UNSIGNED(23 downto 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_a0 : prodXY_uid94_prod_uid47_fpMulTest_cma_a0type(0 to 0);
+ attribute preserve : boolean;
+ attribute preserve of prodXY_uid94_prod_uid47_fpMulTest_cma_a0 : signal is true;
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_c0 : prodXY_uid94_prod_uid47_fpMulTest_cma_a0type(0 to 0);
+ attribute preserve of prodXY_uid94_prod_uid47_fpMulTest_cma_c0 : signal is true;
+ type prodXY_uid94_prod_uid47_fpMulTest_cma_ptype is array(NATURAL range <>) of UNSIGNED(47 downto 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_p : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_u : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_w : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_x : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_y : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_s : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_qq : STD_LOGIC_VECTOR (47 downto 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_q : STD_LOGIC_VECTOR (47 downto 0);
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 : std_logic;
+ signal prodXY_uid94_prod_uid47_fpMulTest_cma_ena1 : std_logic;
+ signal redist0_expRPreExc_uid61_fpMulTest_b_2_q : STD_LOGIC_VECTOR (7 downto 0);
+ signal redist1_expRPreExcExt_uid60_fpMulTest_b_1_q : STD_LOGIC_VECTOR (11 downto 0);
+ signal redist2_fracRPreExc_uid59_fpMulTest_b_3_q : STD_LOGIC_VECTOR (22 downto 0);
+ signal redist3_normalizeBit_uid49_fpMulTest_b_1_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist4_signR_uid48_fpMulTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist5_expSum_uid44_fpMulTest_q_2_q : STD_LOGIC_VECTOR (8 downto 0);
+ signal redist6_excI_y_uid33_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist7_fracXIsZero_uid31_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist8_expXIsMax_uid30_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist9_expXIsMax_uid30_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist10_excZ_y_uid29_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist11_excZ_y_uid29_fpMulTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist12_excI_x_uid19_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist13_fracXIsZero_uid17_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist14_expXIsMax_uid16_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist15_expXIsMax_uid16_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist16_excZ_x_uid15_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal redist17_excZ_x_uid15_fpMulTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0);
+
+begin
+
+
+ -- frac_x_uid14_fpMulTest(BITSELECT,13)@0
+ frac_x_uid14_fpMulTest_b <= a(22 downto 0);
+
+ -- cstZeroWF_uid11_fpMulTest(CONSTANT,10)
+ cstZeroWF_uid11_fpMulTest_q <= "00000000000000000000000";
+
+ -- fracXIsZero_uid17_fpMulTest(LOGICAL,16)@0 + 1
+ fracXIsZero_uid17_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_x_uid14_fpMulTest_b ELSE "0";
+ fracXIsZero_uid17_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_qi, xout => fracXIsZero_uid17_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist13_fracXIsZero_uid17_fpMulTest_q_3(DELAY,110)
+ redist13_fracXIsZero_uid17_fpMulTest_q_3 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist13_fracXIsZero_uid17_fpMulTest_q_3_q, clk => clk, aclr => areset );
+
+ -- cstAllOWE_uid10_fpMulTest(CONSTANT,9)
+ cstAllOWE_uid10_fpMulTest_q <= "11111111";
+
+ -- expX_uid6_fpMulTest(BITSELECT,5)@0
+ expX_uid6_fpMulTest_b <= a(30 downto 23);
+
+ -- expXIsMax_uid16_fpMulTest(LOGICAL,15)@0 + 1
+ expXIsMax_uid16_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0";
+ expXIsMax_uid16_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => expXIsMax_uid16_fpMulTest_qi, xout => expXIsMax_uid16_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist14_expXIsMax_uid16_fpMulTest_q_3(DELAY,111)
+ redist14_expXIsMax_uid16_fpMulTest_q_3 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
+ PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist14_expXIsMax_uid16_fpMulTest_q_3_q, clk => clk, aclr => areset );
+
+ -- excI_x_uid19_fpMulTest(LOGICAL,18)@3 + 1
+ excI_x_uid19_fpMulTest_qi <= redist14_expXIsMax_uid16_fpMulTest_q_3_q and redist13_fracXIsZero_uid17_fpMulTest_q_3_q;
+ excI_x_uid19_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excI_x_uid19_fpMulTest_qi, xout => excI_x_uid19_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- cstAllZWE_uid12_fpMulTest(CONSTANT,11)
+ cstAllZWE_uid12_fpMulTest_q <= "00000000";
+
+ -- expY_uid7_fpMulTest(BITSELECT,6)@0
+ expY_uid7_fpMulTest_b <= b(30 downto 23);
+
+ -- excZ_y_uid29_fpMulTest(LOGICAL,28)@0 + 1
+ excZ_y_uid29_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0";
+ excZ_y_uid29_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excZ_y_uid29_fpMulTest_qi, xout => excZ_y_uid29_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist10_excZ_y_uid29_fpMulTest_q_4(DELAY,107)
+ redist10_excZ_y_uid29_fpMulTest_q_4 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist10_excZ_y_uid29_fpMulTest_q_4_q, clk => clk, aclr => areset );
+
+ -- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@4
+ excYZAndExcXI_uid75_fpMulTest_q <= redist10_excZ_y_uid29_fpMulTest_q_4_q and excI_x_uid19_fpMulTest_q;
+
+ -- frac_y_uid28_fpMulTest(BITSELECT,27)@0
+ frac_y_uid28_fpMulTest_b <= b(22 downto 0);
+
+ -- fracXIsZero_uid31_fpMulTest(LOGICAL,30)@0 + 1
+ fracXIsZero_uid31_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_y_uid28_fpMulTest_b ELSE "0";
+ fracXIsZero_uid31_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_qi, xout => fracXIsZero_uid31_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist7_fracXIsZero_uid31_fpMulTest_q_3(DELAY,104)
+ redist7_fracXIsZero_uid31_fpMulTest_q_3 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist7_fracXIsZero_uid31_fpMulTest_q_3_q, clk => clk, aclr => areset );
+
+ -- expXIsMax_uid30_fpMulTest(LOGICAL,29)@0 + 1
+ expXIsMax_uid30_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0";
+ expXIsMax_uid30_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => expXIsMax_uid30_fpMulTest_qi, xout => expXIsMax_uid30_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist8_expXIsMax_uid30_fpMulTest_q_3(DELAY,105)
+ redist8_expXIsMax_uid30_fpMulTest_q_3 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
+ PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist8_expXIsMax_uid30_fpMulTest_q_3_q, clk => clk, aclr => areset );
+
+ -- excI_y_uid33_fpMulTest(LOGICAL,32)@3 + 1
+ excI_y_uid33_fpMulTest_qi <= redist8_expXIsMax_uid30_fpMulTest_q_3_q and redist7_fracXIsZero_uid31_fpMulTest_q_3_q;
+ excI_y_uid33_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excI_y_uid33_fpMulTest_qi, xout => excI_y_uid33_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- excZ_x_uid15_fpMulTest(LOGICAL,14)@0 + 1
+ excZ_x_uid15_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0";
+ excZ_x_uid15_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excZ_x_uid15_fpMulTest_qi, xout => excZ_x_uid15_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist16_excZ_x_uid15_fpMulTest_q_4(DELAY,113)
+ redist16_excZ_x_uid15_fpMulTest_q_4 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist16_excZ_x_uid15_fpMulTest_q_4_q, clk => clk, aclr => areset );
+
+ -- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@4
+ excXZAndExcYI_uid76_fpMulTest_q <= redist16_excZ_x_uid15_fpMulTest_q_4_q and excI_y_uid33_fpMulTest_q;
+
+ -- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@4
+ ZeroTimesInf_uid77_fpMulTest_q <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q;
+
+ -- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@3 + 1
+ fracXIsNotZero_uid32_fpMulTest_qi <= not (redist7_fracXIsZero_uid31_fpMulTest_q_3_q);
+ fracXIsNotZero_uid32_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsNotZero_uid32_fpMulTest_qi, xout => fracXIsNotZero_uid32_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist9_expXIsMax_uid30_fpMulTest_q_4(DELAY,106)
+ redist9_expXIsMax_uid30_fpMulTest_q_4 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => redist8_expXIsMax_uid30_fpMulTest_q_3_q, xout => redist9_expXIsMax_uid30_fpMulTest_q_4_q, clk => clk, aclr => areset );
+
+ -- excN_y_uid34_fpMulTest(LOGICAL,33)@4
+ excN_y_uid34_fpMulTest_q <= redist9_expXIsMax_uid30_fpMulTest_q_4_q and fracXIsNotZero_uid32_fpMulTest_q;
+
+ -- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@3 + 1
+ fracXIsNotZero_uid18_fpMulTest_qi <= not (redist13_fracXIsZero_uid17_fpMulTest_q_3_q);
+ fracXIsNotZero_uid18_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracXIsNotZero_uid18_fpMulTest_qi, xout => fracXIsNotZero_uid18_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist15_expXIsMax_uid16_fpMulTest_q_4(DELAY,112)
+ redist15_expXIsMax_uid16_fpMulTest_q_4 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => redist14_expXIsMax_uid16_fpMulTest_q_3_q, xout => redist15_expXIsMax_uid16_fpMulTest_q_4_q, clk => clk, aclr => areset );
+
+ -- excN_x_uid20_fpMulTest(LOGICAL,19)@4
+ excN_x_uid20_fpMulTest_q <= redist15_expXIsMax_uid16_fpMulTest_q_4_q and fracXIsNotZero_uid18_fpMulTest_q;
+
+ -- excRNaN_uid78_fpMulTest(LOGICAL,77)@4 + 1
+ excRNaN_uid78_fpMulTest_qi <= excN_x_uid20_fpMulTest_q or excN_y_uid34_fpMulTest_q or ZeroTimesInf_uid77_fpMulTest_q;
+ excRNaN_uid78_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excRNaN_uid78_fpMulTest_qi, xout => excRNaN_uid78_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@5
+ invExcRNaN_uid90_fpMulTest_q <= not (excRNaN_uid78_fpMulTest_q);
+
+ -- signY_uid9_fpMulTest(BITSELECT,8)@0
+ signY_uid9_fpMulTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
+
+ -- signX_uid8_fpMulTest(BITSELECT,7)@0
+ signX_uid8_fpMulTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
+
+ -- signR_uid48_fpMulTest(LOGICAL,47)@0 + 1
+ signR_uid48_fpMulTest_qi <= signX_uid8_fpMulTest_b xor signY_uid9_fpMulTest_b;
+ signR_uid48_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => signR_uid48_fpMulTest_qi, xout => signR_uid48_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- redist4_signR_uid48_fpMulTest_q_5(DELAY,101)
+ redist4_signR_uid48_fpMulTest_q_5 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 4, reset_kind => "ASYNC" )
+ PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist4_signR_uid48_fpMulTest_q_5_q, clk => clk, aclr => areset );
+
+ -- VCC(CONSTANT,1)
+ VCC_q <= "1";
+
+ -- signRPostExc_uid91_fpMulTest(LOGICAL,90)@5 + 1
+ signRPostExc_uid91_fpMulTest_qi <= redist4_signR_uid48_fpMulTest_q_5_q and invExcRNaN_uid90_fpMulTest_q;
+ signRPostExc_uid91_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => signRPostExc_uid91_fpMulTest_qi, xout => signRPostExc_uid91_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- GND(CONSTANT,0)
+ GND_q <= "0";
+
+ -- ofracY_uid43_fpMulTest(BITJOIN,42)@0
+ ofracY_uid43_fpMulTest_q <= VCC_q & frac_y_uid28_fpMulTest_b;
+
+ -- ofracX_uid40_fpMulTest(BITJOIN,39)@0
+ ofracX_uid40_fpMulTest_q <= VCC_q & frac_x_uid14_fpMulTest_b;
+
+ -- prodXY_uid94_prod_uid47_fpMulTest_cma(CHAINMULTADD,96)@0 + 2
+ prodXY_uid94_prod_uid47_fpMulTest_cma_reset <= areset;
+ prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 <= '1';
+ prodXY_uid94_prod_uid47_fpMulTest_cma_ena1 <= prodXY_uid94_prod_uid47_fpMulTest_cma_ena0;
+ prodXY_uid94_prod_uid47_fpMulTest_cma_p(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_a0(0) * prodXY_uid94_prod_uid47_fpMulTest_cma_c0(0);
+ prodXY_uid94_prod_uid47_fpMulTest_cma_u(0) <= RESIZE(prodXY_uid94_prod_uid47_fpMulTest_cma_p(0),48);
+ prodXY_uid94_prod_uid47_fpMulTest_cma_w(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_u(0);
+ prodXY_uid94_prod_uid47_fpMulTest_cma_x(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_w(0);
+ prodXY_uid94_prod_uid47_fpMulTest_cma_y(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_x(0);
+ prodXY_uid94_prod_uid47_fpMulTest_cma_chainmultadd_input: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ prodXY_uid94_prod_uid47_fpMulTest_cma_a0 <= (others => (others => '0'));
+ prodXY_uid94_prod_uid47_fpMulTest_cma_c0 <= (others => (others => '0'));
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 = '1') THEN
+ prodXY_uid94_prod_uid47_fpMulTest_cma_a0(0) <= RESIZE(UNSIGNED(ofracX_uid40_fpMulTest_q),24);
+ prodXY_uid94_prod_uid47_fpMulTest_cma_c0(0) <= RESIZE(UNSIGNED(ofracY_uid43_fpMulTest_q),24);
+ END IF;
+ END IF;
+ END PROCESS;
+ prodXY_uid94_prod_uid47_fpMulTest_cma_chainmultadd_output: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ prodXY_uid94_prod_uid47_fpMulTest_cma_s <= (others => (others => '0'));
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (prodXY_uid94_prod_uid47_fpMulTest_cma_ena1 = '1') THEN
+ prodXY_uid94_prod_uid47_fpMulTest_cma_s(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_y(0);
+ END IF;
+ END IF;
+ END PROCESS;
+ prodXY_uid94_prod_uid47_fpMulTest_cma_delay : dspba_delay
+ GENERIC MAP ( width => 48, depth => 0, reset_kind => "ASYNC" )
+ PORT MAP ( xin => STD_LOGIC_VECTOR(prodXY_uid94_prod_uid47_fpMulTest_cma_s(0)(47 downto 0)), xout => prodXY_uid94_prod_uid47_fpMulTest_cma_qq, clk => clk, aclr => areset );
+ prodXY_uid94_prod_uid47_fpMulTest_cma_q <= STD_LOGIC_VECTOR(prodXY_uid94_prod_uid47_fpMulTest_cma_qq(47 downto 0));
+
+ -- osig_uid95_prod_uid47_fpMulTest(BITSELECT,94)@2
+ osig_uid95_prod_uid47_fpMulTest_b <= prodXY_uid94_prod_uid47_fpMulTest_cma_q(47 downto 22);
+
+ -- normalizeBit_uid49_fpMulTest(BITSELECT,48)@2
+ normalizeBit_uid49_fpMulTest_b <= STD_LOGIC_VECTOR(osig_uid95_prod_uid47_fpMulTest_b(25 downto 25));
+
+ -- redist3_normalizeBit_uid49_fpMulTest_b_1(DELAY,100)
+ redist3_normalizeBit_uid49_fpMulTest_b_1 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => normalizeBit_uid49_fpMulTest_b, xout => redist3_normalizeBit_uid49_fpMulTest_b_1_q, clk => clk, aclr => areset );
+
+ -- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@3
+ roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & redist3_normalizeBit_uid49_fpMulTest_b_1_q & cstZeroWF_uid11_fpMulTest_q & VCC_q;
+
+ -- biasInc_uid45_fpMulTest(CONSTANT,44)
+ biasInc_uid45_fpMulTest_q <= "0001111111";
+
+ -- expSum_uid44_fpMulTest(ADD,43)@0 + 1
+ expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpMulTest_b);
+ expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & expY_uid7_fpMulTest_b);
+ expSum_uid44_fpMulTest_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ expSum_uid44_fpMulTest_o <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ expSum_uid44_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid44_fpMulTest_a) + UNSIGNED(expSum_uid44_fpMulTest_b));
+ END IF;
+ END PROCESS;
+ expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(8 downto 0);
+
+ -- redist5_expSum_uid44_fpMulTest_q_2(DELAY,102)
+ redist5_expSum_uid44_fpMulTest_q_2 : dspba_delay
+ GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => expSum_uid44_fpMulTest_q, xout => redist5_expSum_uid44_fpMulTest_q_2_q, clk => clk, aclr => areset );
+
+ -- expSumMBias_uid46_fpMulTest(SUB,45)@2 + 1
+ expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000" & redist5_expSum_uid44_fpMulTest_q_2_q));
+ expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid45_fpMulTest_q(9)) & biasInc_uid45_fpMulTest_q));
+ expSumMBias_uid46_fpMulTest_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ expSumMBias_uid46_fpMulTest_o <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b));
+ END IF;
+ END PROCESS;
+ expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(10 downto 0);
+
+ -- fracRPostNormHigh_uid51_fpMulTest(BITSELECT,50)@2
+ fracRPostNormHigh_uid51_fpMulTest_in <= osig_uid95_prod_uid47_fpMulTest_b(24 downto 0);
+ fracRPostNormHigh_uid51_fpMulTest_b <= fracRPostNormHigh_uid51_fpMulTest_in(24 downto 1);
+
+ -- fracRPostNormLow_uid52_fpMulTest(BITSELECT,51)@2
+ fracRPostNormLow_uid52_fpMulTest_in <= osig_uid95_prod_uid47_fpMulTest_b(23 downto 0);
+ fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(23 downto 0);
+
+ -- fracRPostNorm_uid53_fpMulTest(MUX,52)@2 + 1
+ fracRPostNorm_uid53_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b;
+ fracRPostNorm_uid53_fpMulTest_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ CASE (fracRPostNorm_uid53_fpMulTest_s) IS
+ WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b;
+ WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b;
+ WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
+ END CASE;
+ END IF;
+ END PROCESS;
+
+ -- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@3
+ expFracPreRound_uid55_fpMulTest_q <= expSumMBias_uid46_fpMulTest_q & fracRPostNorm_uid53_fpMulTest_q;
+
+ -- expFracRPostRounding_uid58_fpMulTest(ADD,57)@3
+ expFracRPostRounding_uid58_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((36 downto 35 => expFracPreRound_uid55_fpMulTest_q(34)) & expFracPreRound_uid55_fpMulTest_q));
+ expFracRPostRounding_uid58_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("00000000000" & roundBitAndNormalizationOp_uid57_fpMulTest_q));
+ expFracRPostRounding_uid58_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid58_fpMulTest_a) + SIGNED(expFracRPostRounding_uid58_fpMulTest_b));
+ expFracRPostRounding_uid58_fpMulTest_q <= expFracRPostRounding_uid58_fpMulTest_o(35 downto 0);
+
+ -- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@3
+ expRPreExcExt_uid60_fpMulTest_b <= STD_LOGIC_VECTOR(expFracRPostRounding_uid58_fpMulTest_q(35 downto 24));
+
+ -- redist1_expRPreExcExt_uid60_fpMulTest_b_1(DELAY,98)
+ redist1_expRPreExcExt_uid60_fpMulTest_b_1 : dspba_delay
+ GENERIC MAP ( width => 12, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => expRPreExcExt_uid60_fpMulTest_b, xout => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q, clk => clk, aclr => areset );
+
+ -- expRPreExc_uid61_fpMulTest(BITSELECT,60)@4
+ expRPreExc_uid61_fpMulTest_in <= redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(7 downto 0);
+ expRPreExc_uid61_fpMulTest_b <= expRPreExc_uid61_fpMulTest_in(7 downto 0);
+
+ -- redist0_expRPreExc_uid61_fpMulTest_b_2(DELAY,97)
+ redist0_expRPreExc_uid61_fpMulTest_b_2 : dspba_delay
+ GENERIC MAP ( width => 8, depth => 2, reset_kind => "ASYNC" )
+ PORT MAP ( xin => expRPreExc_uid61_fpMulTest_b, xout => redist0_expRPreExc_uid61_fpMulTest_b_2_q, clk => clk, aclr => areset );
+
+ -- expOvf_uid64_fpMulTest(COMPARE,63)@4 + 1
+ expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(11)) & redist1_expRPreExcExt_uid60_fpMulTest_b_1_q));
+ expOvf_uid64_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000000" & cstAllOWE_uid10_fpMulTest_q));
+ expOvf_uid64_fpMulTest_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ expOvf_uid64_fpMulTest_o <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ expOvf_uid64_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid64_fpMulTest_a) - SIGNED(expOvf_uid64_fpMulTest_b));
+ END IF;
+ END PROCESS;
+ expOvf_uid64_fpMulTest_n(0) <= not (expOvf_uid64_fpMulTest_o(13));
+
+ -- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@4
+ invExpXIsMax_uid35_fpMulTest_q <= not (redist9_expXIsMax_uid30_fpMulTest_q_4_q);
+
+ -- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@4
+ InvExpXIsZero_uid36_fpMulTest_q <= not (redist10_excZ_y_uid29_fpMulTest_q_4_q);
+
+ -- excR_y_uid37_fpMulTest(LOGICAL,36)@4 + 1
+ excR_y_uid37_fpMulTest_qi <= InvExpXIsZero_uid36_fpMulTest_q and invExpXIsMax_uid35_fpMulTest_q;
+ excR_y_uid37_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excR_y_uid37_fpMulTest_qi, xout => excR_y_uid37_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@4
+ invExpXIsMax_uid21_fpMulTest_q <= not (redist15_expXIsMax_uid16_fpMulTest_q_4_q);
+
+ -- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@4
+ InvExpXIsZero_uid22_fpMulTest_q <= not (redist16_excZ_x_uid15_fpMulTest_q_4_q);
+
+ -- excR_x_uid23_fpMulTest(LOGICAL,22)@4 + 1
+ excR_x_uid23_fpMulTest_qi <= InvExpXIsZero_uid22_fpMulTest_q and invExpXIsMax_uid21_fpMulTest_q;
+ excR_x_uid23_fpMulTest_delay : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excR_x_uid23_fpMulTest_qi, xout => excR_x_uid23_fpMulTest_q, clk => clk, aclr => areset );
+
+ -- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@5
+ ExcROvfAndInReg_uid73_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n;
+
+ -- redist12_excI_x_uid19_fpMulTest_q_2(DELAY,109)
+ redist12_excI_x_uid19_fpMulTest_q_2 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excI_x_uid19_fpMulTest_q, xout => redist12_excI_x_uid19_fpMulTest_q_2_q, clk => clk, aclr => areset );
+
+ -- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@5
+ excYRAndExcXI_uid72_fpMulTest_q <= excR_y_uid37_fpMulTest_q and redist12_excI_x_uid19_fpMulTest_q_2_q;
+
+ -- redist6_excI_y_uid33_fpMulTest_q_2(DELAY,103)
+ redist6_excI_y_uid33_fpMulTest_q_2 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => excI_y_uid33_fpMulTest_q, xout => redist6_excI_y_uid33_fpMulTest_q_2_q, clk => clk, aclr => areset );
+
+ -- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@5
+ excXRAndExcYI_uid71_fpMulTest_q <= excR_x_uid23_fpMulTest_q and redist6_excI_y_uid33_fpMulTest_q_2_q;
+
+ -- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@5
+ excXIAndExcYI_uid70_fpMulTest_q <= redist12_excI_x_uid19_fpMulTest_q_2_q and redist6_excI_y_uid33_fpMulTest_q_2_q;
+
+ -- excRInf_uid74_fpMulTest(LOGICAL,73)@5
+ excRInf_uid74_fpMulTest_q <= excXIAndExcYI_uid70_fpMulTest_q or excXRAndExcYI_uid71_fpMulTest_q or excYRAndExcXI_uid72_fpMulTest_q or ExcROvfAndInReg_uid73_fpMulTest_q;
+
+ -- expUdf_uid62_fpMulTest(COMPARE,61)@4 + 1
+ expUdf_uid62_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0000000000000" & GND_q));
+ expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(11)) & redist1_expRPreExcExt_uid60_fpMulTest_b_1_q));
+ expUdf_uid62_fpMulTest_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ expUdf_uid62_fpMulTest_o <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ expUdf_uid62_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid62_fpMulTest_a) - SIGNED(expUdf_uid62_fpMulTest_b));
+ END IF;
+ END PROCESS;
+ expUdf_uid62_fpMulTest_n(0) <= not (expUdf_uid62_fpMulTest_o(13));
+
+ -- excZC3_uid68_fpMulTest(LOGICAL,67)@5
+ excZC3_uid68_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n;
+
+ -- redist11_excZ_y_uid29_fpMulTest_q_5(DELAY,108)
+ redist11_excZ_y_uid29_fpMulTest_q_5 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => redist10_excZ_y_uid29_fpMulTest_q_4_q, xout => redist11_excZ_y_uid29_fpMulTest_q_5_q, clk => clk, aclr => areset );
+
+ -- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@5
+ excYZAndExcXR_uid67_fpMulTest_q <= redist11_excZ_y_uid29_fpMulTest_q_5_q and excR_x_uid23_fpMulTest_q;
+
+ -- redist17_excZ_x_uid15_fpMulTest_q_5(DELAY,114)
+ redist17_excZ_x_uid15_fpMulTest_q_5 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
+ PORT MAP ( xin => redist16_excZ_x_uid15_fpMulTest_q_4_q, xout => redist17_excZ_x_uid15_fpMulTest_q_5_q, clk => clk, aclr => areset );
+
+ -- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@5
+ excXZAndExcYR_uid66_fpMulTest_q <= redist17_excZ_x_uid15_fpMulTest_q_5_q and excR_y_uid37_fpMulTest_q;
+
+ -- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@5
+ excXZAndExcYZ_uid65_fpMulTest_q <= redist17_excZ_x_uid15_fpMulTest_q_5_q and redist11_excZ_y_uid29_fpMulTest_q_5_q;
+
+ -- excRZero_uid69_fpMulTest(LOGICAL,68)@5
+ excRZero_uid69_fpMulTest_q <= excXZAndExcYZ_uid65_fpMulTest_q or excXZAndExcYR_uid66_fpMulTest_q or excYZAndExcXR_uid67_fpMulTest_q or excZC3_uid68_fpMulTest_q;
+
+ -- concExc_uid79_fpMulTest(BITJOIN,78)@5
+ concExc_uid79_fpMulTest_q <= excRNaN_uid78_fpMulTest_q & excRInf_uid74_fpMulTest_q & excRZero_uid69_fpMulTest_q;
+
+ -- excREnc_uid80_fpMulTest(LOOKUP,79)@5 + 1
+ excREnc_uid80_fpMulTest_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ excREnc_uid80_fpMulTest_q <= "01";
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ CASE (concExc_uid79_fpMulTest_q) IS
+ WHEN "000" => excREnc_uid80_fpMulTest_q <= "01";
+ WHEN "001" => excREnc_uid80_fpMulTest_q <= "00";
+ WHEN "010" => excREnc_uid80_fpMulTest_q <= "10";
+ WHEN "011" => excREnc_uid80_fpMulTest_q <= "00";
+ WHEN "100" => excREnc_uid80_fpMulTest_q <= "11";
+ WHEN "101" => excREnc_uid80_fpMulTest_q <= "00";
+ WHEN "110" => excREnc_uid80_fpMulTest_q <= "00";
+ WHEN "111" => excREnc_uid80_fpMulTest_q <= "00";
+ WHEN OTHERS => -- unreachable
+ excREnc_uid80_fpMulTest_q <= (others => '-');
+ END CASE;
+ END IF;
+ END PROCESS;
+
+ -- expRPostExc_uid89_fpMulTest(MUX,88)@6
+ expRPostExc_uid89_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
+ expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, cstAllZWE_uid12_fpMulTest_q, redist0_expRPreExc_uid61_fpMulTest_b_2_q, cstAllOWE_uid10_fpMulTest_q)
+ BEGIN
+ CASE (expRPostExc_uid89_fpMulTest_s) IS
+ WHEN "00" => expRPostExc_uid89_fpMulTest_q <= cstAllZWE_uid12_fpMulTest_q;
+ WHEN "01" => expRPostExc_uid89_fpMulTest_q <= redist0_expRPreExc_uid61_fpMulTest_b_2_q;
+ WHEN "10" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
+ WHEN "11" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
+ WHEN OTHERS => expRPostExc_uid89_fpMulTest_q <= (others => '0');
+ END CASE;
+ END PROCESS;
+
+ -- oneFracRPostExc2_uid81_fpMulTest(CONSTANT,80)
+ oneFracRPostExc2_uid81_fpMulTest_q <= "00000000000000000000001";
+
+ -- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@3
+ fracRPreExc_uid59_fpMulTest_in <= expFracRPostRounding_uid58_fpMulTest_q(23 downto 0);
+ fracRPreExc_uid59_fpMulTest_b <= fracRPreExc_uid59_fpMulTest_in(23 downto 1);
+
+ -- redist2_fracRPreExc_uid59_fpMulTest_b_3(DELAY,99)
+ redist2_fracRPreExc_uid59_fpMulTest_b_3 : dspba_delay
+ GENERIC MAP ( width => 23, depth => 3, reset_kind => "ASYNC" )
+ PORT MAP ( xin => fracRPreExc_uid59_fpMulTest_b, xout => redist2_fracRPreExc_uid59_fpMulTest_b_3_q, clk => clk, aclr => areset );
+
+ -- fracRPostExc_uid84_fpMulTest(MUX,83)@6
+ fracRPostExc_uid84_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
+ fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, cstZeroWF_uid11_fpMulTest_q, redist2_fracRPreExc_uid59_fpMulTest_b_3_q, oneFracRPostExc2_uid81_fpMulTest_q)
+ BEGIN
+ CASE (fracRPostExc_uid84_fpMulTest_s) IS
+ WHEN "00" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
+ WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= redist2_fracRPreExc_uid59_fpMulTest_b_3_q;
+ WHEN "10" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
+ WHEN "11" => fracRPostExc_uid84_fpMulTest_q <= oneFracRPostExc2_uid81_fpMulTest_q;
+ WHEN OTHERS => fracRPostExc_uid84_fpMulTest_q <= (others => '0');
+ END CASE;
+ END PROCESS;
+
+ -- R_uid92_fpMulTest(BITJOIN,91)@6
+ R_uid92_fpMulTest_q <= signRPostExc_uid91_fpMulTest_q & expRPostExc_uid89_fpMulTest_q & fracRPostExc_uid84_fpMulTest_q;
+
+ -- xOut(GPOUT,4)@6
+ q <= R_uid92_fpMulTest_q;
+
+END normal;
diff --git a/ip/ip_fp_mul_sim.f b/ip/ip_fp_mul_sim.f
new file mode 100644
index 0000000..a5445ba
--- /dev/null
+++ b/ip/ip_fp_mul_sim.f
@@ -0,0 +1 @@
+ip_fp_mul_sim/ip_fp_mul.vo
diff --git a/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl b/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl
new file mode 100644
index 0000000..14027e6
--- /dev/null
+++ b/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl
@@ -0,0 +1,278 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2023.10.21.04:56:13
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_fp_mul"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] {
+ set QUARTUS_INSTALL_DIR "/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
+ set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
+ set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
+ set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] {
+ set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+ set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+ scripterconf -tcl
+ createdesign "$TOP_LEVEL_NAME" "."
+ opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+ echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries
+ensure_lib ./libraries/work
+vmap work ./libraries/work
+ensure_lib ./libraries/altera_ver
+vmap altera_ver ./libraries/altera_ver
+ensure_lib ./libraries/lpm_ver
+vmap lpm_ver ./libraries/lpm_ver
+ensure_lib ./libraries/sgate_ver
+vmap sgate_ver ./libraries/sgate_ver
+ensure_lib ./libraries/altera_mf_ver
+vmap altera_mf_ver ./libraries/altera_mf_ver
+ensure_lib ./libraries/altera_lnsim_ver
+vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
+ensure_lib ./libraries/cyclonev_ver
+vmap cyclonev_ver ./libraries/cyclonev_ver
+ensure_lib ./libraries/cyclonev_hssi_ver
+vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
+ensure_lib ./libraries/cyclonev_pcie_hip_ver
+vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_mul.vo"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "file_copy -- Copy ROM/RAM files to simulation directory"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo " For most designs, this should be overridden"
+ echo " to enable the elab/elab_debug aliases."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
+ echo
+ echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
+ echo
+ echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
+ echo
+ echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
diff --git a/ip/ip_fp_mul_sim/cadence/cds.lib b/ip/ip_fp_mul_sim/cadence/cds.lib
new file mode 100644
index 0000000..b2eae0a
--- /dev/null
+++ b/ip/ip_fp_mul_sim/cadence/cds.lib
@@ -0,0 +1,19 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./libraries/work/
+DEFINE altera_ver ./libraries/altera_ver/
+DEFINE lpm_ver ./libraries/lpm_ver/
+DEFINE sgate_ver ./libraries/sgate_ver/
+DEFINE altera_mf_ver ./libraries/altera_mf_ver/
+DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/
+DEFINE cyclonev_ver ./libraries/cyclonev_ver/
+DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
+DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
diff --git a/ip/ip_fp_mul_sim/cadence/hdl.var b/ip/ip_fp_mul_sim/cadence/hdl.var
new file mode 100644
index 0000000..c1b7814
--- /dev/null
+++ b/ip/ip_fp_mul_sim/cadence/hdl.var
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
diff --git a/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh b/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh
new file mode 100755
index 0000000..11435a9
--- /dev/null
+++ b/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh
@@ -0,0 +1,195 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2023.10.21.04:56:13
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2023.10.21.04:56:13
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_fp_mul"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_mul.vo"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ export GENERIC_PARAM_COMPAT_CHECK=1
+ ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi
diff --git a/ip/ip_fp_mul_sim/ip_fp_mul.vo b/ip/ip_fp_mul_sim/ip_fp_mul.vo
new file mode 100644
index 0000000..bc00f70
--- /dev/null
+++ b/ip/ip_fp_mul_sim/ip_fp_mul.vo
@@ -0,0 +1,1592 @@
+//IP Functional Simulation Model
+//VERSION_BEGIN 20.1 cbx_mgl 2020:11:11:17:50:46:SJ cbx_simgen 2020:11:11:17:03:37:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2020 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions
+// and other software and tools, and any partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors. Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// You may only use these simulation model output files for simulation
+// purposes and expressly not for synthesis or any other purposes (in which
+// event Intel disclaims all warranties of any kind).
+
+
+//synopsys translate_off
+
+//synthesis_resources = lut 268 mux21 24 oper_add 5 oper_mult 1 oper_mux 33
+`timescale 1 ps / 1 ps
+module ip_fp_mul
+ (
+ a,
+ areset,
+ b,
+ clk,
+ q) /* synthesis synthesis_clearbox=1 */;
+ input [31:0] a;
+ input areset;
+ input [31:0] b;
+ input clk;
+ output [31:0] q;
+
+ reg n00i;
+ reg n00l;
+ reg n00O;
+ reg n01i;
+ reg n01l;
+ reg n01O;
+ reg n0ii;
+ reg n0il;
+ reg n0iO;
+ reg n0li;
+ reg n0ll;
+ reg n0lO;
+ reg n0Oi;
+ reg n0Ol;
+ reg n0OO;
+ reg n100i;
+ reg n100l;
+ reg n100O;
+ reg n101i;
+ reg n101l;
+ reg n101O;
+ reg n10i;
+ reg n10ii;
+ reg n10il;
+ reg n10iO;
+ reg n10l;
+ reg n10li;
+ reg n10ll;
+ reg n10lO;
+ reg n10O;
+ reg n10Oi;
+ reg n10Ol;
+ reg n10OO;
+ reg n110i;
+ reg n110l;
+ reg n110O;
+ reg n111i;
+ reg n111l;
+ reg n111O;
+ reg n11i;
+ reg n11ii;
+ reg n11il;
+ reg n11iO;
+ reg n11l;
+ reg n11li;
+ reg n11ll;
+ reg n11lO;
+ reg n11O;
+ reg n11Oi;
+ reg n11Ol;
+ reg n11OO;
+ reg n1i;
+ reg n1i0i;
+ reg n1i0l;
+ reg n1i0O;
+ reg n1i1i;
+ reg n1i1l;
+ reg n1i1O;
+ reg n1ii;
+ reg n1iii;
+ reg n1iil;
+ reg n1iiO;
+ reg n1il;
+ reg n1ili;
+ reg n1ill;
+ reg n1ilO;
+ reg n1iO;
+ reg n1iOi;
+ reg n1iOl;
+ reg n1iOO;
+ reg n1l0i;
+ reg n1l0l;
+ reg n1l0O;
+ reg n1l1i;
+ reg n1l1l;
+ reg n1l1O;
+ reg n1li;
+ reg n1lii;
+ reg n1lil;
+ reg n1liO;
+ reg n1ll;
+ reg n1lli;
+ reg n1lll;
+ reg n1lO;
+ reg n1O;
+ reg n1Oi;
+ reg n1Ol;
+ reg n1OO;
+ reg ni0i;
+ reg ni0l;
+ reg ni0O;
+ reg ni1i;
+ reg ni1l;
+ reg ni1O;
+ reg niii;
+ reg niil;
+ reg niilO;
+ reg niiO;
+ reg niiOi;
+ reg nili;
+ reg nill;
+ reg nilli;
+ reg nilO;
+ reg niOi;
+ reg niOii;
+ reg niOl;
+ reg niOli;
+ reg niOll;
+ reg niOlO;
+ reg niOO;
+ reg niOOi;
+ reg niOOl;
+ reg niOOO;
+ reg nl01i;
+ reg nl01l;
+ reg nl01O;
+ reg nl0i;
+ reg nl0l;
+ reg nl0O;
+ reg nl10i;
+ reg nl10l;
+ reg nl10O;
+ reg nl11i;
+ reg nl11l;
+ reg nl11O;
+ reg nl1i;
+ reg nl1ii;
+ reg nl1il;
+ reg nl1iO;
+ reg nl1l;
+ reg nl1li;
+ reg nl1ll;
+ reg nl1lO;
+ reg nl1O;
+ reg nl1Oi;
+ reg nl1Ol;
+ reg nl1OO;
+ reg nlii;
+ reg nlil;
+ reg nliO;
+ reg nliOi;
+ reg nliOl;
+ reg nliOO;
+ reg nll0i;
+ reg nll0l;
+ reg nll0O;
+ reg nll1i;
+ reg nll1l;
+ reg nll1O;
+ reg nlli;
+ reg nllii;
+ reg nllil;
+ reg nlll;
+ reg nllli;
+ reg nllll;
+ reg nlllO;
+ reg nllO;
+ reg nllO0i;
+ reg nllO0l;
+ reg nllO0O;
+ reg nllO1i;
+ reg nllO1l;
+ reg nllO1O;
+ reg nllOi;
+ reg nllOii;
+ reg nllOil;
+ reg nllOiO;
+ reg nllOl;
+ reg nllOli;
+ reg nllOll;
+ reg nllOlO;
+ reg nllOO;
+ reg nllOOi;
+ reg nllOOl;
+ reg nllOOO;
+ reg nlO00i;
+ reg nlO00l;
+ reg nlO00O;
+ reg nlO01i;
+ reg nlO01l;
+ reg nlO01O;
+ reg nlO0i;
+ reg nlO0ii;
+ reg nlO0il;
+ reg nlO0iO;
+ reg nlO0l;
+ reg nlO0li;
+ reg nlO0ll;
+ reg nlO0lO;
+ reg nlO0O;
+ reg nlO0Oi;
+ reg nlO0Ol;
+ reg nlO0OO;
+ reg nlO10i;
+ reg nlO10l;
+ reg nlO10O;
+ reg nlO11i;
+ reg nlO11l;
+ reg nlO11O;
+ reg nlO1i;
+ reg nlO1ii;
+ reg nlO1il;
+ reg nlO1iO;
+ reg nlO1l;
+ reg nlO1li;
+ reg nlO1ll;
+ reg nlO1lO;
+ reg nlO1Oi;
+ reg nlO1Ol;
+ reg nlO1OO;
+ reg nlOi;
+ reg nlOi0i;
+ reg nlOi0l;
+ reg nlOi0O;
+ reg nlOi1i;
+ reg nlOi1l;
+ reg nlOi1O;
+ reg nlOii;
+ reg nlOiii;
+ reg nlOiil;
+ reg nlOiiO;
+ reg nlOil;
+ reg nlOili;
+ reg nlOill;
+ reg nlOilO;
+ reg nlOiO;
+ reg nlOiOi;
+ reg nlOiOl;
+ reg nlOiOO;
+ reg nlOl;
+ reg nlOl0i;
+ reg nlOl0l;
+ reg nlOl0O;
+ reg nlOl1i;
+ reg nlOl1l;
+ reg nlOl1O;
+ reg nlOli;
+ reg nlOlii;
+ reg nlOlil;
+ reg nlOliO;
+ reg nlOll;
+ reg nlOlli;
+ reg nlOlll;
+ reg nlOllO;
+ reg nlOlO;
+ reg nlOlOi;
+ reg nlOlOl;
+ reg nlOlOO;
+ reg nlOO;
+ reg nlOO0i;
+ reg nlOO0l;
+ reg nlOO0O;
+ reg nlOO1i;
+ reg nlOO1l;
+ reg nlOO1O;
+ reg nlOOi;
+ reg nlOOii;
+ reg nlOOil;
+ reg nlOOiO;
+ reg nlOOl;
+ reg nlOOli;
+ reg nlOOll;
+ reg nlOOlO;
+ reg nlOOO;
+ reg nlOOOi;
+ reg nlOOOl;
+ reg nlOOOO;
+ reg niliO;
+ wire wire_nl00i_dataout;
+ wire wire_nl00l_dataout;
+ wire wire_nl00O_dataout;
+ wire wire_nl0ii_dataout;
+ wire wire_nl0il_dataout;
+ wire wire_nl0iO_dataout;
+ wire wire_nl0li_dataout;
+ wire wire_nl0ll_dataout;
+ wire wire_nl0lO_dataout;
+ wire wire_nl0Oi_dataout;
+ wire wire_nl0Ol_dataout;
+ wire wire_nl0OO_dataout;
+ wire wire_nli0i_dataout;
+ wire wire_nli0l_dataout;
+ wire wire_nli0O_dataout;
+ wire wire_nli1i_dataout;
+ wire wire_nli1l_dataout;
+ wire wire_nli1O_dataout;
+ wire wire_nliii_dataout;
+ wire wire_nliil_dataout;
+ wire wire_nliiO_dataout;
+ wire wire_nlili_dataout;
+ wire wire_nlill_dataout;
+ wire wire_nlilO_dataout;
+ wire [14:0] wire_nilll_o;
+ wire [14:0] wire_niOil_o;
+ wire [36:0] wire_niOiO_o;
+ wire [12:0] wire_nlliO_o;
+ wire [8:0] wire_nlO1O_o;
+ wire [47:0] wire_n0i_o;
+ wire wire_ni00i_o;
+ wire wire_ni00l_o;
+ wire wire_ni00O_o;
+ wire wire_ni01i_o;
+ wire wire_ni01l_o;
+ wire wire_ni01O_o;
+ wire wire_ni0ii_o;
+ wire wire_ni0il_o;
+ wire wire_ni0iO_o;
+ wire wire_ni0li_o;
+ wire wire_ni0ll_o;
+ wire wire_ni0lO_o;
+ wire wire_ni0Oi_o;
+ wire wire_ni0Ol_o;
+ wire wire_ni0OO_o;
+ wire wire_ni1ll_o;
+ wire wire_ni1lO_o;
+ wire wire_ni1Oi_o;
+ wire wire_ni1Ol_o;
+ wire wire_ni1OO_o;
+ wire wire_nii0i_o;
+ wire wire_nii0l_o;
+ wire wire_nii0O_o;
+ wire wire_nii1i_o;
+ wire wire_nii1l_o;
+ wire wire_nii1O_o;
+ wire wire_niiii_o;
+ wire wire_niiil_o;
+ wire wire_niiiO_o;
+ wire wire_niili_o;
+ wire wire_niill_o;
+ wire wire_niiOl_o;
+ wire wire_niiOO_o;
+ wire nlll0i;
+ wire nlll0l;
+ wire nlll0O;
+ wire nlllii;
+ wire nlllil;
+ wire nllliO;
+ wire nlllli;
+ wire nlllll;
+ wire nllllO;
+ wire nlllOl;
+
+ initial
+ begin
+ n00i = 0;
+ n00l = 0;
+ n00O = 0;
+ n01i = 0;
+ n01l = 0;
+ n01O = 0;
+ n0ii = 0;
+ n0il = 0;
+ n0iO = 0;
+ n0li = 0;
+ n0ll = 0;
+ n0lO = 0;
+ n0Oi = 0;
+ n0Ol = 0;
+ n0OO = 0;
+ n100i = 0;
+ n100l = 0;
+ n100O = 0;
+ n101i = 0;
+ n101l = 0;
+ n101O = 0;
+ n10i = 0;
+ n10ii = 0;
+ n10il = 0;
+ n10iO = 0;
+ n10l = 0;
+ n10li = 0;
+ n10ll = 0;
+ n10lO = 0;
+ n10O = 0;
+ n10Oi = 0;
+ n10Ol = 0;
+ n10OO = 0;
+ n110i = 0;
+ n110l = 0;
+ n110O = 0;
+ n111i = 0;
+ n111l = 0;
+ n111O = 0;
+ n11i = 0;
+ n11ii = 0;
+ n11il = 0;
+ n11iO = 0;
+ n11l = 0;
+ n11li = 0;
+ n11ll = 0;
+ n11lO = 0;
+ n11O = 0;
+ n11Oi = 0;
+ n11Ol = 0;
+ n11OO = 0;
+ n1i = 0;
+ n1i0i = 0;
+ n1i0l = 0;
+ n1i0O = 0;
+ n1i1i = 0;
+ n1i1l = 0;
+ n1i1O = 0;
+ n1ii = 0;
+ n1iii = 0;
+ n1iil = 0;
+ n1iiO = 0;
+ n1il = 0;
+ n1ili = 0;
+ n1ill = 0;
+ n1ilO = 0;
+ n1iO = 0;
+ n1iOi = 0;
+ n1iOl = 0;
+ n1iOO = 0;
+ n1l0i = 0;
+ n1l0l = 0;
+ n1l0O = 0;
+ n1l1i = 0;
+ n1l1l = 0;
+ n1l1O = 0;
+ n1li = 0;
+ n1lii = 0;
+ n1lil = 0;
+ n1liO = 0;
+ n1ll = 0;
+ n1lli = 0;
+ n1lll = 0;
+ n1lO = 0;
+ n1O = 0;
+ n1Oi = 0;
+ n1Ol = 0;
+ n1OO = 0;
+ ni0i = 0;
+ ni0l = 0;
+ ni0O = 0;
+ ni1i = 0;
+ ni1l = 0;
+ ni1O = 0;
+ niii = 0;
+ niil = 0;
+ niilO = 0;
+ niiO = 0;
+ niiOi = 0;
+ nili = 0;
+ nill = 0;
+ nilli = 0;
+ nilO = 0;
+ niOi = 0;
+ niOii = 0;
+ niOl = 0;
+ niOli = 0;
+ niOll = 0;
+ niOlO = 0;
+ niOO = 0;
+ niOOi = 0;
+ niOOl = 0;
+ niOOO = 0;
+ nl01i = 0;
+ nl01l = 0;
+ nl01O = 0;
+ nl0i = 0;
+ nl0l = 0;
+ nl0O = 0;
+ nl10i = 0;
+ nl10l = 0;
+ nl10O = 0;
+ nl11i = 0;
+ nl11l = 0;
+ nl11O = 0;
+ nl1i = 0;
+ nl1ii = 0;
+ nl1il = 0;
+ nl1iO = 0;
+ nl1l = 0;
+ nl1li = 0;
+ nl1ll = 0;
+ nl1lO = 0;
+ nl1O = 0;
+ nl1Oi = 0;
+ nl1Ol = 0;
+ nl1OO = 0;
+ nlii = 0;
+ nlil = 0;
+ nliO = 0;
+ nliOi = 0;
+ nliOl = 0;
+ nliOO = 0;
+ nll0i = 0;
+ nll0l = 0;
+ nll0O = 0;
+ nll1i = 0;
+ nll1l = 0;
+ nll1O = 0;
+ nlli = 0;
+ nllii = 0;
+ nllil = 0;
+ nlll = 0;
+ nllli = 0;
+ nllll = 0;
+ nlllO = 0;
+ nllO = 0;
+ nllO0i = 0;
+ nllO0l = 0;
+ nllO0O = 0;
+ nllO1i = 0;
+ nllO1l = 0;
+ nllO1O = 0;
+ nllOi = 0;
+ nllOii = 0;
+ nllOil = 0;
+ nllOiO = 0;
+ nllOl = 0;
+ nllOli = 0;
+ nllOll = 0;
+ nllOlO = 0;
+ nllOO = 0;
+ nllOOi = 0;
+ nllOOl = 0;
+ nllOOO = 0;
+ nlO00i = 0;
+ nlO00l = 0;
+ nlO00O = 0;
+ nlO01i = 0;
+ nlO01l = 0;
+ nlO01O = 0;
+ nlO0i = 0;
+ nlO0ii = 0;
+ nlO0il = 0;
+ nlO0iO = 0;
+ nlO0l = 0;
+ nlO0li = 0;
+ nlO0ll = 0;
+ nlO0lO = 0;
+ nlO0O = 0;
+ nlO0Oi = 0;
+ nlO0Ol = 0;
+ nlO0OO = 0;
+ nlO10i = 0;
+ nlO10l = 0;
+ nlO10O = 0;
+ nlO11i = 0;
+ nlO11l = 0;
+ nlO11O = 0;
+ nlO1i = 0;
+ nlO1ii = 0;
+ nlO1il = 0;
+ nlO1iO = 0;
+ nlO1l = 0;
+ nlO1li = 0;
+ nlO1ll = 0;
+ nlO1lO = 0;
+ nlO1Oi = 0;
+ nlO1Ol = 0;
+ nlO1OO = 0;
+ nlOi = 0;
+ nlOi0i = 0;
+ nlOi0l = 0;
+ nlOi0O = 0;
+ nlOi1i = 0;
+ nlOi1l = 0;
+ nlOi1O = 0;
+ nlOii = 0;
+ nlOiii = 0;
+ nlOiil = 0;
+ nlOiiO = 0;
+ nlOil = 0;
+ nlOili = 0;
+ nlOill = 0;
+ nlOilO = 0;
+ nlOiO = 0;
+ nlOiOi = 0;
+ nlOiOl = 0;
+ nlOiOO = 0;
+ nlOl = 0;
+ nlOl0i = 0;
+ nlOl0l = 0;
+ nlOl0O = 0;
+ nlOl1i = 0;
+ nlOl1l = 0;
+ nlOl1O = 0;
+ nlOli = 0;
+ nlOlii = 0;
+ nlOlil = 0;
+ nlOliO = 0;
+ nlOll = 0;
+ nlOlli = 0;
+ nlOlll = 0;
+ nlOllO = 0;
+ nlOlO = 0;
+ nlOlOi = 0;
+ nlOlOl = 0;
+ nlOlOO = 0;
+ nlOO = 0;
+ nlOO0i = 0;
+ nlOO0l = 0;
+ nlOO0O = 0;
+ nlOO1i = 0;
+ nlOO1l = 0;
+ nlOO1O = 0;
+ nlOOi = 0;
+ nlOOii = 0;
+ nlOOil = 0;
+ nlOOiO = 0;
+ nlOOl = 0;
+ nlOOli = 0;
+ nlOOll = 0;
+ nlOOlO = 0;
+ nlOOO = 0;
+ nlOOOi = 0;
+ nlOOOl = 0;
+ nlOOOO = 0;
+ end
+ always @ ( posedge clk or posedge areset)
+ begin
+ if (areset == 1'b1)
+ begin
+ n00i <= 0;
+ n00l <= 0;
+ n00O <= 0;
+ n01i <= 0;
+ n01l <= 0;
+ n01O <= 0;
+ n0ii <= 0;
+ n0il <= 0;
+ n0iO <= 0;
+ n0li <= 0;
+ n0ll <= 0;
+ n0lO <= 0;
+ n0Oi <= 0;
+ n0Ol <= 0;
+ n0OO <= 0;
+ n100i <= 0;
+ n100l <= 0;
+ n100O <= 0;
+ n101i <= 0;
+ n101l <= 0;
+ n101O <= 0;
+ n10i <= 0;
+ n10ii <= 0;
+ n10il <= 0;
+ n10iO <= 0;
+ n10l <= 0;
+ n10li <= 0;
+ n10ll <= 0;
+ n10lO <= 0;
+ n10O <= 0;
+ n10Oi <= 0;
+ n10Ol <= 0;
+ n10OO <= 0;
+ n110i <= 0;
+ n110l <= 0;
+ n110O <= 0;
+ n111i <= 0;
+ n111l <= 0;
+ n111O <= 0;
+ n11i <= 0;
+ n11ii <= 0;
+ n11il <= 0;
+ n11iO <= 0;
+ n11l <= 0;
+ n11li <= 0;
+ n11ll <= 0;
+ n11lO <= 0;
+ n11O <= 0;
+ n11Oi <= 0;
+ n11Ol <= 0;
+ n11OO <= 0;
+ n1i <= 0;
+ n1i0i <= 0;
+ n1i0l <= 0;
+ n1i0O <= 0;
+ n1i1i <= 0;
+ n1i1l <= 0;
+ n1i1O <= 0;
+ n1ii <= 0;
+ n1iii <= 0;
+ n1iil <= 0;
+ n1iiO <= 0;
+ n1il <= 0;
+ n1ili <= 0;
+ n1ill <= 0;
+ n1ilO <= 0;
+ n1iO <= 0;
+ n1iOi <= 0;
+ n1iOl <= 0;
+ n1iOO <= 0;
+ n1l0i <= 0;
+ n1l0l <= 0;
+ n1l0O <= 0;
+ n1l1i <= 0;
+ n1l1l <= 0;
+ n1l1O <= 0;
+ n1li <= 0;
+ n1lii <= 0;
+ n1lil <= 0;
+ n1liO <= 0;
+ n1ll <= 0;
+ n1lli <= 0;
+ n1lll <= 0;
+ n1lO <= 0;
+ n1O <= 0;
+ n1Oi <= 0;
+ n1Ol <= 0;
+ n1OO <= 0;
+ ni0i <= 0;
+ ni0l <= 0;
+ ni0O <= 0;
+ ni1i <= 0;
+ ni1l <= 0;
+ ni1O <= 0;
+ niii <= 0;
+ niil <= 0;
+ niilO <= 0;
+ niiO <= 0;
+ niiOi <= 0;
+ nili <= 0;
+ nill <= 0;
+ nilli <= 0;
+ nilO <= 0;
+ niOi <= 0;
+ niOii <= 0;
+ niOl <= 0;
+ niOli <= 0;
+ niOll <= 0;
+ niOlO <= 0;
+ niOO <= 0;
+ niOOi <= 0;
+ niOOl <= 0;
+ niOOO <= 0;
+ nl01i <= 0;
+ nl01l <= 0;
+ nl01O <= 0;
+ nl0i <= 0;
+ nl0l <= 0;
+ nl0O <= 0;
+ nl10i <= 0;
+ nl10l <= 0;
+ nl10O <= 0;
+ nl11i <= 0;
+ nl11l <= 0;
+ nl11O <= 0;
+ nl1i <= 0;
+ nl1ii <= 0;
+ nl1il <= 0;
+ nl1iO <= 0;
+ nl1l <= 0;
+ nl1li <= 0;
+ nl1ll <= 0;
+ nl1lO <= 0;
+ nl1O <= 0;
+ nl1Oi <= 0;
+ nl1Ol <= 0;
+ nl1OO <= 0;
+ nlii <= 0;
+ nlil <= 0;
+ nliO <= 0;
+ nliOi <= 0;
+ nliOl <= 0;
+ nliOO <= 0;
+ nll0i <= 0;
+ nll0l <= 0;
+ nll0O <= 0;
+ nll1i <= 0;
+ nll1l <= 0;
+ nll1O <= 0;
+ nlli <= 0;
+ nllii <= 0;
+ nllil <= 0;
+ nlll <= 0;
+ nllli <= 0;
+ nllll <= 0;
+ nlllO <= 0;
+ nllO <= 0;
+ nllO0i <= 0;
+ nllO0l <= 0;
+ nllO0O <= 0;
+ nllO1i <= 0;
+ nllO1l <= 0;
+ nllO1O <= 0;
+ nllOi <= 0;
+ nllOii <= 0;
+ nllOil <= 0;
+ nllOiO <= 0;
+ nllOl <= 0;
+ nllOli <= 0;
+ nllOll <= 0;
+ nllOlO <= 0;
+ nllOO <= 0;
+ nllOOi <= 0;
+ nllOOl <= 0;
+ nllOOO <= 0;
+ nlO00i <= 0;
+ nlO00l <= 0;
+ nlO00O <= 0;
+ nlO01i <= 0;
+ nlO01l <= 0;
+ nlO01O <= 0;
+ nlO0i <= 0;
+ nlO0ii <= 0;
+ nlO0il <= 0;
+ nlO0iO <= 0;
+ nlO0l <= 0;
+ nlO0li <= 0;
+ nlO0ll <= 0;
+ nlO0lO <= 0;
+ nlO0O <= 0;
+ nlO0Oi <= 0;
+ nlO0Ol <= 0;
+ nlO0OO <= 0;
+ nlO10i <= 0;
+ nlO10l <= 0;
+ nlO10O <= 0;
+ nlO11i <= 0;
+ nlO11l <= 0;
+ nlO11O <= 0;
+ nlO1i <= 0;
+ nlO1ii <= 0;
+ nlO1il <= 0;
+ nlO1iO <= 0;
+ nlO1l <= 0;
+ nlO1li <= 0;
+ nlO1ll <= 0;
+ nlO1lO <= 0;
+ nlO1Oi <= 0;
+ nlO1Ol <= 0;
+ nlO1OO <= 0;
+ nlOi <= 0;
+ nlOi0i <= 0;
+ nlOi0l <= 0;
+ nlOi0O <= 0;
+ nlOi1i <= 0;
+ nlOi1l <= 0;
+ nlOi1O <= 0;
+ nlOii <= 0;
+ nlOiii <= 0;
+ nlOiil <= 0;
+ nlOiiO <= 0;
+ nlOil <= 0;
+ nlOili <= 0;
+ nlOill <= 0;
+ nlOilO <= 0;
+ nlOiO <= 0;
+ nlOiOi <= 0;
+ nlOiOl <= 0;
+ nlOiOO <= 0;
+ nlOl <= 0;
+ nlOl0i <= 0;
+ nlOl0l <= 0;
+ nlOl0O <= 0;
+ nlOl1i <= 0;
+ nlOl1l <= 0;
+ nlOl1O <= 0;
+ nlOli <= 0;
+ nlOlii <= 0;
+ nlOlil <= 0;
+ nlOliO <= 0;
+ nlOll <= 0;
+ nlOlli <= 0;
+ nlOlll <= 0;
+ nlOllO <= 0;
+ nlOlO <= 0;
+ nlOlOi <= 0;
+ nlOlOl <= 0;
+ nlOlOO <= 0;
+ nlOO <= 0;
+ nlOO0i <= 0;
+ nlOO0l <= 0;
+ nlOO0O <= 0;
+ nlOO1i <= 0;
+ nlOO1l <= 0;
+ nlOO1O <= 0;
+ nlOOi <= 0;
+ nlOOii <= 0;
+ nlOOil <= 0;
+ nlOOiO <= 0;
+ nlOOl <= 0;
+ nlOOli <= 0;
+ nlOOll <= 0;
+ nlOOlO <= 0;
+ nlOOO <= 0;
+ nlOOOi <= 0;
+ nlOOOl <= 0;
+ nlOOOO <= 0;
+ end
+ else
+ begin
+ n00i <= b[4];
+ n00l <= b[5];
+ n00O <= b[6];
+ n01i <= b[1];
+ n01l <= b[2];
+ n01O <= b[3];
+ n0ii <= b[7];
+ n0il <= b[8];
+ n0iO <= b[9];
+ n0li <= b[10];
+ n0ll <= b[11];
+ n0lO <= b[12];
+ n0Oi <= b[13];
+ n0Ol <= b[14];
+ n0OO <= b[15];
+ n100i <= n1ilO;
+ n100l <= n1iOi;
+ n100O <= n1iOl;
+ n101i <= n1iiO;
+ n101l <= n1ili;
+ n101O <= n1ill;
+ n10i <= wire_n0i_o[37];
+ n10ii <= n1iOO;
+ n10il <= n1l1i;
+ n10iO <= n1l1l;
+ n10l <= wire_n0i_o[38];
+ n10li <= n1l1O;
+ n10ll <= n1l0i;
+ n10lO <= n1l0l;
+ n10O <= wire_n0i_o[39];
+ n10Oi <= n1l0O;
+ n10Ol <= n1lii;
+ n10OO <= n1lil;
+ n110i <= n10lO;
+ n110l <= n10Oi;
+ n110O <= n10Ol;
+ n111i <= n10iO;
+ n111l <= n10li;
+ n111O <= n10ll;
+ n11i <= wire_n0i_o[34];
+ n11ii <= n10OO;
+ n11il <= n1i1i;
+ n11iO <= n1i1l;
+ n11l <= wire_n0i_o[35];
+ n11li <= n1i1O;
+ n11ll <= n1i0i;
+ n11lO <= n1i0l;
+ n11O <= wire_n0i_o[36];
+ n11Oi <= n1i0O;
+ n11Ol <= n1iii;
+ n11OO <= n1iil;
+ n1i <= a[22];
+ n1i0i <= wire_niOiO_o[1];
+ n1i0l <= wire_niOiO_o[2];
+ n1i0O <= wire_niOiO_o[3];
+ n1i1i <= n1liO;
+ n1i1l <= n1lli;
+ n1i1O <= n1lll;
+ n1ii <= wire_n0i_o[40];
+ n1iii <= wire_niOiO_o[4];
+ n1iil <= wire_niOiO_o[5];
+ n1iiO <= wire_niOiO_o[6];
+ n1il <= wire_n0i_o[41];
+ n1ili <= wire_niOiO_o[7];
+ n1ill <= wire_niOiO_o[8];
+ n1ilO <= wire_niOiO_o[9];
+ n1iO <= wire_n0i_o[42];
+ n1iOi <= wire_niOiO_o[10];
+ n1iOl <= wire_niOiO_o[11];
+ n1iOO <= wire_niOiO_o[12];
+ n1l0i <= wire_niOiO_o[16];
+ n1l0l <= wire_niOiO_o[17];
+ n1l0O <= wire_niOiO_o[18];
+ n1l1i <= wire_niOiO_o[13];
+ n1l1l <= wire_niOiO_o[14];
+ n1l1O <= wire_niOiO_o[15];
+ n1li <= wire_n0i_o[43];
+ n1lii <= wire_niOiO_o[19];
+ n1lil <= wire_niOiO_o[20];
+ n1liO <= wire_niOiO_o[21];
+ n1ll <= wire_n0i_o[44];
+ n1lli <= wire_niOiO_o[22];
+ n1lll <= wire_niOiO_o[23];
+ n1lO <= wire_n0i_o[45];
+ n1O <= nlllOl;
+ n1Oi <= wire_n0i_o[46];
+ n1Ol <= wire_n0i_o[47];
+ n1OO <= b[0];
+ ni0i <= b[19];
+ ni0l <= b[20];
+ ni0O <= b[21];
+ ni1i <= b[16];
+ ni1l <= b[17];
+ ni1O <= b[18];
+ niii <= b[22];
+ niil <= nlllOl;
+ niilO <= wire_niiOO_o;
+ niiO <= a[0];
+ niiOi <= wire_nilll_o[14];
+ nili <= a[1];
+ nill <= a[2];
+ nilli <= wire_niOil_o[14];
+ nilO <= a[3];
+ niOi <= a[4];
+ niOii <= wire_nl00i_dataout;
+ niOl <= a[5];
+ niOli <= wire_nl00l_dataout;
+ niOll <= wire_nl00O_dataout;
+ niOlO <= wire_nl0ii_dataout;
+ niOO <= a[6];
+ niOOi <= wire_nl0il_dataout;
+ niOOl <= wire_nl0iO_dataout;
+ niOOO <= wire_nl0li_dataout;
+ nl01i <= wire_nlill_dataout;
+ nl01l <= wire_nlilO_dataout;
+ nl01O <= wire_nlliO_o[1];
+ nl0i <= a[10];
+ nl0l <= a[11];
+ nl0O <= a[12];
+ nl10i <= wire_nl0Ol_dataout;
+ nl10l <= wire_nl0OO_dataout;
+ nl10O <= wire_nli1i_dataout;
+ nl11i <= wire_nl0ll_dataout;
+ nl11l <= wire_nl0lO_dataout;
+ nl11O <= wire_nl0Oi_dataout;
+ nl1i <= a[7];
+ nl1ii <= wire_nli1l_dataout;
+ nl1il <= wire_nli1O_dataout;
+ nl1iO <= wire_nli0i_dataout;
+ nl1l <= a[8];
+ nl1li <= wire_nli0l_dataout;
+ nl1ll <= wire_nli0O_dataout;
+ nl1lO <= wire_nliii_dataout;
+ nl1O <= a[9];
+ nl1Oi <= wire_nliil_dataout;
+ nl1Ol <= wire_nliiO_dataout;
+ nl1OO <= wire_nlili_dataout;
+ nlii <= a[13];
+ nlil <= a[14];
+ nliO <= a[15];
+ nliOi <= wire_nlliO_o[2];
+ nliOl <= wire_nlliO_o[3];
+ nliOO <= wire_nlliO_o[4];
+ nll0i <= wire_nlliO_o[8];
+ nll0l <= wire_nlliO_o[9];
+ nll0O <= wire_nlliO_o[10];
+ nll1i <= wire_nlliO_o[5];
+ nll1l <= wire_nlliO_o[6];
+ nll1O <= wire_nlliO_o[7];
+ nlli <= a[16];
+ nllii <= wire_nlliO_o[11];
+ nllil <= wire_nlO1O_o[0];
+ nlll <= a[17];
+ nllli <= wire_nlO1O_o[1];
+ nllll <= wire_nlO1O_o[2];
+ nlllO <= wire_nlO1O_o[3];
+ nllO <= a[18];
+ nllO0i <= nlllil;
+ nllO0l <= nllO0O;
+ nllO0O <= nllO0i;
+ nllO1i <= nllliO;
+ nllO1l <= nllO1O;
+ nllO1O <= nllO1i;
+ nllOi <= wire_nlO1O_o[4];
+ nllOii <= (nllO1l & nllO0l);
+ nllOil <= nlllii;
+ nllOiO <= nllOli;
+ nllOl <= wire_nlO1O_o[5];
+ nllOli <= nllOll;
+ nllOll <= nllOil;
+ nllOlO <= nlll0O;
+ nllOO <= wire_nlO1O_o[6];
+ nllOOi <= nllOOl;
+ nllOOl <= nllOlO;
+ nllOOO <= nlll0l;
+ nlO00i <= n1Ol;
+ nlO00l <= nllil;
+ nlO00O <= nllli;
+ nlO01i <= nlO01l;
+ nlO01l <= nlO1Oi;
+ nlO01O <= ((~ nlO1lO) & nlO1Ol);
+ nlO0i <= wire_n0i_o[22];
+ nlO0ii <= nllll;
+ nlO0il <= nlllO;
+ nlO0iO <= nllOi;
+ nlO0l <= wire_n0i_o[23];
+ nlO0li <= nllOl;
+ nlO0ll <= nllOO;
+ nlO0lO <= nlO1i;
+ nlO0O <= wire_n0i_o[24];
+ nlO0Oi <= nlO1l;
+ nlO0Ol <= wire_niOiO_o[24];
+ nlO0OO <= wire_niOiO_o[25];
+ nlO10i <= nlll0i;
+ nlO10l <= nlO10O;
+ nlO10O <= nlO1ii;
+ nlO11i <= nlO11l;
+ nlO11l <= nllOOO;
+ nlO11O <= (nllOOi & nlO11i);
+ nlO1i <= wire_nlO1O_o[7];
+ nlO1ii <= nlO10i;
+ nlO1il <= (~ nllOOi);
+ nlO1iO <= nlO11i;
+ nlO1l <= wire_nlO1O_o[8];
+ nlO1li <= (~ nllO1l);
+ nlO1ll <= nllO0l;
+ nlO1lO <= (((nllOii & nllOiO) | (nlO11O & nlO10l)) | ((nlO1il & nlO1iO) | (nlO1li & nlO1ll)));
+ nlO1Oi <= (a[31] ^ b[31]);
+ nlO1Ol <= nlO1OO;
+ nlO1OO <= nlO01i;
+ nlOi <= a[19];
+ nlOi0i <= wire_niOiO_o[29];
+ nlOi0l <= wire_niOiO_o[30];
+ nlOi0O <= wire_niOiO_o[31];
+ nlOi1i <= wire_niOiO_o[26];
+ nlOi1l <= wire_niOiO_o[27];
+ nlOi1O <= wire_niOiO_o[28];
+ nlOii <= wire_n0i_o[25];
+ nlOiii <= wire_niOiO_o[32];
+ nlOiil <= wire_niOiO_o[33];
+ nlOiiO <= wire_niOiO_o[34];
+ nlOil <= wire_n0i_o[26];
+ nlOili <= wire_niOiO_o[35];
+ nlOill <= nlOl0i;
+ nlOilO <= nlOl0l;
+ nlOiO <= wire_n0i_o[27];
+ nlOiOi <= nlOl0O;
+ nlOiOl <= nlOlii;
+ nlOiOO <= nlOlil;
+ nlOl <= a[20];
+ nlOl0i <= nlO0Ol;
+ nlOl0l <= nlO0OO;
+ nlOl0O <= nlOi1i;
+ nlOl1i <= nlOliO;
+ nlOl1l <= nlOlli;
+ nlOl1O <= nlOlll;
+ nlOli <= wire_n0i_o[28];
+ nlOlii <= nlOi1l;
+ nlOlil <= nlOi1O;
+ nlOliO <= nlOi0i;
+ nlOll <= wire_n0i_o[29];
+ nlOlli <= nlOi0l;
+ nlOlll <= nlOi0O;
+ nlOllO <= ((~ nllOiO) & (~ nlO1iO));
+ nlOlO <= wire_n0i_o[30];
+ nlOlOi <= ((~ nlO10l) & (~ nlO1ll));
+ nlOlOl <= nllOii;
+ nlOlOO <= nlO11O;
+ nlOO <= a[21];
+ nlOO0i <= n11lO;
+ nlOO0l <= n11Oi;
+ nlOO0O <= n11Ol;
+ nlOO1i <= nllOiO;
+ nlOO1l <= nlO10l;
+ nlOO1O <= n11ll;
+ nlOOi <= wire_n0i_o[31];
+ nlOOii <= n11OO;
+ nlOOil <= n101i;
+ nlOOiO <= n101l;
+ nlOOl <= wire_n0i_o[32];
+ nlOOli <= n101O;
+ nlOOll <= n100i;
+ nlOOlO <= n100l;
+ nlOOO <= wire_n0i_o[33];
+ nlOOOi <= n100O;
+ nlOOOl <= n10ii;
+ nlOOOO <= n10il;
+ end
+ end
+ initial
+ begin
+ niliO = 0;
+ end
+ always @ ( posedge clk or posedge areset)
+ begin
+ if (areset == 1'b1)
+ begin
+ niliO <= 1;
+ end
+ else
+ begin
+ niliO <= wire_niiOl_o;
+ end
+ end
+ event niliO_event;
+ initial
+ #1 ->niliO_event;
+ always @(niliO_event)
+ niliO <= 1;
+ assign wire_nl00i_dataout = ((~ n1Ol) === 1'b1) ? nlO0i : nlO0l;
+ assign wire_nl00l_dataout = ((~ n1Ol) === 1'b1) ? nlO0l : nlO0O;
+ assign wire_nl00O_dataout = ((~ n1Ol) === 1'b1) ? nlO0O : nlOii;
+ assign wire_nl0ii_dataout = ((~ n1Ol) === 1'b1) ? nlOii : nlOil;
+ assign wire_nl0il_dataout = ((~ n1Ol) === 1'b1) ? nlOil : nlOiO;
+ assign wire_nl0iO_dataout = ((~ n1Ol) === 1'b1) ? nlOiO : nlOli;
+ assign wire_nl0li_dataout = ((~ n1Ol) === 1'b1) ? nlOli : nlOll;
+ assign wire_nl0ll_dataout = ((~ n1Ol) === 1'b1) ? nlOll : nlOlO;
+ assign wire_nl0lO_dataout = ((~ n1Ol) === 1'b1) ? nlOlO : nlOOi;
+ assign wire_nl0Oi_dataout = ((~ n1Ol) === 1'b1) ? nlOOi : nlOOl;
+ assign wire_nl0Ol_dataout = ((~ n1Ol) === 1'b1) ? nlOOl : nlOOO;
+ assign wire_nl0OO_dataout = ((~ n1Ol) === 1'b1) ? nlOOO : n11i;
+ assign wire_nli0i_dataout = ((~ n1Ol) === 1'b1) ? n10i : n10l;
+ assign wire_nli0l_dataout = ((~ n1Ol) === 1'b1) ? n10l : n10O;
+ assign wire_nli0O_dataout = ((~ n1Ol) === 1'b1) ? n10O : n1ii;
+ assign wire_nli1i_dataout = ((~ n1Ol) === 1'b1) ? n11i : n11l;
+ assign wire_nli1l_dataout = ((~ n1Ol) === 1'b1) ? n11l : n11O;
+ assign wire_nli1O_dataout = ((~ n1Ol) === 1'b1) ? n11O : n10i;
+ assign wire_nliii_dataout = ((~ n1Ol) === 1'b1) ? n1ii : n1il;
+ assign wire_nliil_dataout = ((~ n1Ol) === 1'b1) ? n1il : n1iO;
+ assign wire_nliiO_dataout = ((~ n1Ol) === 1'b1) ? n1iO : n1li;
+ assign wire_nlili_dataout = ((~ n1Ol) === 1'b1) ? n1li : n1ll;
+ assign wire_nlill_dataout = ((~ n1Ol) === 1'b1) ? n1ll : n1lO;
+ assign wire_nlilO_dataout = ((~ n1Ol) === 1'b1) ? n1lO : n1Oi;
+ oper_add nilll
+ (
+ .a({{3{(~ nlOili)}}, (~ nlOiiO), (~ nlOiil), (~ nlOiii), (~ nlOi0O), (~ nlOi0l), (~ nlOi0i), (~ nlOi1O), (~ nlOi1l), (~ nlOi1i), (~ nlO0OO), (~ nlO0Ol), 1'b1}),
+ .b({{14{1'b0}}, 1'b1}),
+ .cin(1'b0),
+ .cout(),
+ .o(wire_nilll_o));
+ defparam
+ nilll.sgate_representation = 0,
+ nilll.width_a = 15,
+ nilll.width_b = 15,
+ nilll.width_o = 15;
+ oper_add niOil
+ (
+ .a({{3{nlOili}}, nlOiiO, nlOiil, nlOiii, nlOi0O, nlOi0l, nlOi0i, nlOi1O, nlOi1l, nlOi1i, nlO0OO, nlO0Ol, 1'b1}),
+ .b({{6{1'b1}}, {8{1'b0}}, 1'b1}),
+ .cin(1'b0),
+ .cout(),
+ .o(wire_niOil_o));
+ defparam
+ niOil.sgate_representation = 0,
+ niOil.width_a = 15,
+ niOil.width_b = 15,
+ niOil.width_o = 15;
+ oper_add niOiO
+ (
+ .a({{3{nllii}}, nll0O, nll0l, nll0i, nll1O, nll1l, nll1i, nliOO, nliOl, nliOi, nl01O, nl01l, nl01i, nl1OO, nl1Ol, nl1Oi, nl1lO, nl1ll, nl1li, nl1iO, nl1il, nl1ii, nl10O, nl10l, nl10i, nl11O, nl11l, nl11i, niOOO, niOOl, niOOi, niOlO, niOll, niOli, niOii}),
+ .b({{12{1'b0}}, nlO00i, {23{1'b0}}, 1'b1}),
+ .cin(1'b0),
+ .cout(),
+ .o(wire_niOiO_o));
+ defparam
+ niOiO.sgate_representation = 0,
+ niOiO.width_a = 37,
+ niOiO.width_b = 37,
+ niOiO.width_o = 37;
+ oper_add nlliO
+ (
+ .a({{3{1'b0}}, nlO0Oi, nlO0lO, nlO0ll, nlO0li, nlO0iO, nlO0il, nlO0ii, nlO00O, nlO00l, 1'b1}),
+ .b({{5{1'b1}}, {7{1'b0}}, 1'b1}),
+ .cin(1'b0),
+ .cout(),
+ .o(wire_nlliO_o));
+ defparam
+ nlliO.sgate_representation = 0,
+ nlliO.width_a = 13,
+ nlliO.width_b = 13,
+ nlliO.width_o = 13;
+ oper_add nlO1O
+ (
+ .a({1'b0, a[30:23]}),
+ .b({1'b0, b[30:23]}),
+ .cin(1'b0),
+ .cout(),
+ .o(wire_nlO1O_o));
+ defparam
+ nlO1O.sgate_representation = 0,
+ nlO1O.width_a = 9,
+ nlO1O.width_b = 9,
+ nlO1O.width_o = 9;
+ oper_mult n0i
+ (
+ .a({n1O, n1i, nlOO, nlOl, nlOi, nllO, nlll, nlli, nliO, nlil, nlii, nl0O, nl0l, nl0i, nl1O, nl1l, nl1i, niOO, niOl, niOi, nilO, nill, nili, niiO}),
+ .b({niil, niii, ni0O, ni0l, ni0i, ni1O, ni1l, ni1i, n0OO, n0Ol, n0Oi, n0lO, n0ll, n0li, n0iO, n0il, n0ii, n00O, n00l, n00i, n01O, n01l, n01i, n1OO}),
+ .o(wire_n0i_o));
+ defparam
+ n0i.sgate_representation = 0,
+ n0i.width_a = 24,
+ n0i.width_b = 24,
+ n0i.width_o = 48;
+ oper_mux ni00i
+ (
+ .data({{2{1'b0}}, nlOOll, 1'b0}),
+ .o(wire_ni00i_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni00i.width_data = 4,
+ ni00i.width_sel = 2;
+ oper_mux ni00l
+ (
+ .data({{2{1'b0}}, nlOOlO, 1'b0}),
+ .o(wire_ni00l_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni00l.width_data = 4,
+ ni00l.width_sel = 2;
+ oper_mux ni00O
+ (
+ .data({{2{1'b0}}, nlOOOi, 1'b0}),
+ .o(wire_ni00O_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni00O.width_data = 4,
+ ni00O.width_sel = 2;
+ oper_mux ni01i
+ (
+ .data({{2{1'b0}}, nlOOil, 1'b0}),
+ .o(wire_ni01i_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni01i.width_data = 4,
+ ni01i.width_sel = 2;
+ oper_mux ni01l
+ (
+ .data({{2{1'b0}}, nlOOiO, 1'b0}),
+ .o(wire_ni01l_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni01l.width_data = 4,
+ ni01l.width_sel = 2;
+ oper_mux ni01O
+ (
+ .data({{2{1'b0}}, nlOOli, 1'b0}),
+ .o(wire_ni01O_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni01O.width_data = 4,
+ ni01O.width_sel = 2;
+ oper_mux ni0ii
+ (
+ .data({{2{1'b0}}, nlOOOl, 1'b0}),
+ .o(wire_ni0ii_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0ii.width_data = 4,
+ ni0ii.width_sel = 2;
+ oper_mux ni0il
+ (
+ .data({{2{1'b0}}, nlOOOO, 1'b0}),
+ .o(wire_ni0il_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0il.width_data = 4,
+ ni0il.width_sel = 2;
+ oper_mux ni0iO
+ (
+ .data({{2{1'b0}}, n111i, 1'b0}),
+ .o(wire_ni0iO_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0iO.width_data = 4,
+ ni0iO.width_sel = 2;
+ oper_mux ni0li
+ (
+ .data({{2{1'b0}}, n111l, 1'b0}),
+ .o(wire_ni0li_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0li.width_data = 4,
+ ni0li.width_sel = 2;
+ oper_mux ni0ll
+ (
+ .data({{2{1'b0}}, n111O, 1'b0}),
+ .o(wire_ni0ll_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0ll.width_data = 4,
+ ni0ll.width_sel = 2;
+ oper_mux ni0lO
+ (
+ .data({{2{1'b0}}, n110i, 1'b0}),
+ .o(wire_ni0lO_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0lO.width_data = 4,
+ ni0lO.width_sel = 2;
+ oper_mux ni0Oi
+ (
+ .data({{2{1'b0}}, n110l, 1'b0}),
+ .o(wire_ni0Oi_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0Oi.width_data = 4,
+ ni0Oi.width_sel = 2;
+ oper_mux ni0Ol
+ (
+ .data({{2{1'b0}}, n110O, 1'b0}),
+ .o(wire_ni0Ol_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0Ol.width_data = 4,
+ ni0Ol.width_sel = 2;
+ oper_mux ni0OO
+ (
+ .data({{2{1'b0}}, n11ii, 1'b0}),
+ .o(wire_ni0OO_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni0OO.width_data = 4,
+ ni0OO.width_sel = 2;
+ oper_mux ni1ll
+ (
+ .data({1'b1, 1'b0, nlOO1O, 1'b0}),
+ .o(wire_ni1ll_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni1ll.width_data = 4,
+ ni1ll.width_sel = 2;
+ oper_mux ni1lO
+ (
+ .data({{2{1'b0}}, nlOO0i, 1'b0}),
+ .o(wire_ni1lO_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni1lO.width_data = 4,
+ ni1lO.width_sel = 2;
+ oper_mux ni1Oi
+ (
+ .data({{2{1'b0}}, nlOO0l, 1'b0}),
+ .o(wire_ni1Oi_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni1Oi.width_data = 4,
+ ni1Oi.width_sel = 2;
+ oper_mux ni1Ol
+ (
+ .data({{2{1'b0}}, nlOO0O, 1'b0}),
+ .o(wire_ni1Ol_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni1Ol.width_data = 4,
+ ni1Ol.width_sel = 2;
+ oper_mux ni1OO
+ (
+ .data({{2{1'b0}}, nlOOii, 1'b0}),
+ .o(wire_ni1OO_o),
+ .sel({niilO, niliO}));
+ defparam
+ ni1OO.width_data = 4,
+ ni1OO.width_sel = 2;
+ oper_mux nii0i
+ (
+ .data({{2{1'b1}}, nlOill, 1'b0}),
+ .o(wire_nii0i_o),
+ .sel({niilO, niliO}));
+ defparam
+ nii0i.width_data = 4,
+ nii0i.width_sel = 2;
+ oper_mux nii0l
+ (
+ .data({{2{1'b1}}, nlOilO, 1'b0}),
+ .o(wire_nii0l_o),
+ .sel({niilO, niliO}));
+ defparam
+ nii0l.width_data = 4,
+ nii0l.width_sel = 2;
+ oper_mux nii0O
+ (
+ .data({{2{1'b1}}, nlOiOi, 1'b0}),
+ .o(wire_nii0O_o),
+ .sel({niilO, niliO}));
+ defparam
+ nii0O.width_data = 4,
+ nii0O.width_sel = 2;
+ oper_mux nii1i
+ (
+ .data({{2{1'b0}}, n11il, 1'b0}),
+ .o(wire_nii1i_o),
+ .sel({niilO, niliO}));
+ defparam
+ nii1i.width_data = 4,
+ nii1i.width_sel = 2;
+ oper_mux nii1l
+ (
+ .data({{2{1'b0}}, n11iO, 1'b0}),
+ .o(wire_nii1l_o),
+ .sel({niilO, niliO}));
+ defparam
+ nii1l.width_data = 4,
+ nii1l.width_sel = 2;
+ oper_mux nii1O
+ (
+ .data({{2{1'b0}}, n11li, 1'b0}),
+ .o(wire_nii1O_o),
+ .sel({niilO, niliO}));
+ defparam
+ nii1O.width_data = 4,
+ nii1O.width_sel = 2;
+ oper_mux niiii
+ (
+ .data({{2{1'b1}}, nlOiOl, 1'b0}),
+ .o(wire_niiii_o),
+ .sel({niilO, niliO}));
+ defparam
+ niiii.width_data = 4,
+ niiii.width_sel = 2;
+ oper_mux niiil
+ (
+ .data({{2{1'b1}}, nlOiOO, 1'b0}),
+ .o(wire_niiil_o),
+ .sel({niilO, niliO}));
+ defparam
+ niiil.width_data = 4,
+ niiil.width_sel = 2;
+ oper_mux niiiO
+ (
+ .data({{2{1'b1}}, nlOl1i, 1'b0}),
+ .o(wire_niiiO_o),
+ .sel({niilO, niliO}));
+ defparam
+ niiiO.width_data = 4,
+ niiiO.width_sel = 2;
+ oper_mux niili
+ (
+ .data({{2{1'b1}}, nlOl1l, 1'b0}),
+ .o(wire_niili_o),
+ .sel({niilO, niliO}));
+ defparam
+ niili.width_data = 4,
+ niili.width_sel = 2;
+ oper_mux niill
+ (
+ .data({{2{1'b1}}, nlOl1O, 1'b0}),
+ .o(wire_niill_o),
+ .sel({niilO, niliO}));
+ defparam
+ niill.width_data = 4,
+ niill.width_sel = 2;
+ oper_mux niiOl
+ (
+ .data({{3{1'b0}}, 1'b1}),
+ .o(wire_niiOl_o),
+ .sel({nlllll, nlllli}));
+ defparam
+ niiOl.width_data = 4,
+ niiOl.width_sel = 2;
+ oper_mux niiOO
+ (
+ .data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}}),
+ .o(wire_niiOO_o),
+ .sel({nlO1lO, nlllll, nlllli}));
+ defparam
+ niiOO.width_data = 8,
+ niiOO.width_sel = 3;
+ assign
+ nlll0i = ((((((((~ a[23]) & (~ a[24])) & (~ a[25])) & (~ a[26])) & (~ a[27])) & (~ a[28])) & (~ a[29])) & (~ a[30])),
+ nlll0l = (((((((b[23] & b[24]) & b[25]) & b[26]) & b[27]) & b[28]) & b[29]) & b[30]),
+ nlll0O = (((((((((((((((((((((((~ b[0]) & (~ b[1])) & (~ b[2])) & (~ b[3])) & (~ b[4])) & (~ b[5])) & (~ b[6])) & (~ b[7])) & (~ b[8])) & (~ b[9])) & (~ b[10])) & (~ b[11])) & (~ b[12])) & (~ b[13])) & (~ b[14])) & (~ b[15])) & (~ b[16])) & (~ b[17])) & (~ b[18])) & (~ b[19])) & (~ b[20])) & (~ b[21])) & (~ b[22])),
+ nlllii = ((((((((~ b[23]) & (~ b[24])) & (~ b[25])) & (~ b[26])) & (~ b[27])) & (~ b[28])) & (~ b[29])) & (~ b[30])),
+ nlllil = (((((((a[23] & a[24]) & a[25]) & a[26]) & a[27]) & a[28]) & a[29]) & a[30]),
+ nllliO = (((((((((((((((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])) & (~ a[10])) & (~ a[11])) & (~ a[12])) & (~ a[13])) & (~ a[14])) & (~ a[15])) & (~ a[16])) & (~ a[17])) & (~ a[18])) & (~ a[19])) & (~ a[20])) & (~ a[21])) & (~ a[22])),
+ nlllli = ((nllllO & (~ niiOi)) | ((nlOlOi & nlOO1i) | ((nlOllO & nlOO1l) | (nlOO1i & nlOO1l)))),
+ nlllll = ((nllllO & (~ nilli)) | ((nlOllO & nlOlOl) | ((nlOlOi & nlOlOO) | (nlOlOl & nlOlOO)))),
+ nllllO = (nlOllO & nlOlOi),
+ nlllOl = 1'b1,
+ q = {nlO01O, wire_niill_o, wire_niili_o, wire_niiiO_o, wire_niiil_o, wire_niiii_o, wire_nii0O_o, wire_nii0l_o, wire_nii0i_o, wire_nii1O_o, wire_nii1l_o, wire_nii1i_o, wire_ni0OO_o, wire_ni0Ol_o, wire_ni0Oi_o, wire_ni0lO_o, wire_ni0ll_o, wire_ni0li_o, wire_ni0iO_o, wire_ni0il_o, wire_ni0ii_o, wire_ni00O_o, wire_ni00l_o, wire_ni00i_o, wire_ni01O_o, wire_ni01l_o, wire_ni01i_o, wire_ni1OO_o, wire_ni1Ol_o, wire_ni1Oi_o, wire_ni1lO_o, wire_ni1ll_o};
+endmodule //ip_fp_mul
+//synopsys translate_on
+//VALID FILE
diff --git a/ip/ip_fp_mul_sim/mentor/msim_setup.tcl b/ip/ip_fp_mul_sim/mentor/msim_setup.tcl
new file mode 100644
index 0000000..490a369
--- /dev/null
+++ b/ip/ip_fp_mul_sim/mentor/msim_setup.tcl
@@ -0,0 +1,272 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2023.10.21.04:56:13
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_fp_mul"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] {
+ set QUARTUS_INSTALL_DIR "/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
+ set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
+ set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
+ set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] {
+ set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+ echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries/
+ensure_lib ./libraries/work/
+vmap work ./libraries/work/
+vmap work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+ ensure_lib ./libraries/altera_ver/
+ vmap altera_ver ./libraries/altera_ver/
+ ensure_lib ./libraries/lpm_ver/
+ vmap lpm_ver ./libraries/lpm_ver/
+ ensure_lib ./libraries/sgate_ver/
+ vmap sgate_ver ./libraries/sgate_ver/
+ ensure_lib ./libraries/altera_mf_ver/
+ vmap altera_mf_ver ./libraries/altera_mf_ver/
+ ensure_lib ./libraries/altera_lnsim_ver/
+ vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
+ ensure_lib ./libraries/cyclonev_ver/
+ vmap cyclonev_ver ./libraries/cyclonev_ver/
+ ensure_lib ./libraries/cyclonev_hssi_ver/
+ vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
+ ensure_lib ./libraries/cyclonev_pcie_hip_ver/
+ vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
+}
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+ }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_mul.vo"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -voptargs=+acc option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -voptargs=+acc
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "file_copy -- Copy ROM/RAM files to simulation directory"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo " For most designs, this should be overridden"
+ echo " to enable the elab/elab_debug aliases."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
+ echo
+ echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
+ echo
+ echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
+ echo
+ echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
diff --git a/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh b/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh
new file mode 100755
index 0000000..05b6a3c
--- /dev/null
+++ b/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh
@@ -0,0 +1,152 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2023.10.21.04:56:13
+
+# ----------------------------------------
+# vcs - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, follow the guidelines below.
+#
+# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
+# below into a new file, e.g. named "vcs_sim.sh".
+#
+# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
+# a separate file, e.g. named "filelist.f".
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
+# # set the top-level simulation or testbench module/entity name.
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# # Source the Quartus-generated IP simulation script and do the following:
+# # - Compile the Quartus EDA simulation library and IP simulation files.
+# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
+# # - Compile the design and top-level simulation module/entity using
+# # information specified in "filelist.f".
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# # - Run the simulation.
+# #
+# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
+# TOP_LEVEL_NAME=<simulation top> \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# ----------------------------------------
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the Quartus-generated IP simulation script)
+# #
+# +systemverilogext+.sv
+# <design and testbench files, compile-time options, elaboration options>
+# #
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2023.10.21.04:56:13
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_fp_mul"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
+ $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
+ $QSYS_SIMDIR/ip_fp_mul.vo \
+ -top $TOP_LEVEL_NAME
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi
diff --git a/ip/ip_fp_mul_sim/synopsys/vcsmx/synopsys_sim.setup b/ip/ip_fp_mul_sim/synopsys/vcsmx/synopsys_sim.setup
new file mode 100644
index 0000000..5ae9b46
--- /dev/null
+++ b/ip/ip_fp_mul_sim/synopsys/vcsmx/synopsys_sim.setup
@@ -0,0 +1,13 @@
+
+WORK > DEFAULT
+DEFAULT: ./libraries/work/
+work: ./libraries/work/
+altera_ver: ./libraries/altera_ver/
+lpm_ver: ./libraries/lpm_ver/
+sgate_ver: ./libraries/sgate_ver/
+altera_mf_ver: ./libraries/altera_mf_ver/
+altera_lnsim_ver: ./libraries/altera_lnsim_ver/
+cyclonev_ver: ./libraries/cyclonev_ver/
+cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/
+cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
+LIBRARY_SCAN = TRUE
diff --git a/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh
new file mode 100755
index 0000000..6dbe5b1
--- /dev/null
+++ b/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh
@@ -0,0 +1,195 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2023.10.21.04:56:13
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_fp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_fp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2023.10.21.04:56:13
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_fp_mul"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_mul.vo"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-21 04:34:00 +0000