Fix output buffer atom errors

1 files changed, 42 insertions, 0 deletions

diff --git a/hps_sdram_p0_all_pins.txt b/hps_sdram_p0_all_pins.txt
new file mode 100755
index 0000000..70f45e1
--- /dev/null
+++ b/hps_sdram_p0_all_pins.txt
@@ -0,0 +1,42 @@
+# PIN MAP for core < hps_sdram_p0 >
+#
+# Generated by hps_sdram_p0_pin_assignments.tcl
+#
+# This file is for reference only and is not used by Quartus Prime
+#
+
+INSTANCE: plat|hps_0|hps_io|border|hps_sdram_inst
+DQS: memory_mem_dqs
+DQSn: memory_mem_dqs_n
+DQ: {{memory_mem_dq[0]} {memory_mem_dq[1]} {memory_mem_dq[2]} {memory_mem_dq[3]} {memory_mem_dq[4]} {memory_mem_dq[5]} {memory_mem_dq[6]} {memory_mem_dq[7]}}
+DM memory_mem_dm
+CK: memory_mem_ck
+CKn: memory_mem_ck_n
+ADD: {memory_mem_a[0]} {memory_mem_a[10]} {memory_mem_a[11]} {memory_mem_a[12]} {memory_mem_a[1]} {memory_mem_a[2]} {memory_mem_a[3]} {memory_mem_a[4]} {memory_mem_a[5]} {memory_mem_a[6]} {memory_mem_a[7]} {memory_mem_a[8]} {memory_mem_a[9]}
+CMD: memory_mem_cas_n memory_mem_cke memory_mem_cs_n memory_mem_odt memory_mem_ras_n memory_mem_we_n
+RESET: memory_mem_reset_n
+BA: {memory_mem_ba[0]} {memory_mem_ba[1]} {memory_mem_ba[2]}
+PLL CK: platform:plat|platform_hps_0:hps_0|platform_hps_0_hps_io:hps_io|platform_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk
+PLL DQ WRITE: platform:plat|platform_hps_0:hps_0|platform_hps_0_hps_io:hps_io|platform_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk
+PLL WRITE: platform:plat|platform_hps_0:hps_0|platform_hps_0_hps_io:hps_io|platform_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk
+PLL DRIVER CORE: _UNDEFINED_PIN_
+DQS_IN_CLOCK DQS_PIN (0): memory_mem_dqs
+DQS_IN_CLOCK DQS_SHIFTED_PIN (0): plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
+DQS_IN_CLOCK DIV_NAME (0): plat|hps_0|hps_io|border|hps_sdram_inst|div_clock_0
+DQS_IN_CLOCK DIV_PIN (0): plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]
+DQS_OUT_CLOCK SRC (0): plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
+DQS_OUT_CLOCK DST (0): memory_mem_dqs
+DQS_OUT_CLOCK DM (0): memory_mem_dm
+DQSN_OUT_CLOCK SRC (0): plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
+DQSN_OUT_CLOCK DST (0): memory_mem_dqs_n
+DQSN_OUT_CLOCK DM (0): memory_mem_dm
+READ CAPTURE DDIO: {*:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}
+AFI RESET REGISTERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:ureset|*:ureset_afi_clk|reset_reg[3]
+SYNCHRONIZERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].seq_read_fifo_reset_sync
+SYNCHRONIZATION FIFO WRITE ADDRESS REGISTERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*]
+SYNCHRONIZATION FIFO WRITE REGISTERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|*INPUT_DFF*
+SYNCHRONIZATION FIFO READ REGISTERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|dout[*]
+
+#
+# END OF INSTANCE: plat|hps_0|hps_io|border|hps_sdram_inst
+