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authorAlejandro Soto <alejandro@34project.org>2023-10-28 02:29:46 -0600
committerAlejandro Soto <alejandro@34project.org>2023-10-28 02:29:46 -0600
commit98d493f9c80f356cdbc2669150d772e451c3b80e (patch)
tree320f7c6b86ea5be5d07f848ec450663e9319de0b /core_hw.tcl
parent7c5974f80f2b549a45721053037e877bc6bda438 (diff)
platform: implement support for disabling CPUs
Diffstat (limited to '')
-rw-r--r--core_hw.tcl9
1 files changed, 9 insertions, 0 deletions
diff --git a/core_hw.tcl b/core_hw.tcl
index 0bdd457..0b0a2da 100644
--- a/core_hw.tcl
+++ b/core_hw.tcl
@@ -40,6 +40,7 @@ set_fileset_property QUARTUS_SYNTH TOP_LEVEL core
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file core.sv SYSTEM_VERILOG PATH rtl/core/core.sv TOP_LEVEL_FILE
+add_fileset_file bus_master.sv SYSTEM_VERILOG PATH rtl/core/bus_master.sv
add_fileset_file arm810.sv SYSTEM_VERILOG PATH rtl/core/arm810.sv
add_fileset_file mul.sv SYSTEM_VERILOG PATH rtl/core/mul.sv
add_fileset_file psr.sv SYSTEM_VERILOG PATH rtl/core/psr.sv
@@ -111,6 +112,14 @@ add_fileset_file exclusive.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/exclusive
#
# parameters
#
+add_parameter ID INTEGER 0
+set_parameter_property ID DEFAULT_VALUE 0
+set_parameter_property ID DISPLAY_NAME ID
+set_parameter_property ID TYPE INTEGER
+set_parameter_property ID UNITS None
+set_parameter_property ID ALLOWED_RANGES 0:3
+set_parameter_property ID AFFECTS_GENERATION false
+set_parameter_property ID HDL_PARAMETER true
#