Add reset signal to bus master

1 files changed, 40 insertions, 40 deletions

diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl
index 93da31b..f7f9760 100644
--- a/conspiracion_bus_master_hw.tcl
+++ b/conspiracion_bus_master_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 20.1
-# Thu Nov 03 05:39:37 GMT 2022
+# Wed Nov 09 13:54:58 GMT 2022
 # DO NOT MODIFY
 
 
 # 
 # conspiracion_bus_master "Toplevel bus master" v1.0
-#  2022.11.03.05:39:37
+#  2022.11.09.13:54:58
 # 
 # 
 
@@ -67,42 +67,6 @@ add_interface_port clock clk clk Input 1
 
 
 # 
-# connection point avalon_master
-# 
-add_interface avalon_master avalon start
-set_interface_property avalon_master addressUnits SYMBOLS
-set_interface_property avalon_master associatedClock clock
-set_interface_property avalon_master associatedReset reset_sink
-set_interface_property avalon_master bitsPerSymbol 8
-set_interface_property avalon_master burstOnBurstBoundariesOnly false
-set_interface_property avalon_master burstcountUnits WORDS
-set_interface_property avalon_master doStreamReads false
-set_interface_property avalon_master doStreamWrites false
-set_interface_property avalon_master holdTime 0
-set_interface_property avalon_master linewrapBursts false
-set_interface_property avalon_master maximumPendingReadTransactions 0
-set_interface_property avalon_master maximumPendingWriteTransactions 0
-set_interface_property avalon_master readLatency 0
-set_interface_property avalon_master readWaitTime 1
-set_interface_property avalon_master setupTime 0
-set_interface_property avalon_master timingUnits Cycles
-set_interface_property avalon_master writeWaitTime 0
-set_interface_property avalon_master ENABLED true
-set_interface_property avalon_master EXPORT_OF ""
-set_interface_property avalon_master PORT_NAME_MAP ""
-set_interface_property avalon_master CMSIS_SVD_VARIABLES ""
-set_interface_property avalon_master SVD_ADDRESS_GROUP ""
-
-add_interface_port avalon_master avl_address address Output 32
-add_interface_port avalon_master avl_read read Output 1
-add_interface_port avalon_master avl_readdata readdata Input 32
-add_interface_port avalon_master avl_write write Output 1
-add_interface_port avalon_master avl_writedata writedata Output 32
-add_interface_port avalon_master avl_byteenable byteenable Output 4
-add_interface_port avalon_master avl_waitrequest waitrequest Input 1
-
-
-# 
 # connection point reset_sink
 # 
 add_interface reset_sink reset end
@@ -114,7 +78,7 @@ set_interface_property reset_sink PORT_NAME_MAP ""
 set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
 set_interface_property reset_sink SVD_ADDRESS_GROUP ""
 
-add_interface_port reset_sink rst reset Input 1
+add_interface_port reset_sink rst_n reset_n Input 1
 
 
 # 
@@ -143,7 +107,7 @@ add_interface_port core cpu_clk cpu_clk Output 1
 # connection point irq
 # 
 add_interface irq interrupt start
-set_interface_property irq associatedAddressablePoint avalon_master
+set_interface_property irq associatedAddressablePoint avalon_master_1
 set_interface_property irq associatedClock clock
 set_interface_property irq associatedReset reset_sink
 set_interface_property irq irqScheme INDIVIDUAL_REQUESTS
@@ -155,3 +119,39 @@ set_interface_property irq SVD_ADDRESS_GROUP ""
 
 add_interface_port irq avl_irq irq Input 1
 
+
+# 
+# connection point avalon_master_1
+# 
+add_interface avalon_master_1 avalon start
+set_interface_property avalon_master_1 addressUnits SYMBOLS
+set_interface_property avalon_master_1 associatedClock clock
+set_interface_property avalon_master_1 associatedReset reset_sink
+set_interface_property avalon_master_1 bitsPerSymbol 8
+set_interface_property avalon_master_1 burstOnBurstBoundariesOnly false
+set_interface_property avalon_master_1 burstcountUnits WORDS
+set_interface_property avalon_master_1 doStreamReads false
+set_interface_property avalon_master_1 doStreamWrites false
+set_interface_property avalon_master_1 holdTime 0
+set_interface_property avalon_master_1 linewrapBursts false
+set_interface_property avalon_master_1 maximumPendingReadTransactions 0
+set_interface_property avalon_master_1 maximumPendingWriteTransactions 0
+set_interface_property avalon_master_1 readLatency 0
+set_interface_property avalon_master_1 readWaitTime 1
+set_interface_property avalon_master_1 setupTime 0
+set_interface_property avalon_master_1 timingUnits Cycles
+set_interface_property avalon_master_1 writeWaitTime 0
+set_interface_property avalon_master_1 ENABLED true
+set_interface_property avalon_master_1 EXPORT_OF ""
+set_interface_property avalon_master_1 PORT_NAME_MAP ""
+set_interface_property avalon_master_1 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_master_1 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_master_1 avl_address address Output 32
+add_interface_port avalon_master_1 avl_read read Output 1
+add_interface_port avalon_master_1 avl_readdata readdata Input 32
+add_interface_port avalon_master_1 avl_write write Output 1
+add_interface_port avalon_master_1 avl_writedata writedata Output 32
+add_interface_port avalon_master_1 avl_byteenable byteenable Output 4
+add_interface_port avalon_master_1 avl_waitrequest waitrequest Input 1
+