diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-02 11:02:18 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-02 11:02:18 -0600 |
| commit | 97bc74277d0e9672a55552ed1cded66ecb7d317e (patch) | |
| tree | 3938f0ee5aa86d9fae7a22d7a15f37026e62ab70 /conspiracion.qsf | |
| parent | 2734327402470cbc9a72ac6dde2d15e2253c8f14 (diff) | |
Make the fetch stage use the bus arbiter
Diffstat (limited to 'conspiracion.qsf')
| -rw-r--r-- | conspiracion.qsf | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index e8371d3..86add17 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -213,27 +213,27 @@ set_location_assignment PIN_AF14 -to clk_clk set_global_assignment -name SEARCH_PATH rtl -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/shifter.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/and.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/orr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cycles.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/isa.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/mmu.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/shifter.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/map.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/shifter.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/uarch.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/isa.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cycles.sv set_global_assignment -name QSYS_FILE platform.qsys set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv @@ -242,4 +242,4 @@ set_global_assignment -name SDC_FILE conspiracion.sdc -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |