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| author | Alejandro Soto <alejandro@34project.org> | 2022-12-10 19:36:38 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-10 19:36:38 -0600 |
| commit | 8026947ecdf9b023c3720b26bf257bf46f7a2805 (patch) | |
| tree | 8b2fbd0beb29c575730a76b010e8aa35977d5417 /conspiracion.qsf | |
| parent | 02f76bae32e295bf1da04e38dfa12dfbc5832aec (diff) | |
Implement rest of cp15 registers
Diffstat (limited to 'conspiracion.qsf')
| -rw-r--r-- | conspiracion.qsf | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index 5dab632..e026a5d 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -223,9 +223,18 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/psr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/select.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/stall.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/writeback.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cache.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cache_lockdown.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cp15.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cpuid.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/domain.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/far.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/fsr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/map.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/syscfg.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/tlb.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/tlb_lockdown.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/ttbr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/coproc.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv @@ -243,6 +252,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/snd.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/arbiter.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/format.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/mmu.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mul.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/conds.sv |