diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-10-02 01:46:44 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-02 01:46:44 -0600 |
| commit | 70d7dc9489f4d5b91d8138e0a341eec4ad7f15b0 (patch) | |
| tree | 19f6171ade81451d40a1daf582914525eaee100a /cache_hw.tcl | |
| parent | 7b329b833ec3f63b0195369e76b86cca1e5e3ad6 (diff) | |
rtl: implement exclusive monitor datapath
Diffstat (limited to 'cache_hw.tcl')
| -rw-r--r-- | cache_hw.tcl | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/cache_hw.tcl b/cache_hw.tcl index 7cae804..4a06546 100644 --- a/cache_hw.tcl +++ b/cache_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Sat Sep 30 02:25:24 GMT 2023 +# Mon Oct 02 07:43:58 GMT 2023 # DO NOT MODIFY # # cache "8KiB 1-way cache w/ controller" v1.0 -# 2023.09.30.02:25:24 +# 2023.10.02.07:43:58 # # @@ -127,6 +127,8 @@ add_interface_port core core_waitrequest waitrequest Output 1 add_interface_port core core_readdata readdata Output 32 add_interface_port core core_writedata writedata Input 32 add_interface_port core core_byteenable byteenable Input 4 +add_interface_port core core_lock lock Input 1 +add_interface_port core core_response response Output 2 set_interface_assignment core embeddedsw.configuration.isFlash 0 set_interface_assignment core embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment core embeddedsw.configuration.isNonVolatileStorage 0 |