platform: add mem master to gfx

3 files changed, 66 insertions, 5 deletions

diff --git a/gfx_hw.tcl b/gfx_hw.tcl
index 6a6d647..570d948 100644
--- a/gfx_hw.tcl
+++ b/gfx_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 20.1
-# Sat Oct 21 08:29:20 GMT 2023
+# Thu Oct 26 01:42:02 GMT 2023
 # DO NOT MODIFY
 
 
 # 
 # gfx "3D graphics accelerator" v1.0
-#  2023.10.21.08:29:20
+#  2023.10.26.01:42:02
 # 
 # 
 
@@ -103,7 +103,7 @@ set_interface_property cmd PORT_NAME_MAP ""
 set_interface_property cmd CMSIS_SVD_VARIABLES ""
 set_interface_property cmd SVD_ADDRESS_GROUP ""
 
-add_interface_port cmd cmd_address address Input 5
+add_interface_port cmd cmd_address address Input 6
 add_interface_port cmd cmd_read read Input 1
 add_interface_port cmd cmd_write write Input 1
 add_interface_port cmd cmd_writedata writedata Input 32
@@ -128,3 +128,39 @@ set_interface_property reset_sink SVD_ADDRESS_GROUP ""
 
 add_interface_port reset_sink rst_n reset_n Input 1
 
+
+# 
+# connection point mem
+# 
+add_interface mem avalon start
+set_interface_property mem addressUnits SYMBOLS
+set_interface_property mem associatedClock clock
+set_interface_property mem associatedReset reset_sink
+set_interface_property mem bitsPerSymbol 8
+set_interface_property mem burstOnBurstBoundariesOnly false
+set_interface_property mem burstcountUnits WORDS
+set_interface_property mem doStreamReads false
+set_interface_property mem doStreamWrites false
+set_interface_property mem holdTime 0
+set_interface_property mem linewrapBursts false
+set_interface_property mem maximumPendingReadTransactions 0
+set_interface_property mem maximumPendingWriteTransactions 0
+set_interface_property mem readLatency 0
+set_interface_property mem readWaitTime 1
+set_interface_property mem setupTime 0
+set_interface_property mem timingUnits Cycles
+set_interface_property mem writeWaitTime 0
+set_interface_property mem ENABLED true
+set_interface_property mem EXPORT_OF ""
+set_interface_property mem PORT_NAME_MAP ""
+set_interface_property mem CMSIS_SVD_VARIABLES ""
+set_interface_property mem SVD_ADDRESS_GROUP ""
+
+add_interface_port mem mem_address address Output 26
+add_interface_port mem mem_read read Output 1
+add_interface_port mem mem_write write Output 1
+add_interface_port mem mem_readdatavalid readdatavalid Input 1
+add_interface_port mem mem_readdata readdata Input 16
+add_interface_port mem mem_writedata writedata Output 16
+add_interface_port mem mem_waitrequest waitrequest Input 1
+
diff --git a/platform.qsys b/platform.qsys
index ebcff33..f0724b0 100644
--- a/platform.qsys
+++ b/platform.qsys
@@ -254,6 +254,14 @@
          type = "String";
       }
    }
+   element platform
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
    element pll_0
    {
       datum _sortIndex
@@ -1546,6 +1554,11 @@
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection kind="avalon" version="20.1" start="gfx_0.mem" end="vram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection kind="avalon" version="20.1" start="perf_0.mem_0" end="mm_bridge.s0">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv
index 233d285..1974991 100644
--- a/rtl/gfx/gfx.sv
+++ b/rtl/gfx/gfx.sv
@@ -5,17 +5,29 @@ module gfx
 	input  logic       clk,
 	                   rst_n,
 
-	input  logic[4:0]  cmd_address,
+	input  logic[5:0]  cmd_address,
 	input  logic       cmd_read,
 	                   cmd_write,
 	input  logic[31:0] cmd_writedata,
-	output logic[31:0] cmd_readdata
+	output logic[31:0] cmd_readdata,
+
+	input  logic       mem_waitrequest,
+	                   mem_readdatavalid,
+	input  logic[15:0] mem_readdata,
+	output logic[25:0] mem_address,
+	output logic       mem_read,
+	                   mem_write,
+	output logic[15:0] mem_writedata
 );
 
 	fp readdata, writedata;
 	mat4 a, b, q, hold_q;
 	logic start, done;
 
+	assign mem_address = 26'b0;
+	assign mem_read = 1;
+	assign mem_write = 0;
+
 	assign readdata = hold_q[cmd_address[3:2]][cmd_address[1:0]];
 	assign writedata = cmd_writedata[`FLOAT_BITS - 1:0];
 	assign cmd_readdata = {{($bits(cmd_readdata) - `FLOAT_BITS){1'b0}}, readdata};