diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-20 16:16:08 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-21 04:16:46 -0600 |
| commit | d2fc80b6d8b4a64efa00c8458ae94f6b44ddf6be (patch) | |
| tree | 8f9b3b81b36cb3b4deda5eebfd0de2ddc4f7e0ed | |
| parent | 42bbf5619d9ec4437abf8277d5a458257c3076f0 (diff) | |
Fix clock/reset timing in single-step, dsp_mul
| -rw-r--r-- | rtl/core/mul.sv | 6 | ||||
| -rw-r--r-- | rtl/top/conspiracion.sv | 9 | ||||
| -rw-r--r-- | tb/dsp_mul.sv | 4 |
3 files changed, 13 insertions, 6 deletions
diff --git a/rtl/core/mul.sv b/rtl/core/mul.sv index a05aff7..7c30d0c 100644 --- a/rtl/core/mul.sv +++ b/rtl/core/mul.sv @@ -22,7 +22,7 @@ module core_mul ready // 1 cuando la multiplicación está lista ); - logic wait_state; + logic[1:0] wait_state; dword c, q; assign ready = !start && wait_state == {$bits(wait_state){1'b0}}; @@ -34,7 +34,7 @@ module core_mul dsp_mul it ( .clock0(clk), - .aclr0(rst_n), + .aclr0(0), //TODO: parece ser active-high, así que no puede ir a rst_n .ena0(start || !ready), .dataa_0(a), .datab_0(b), @@ -58,6 +58,6 @@ module core_mul else if(wait_state > {$bits(wait_state){1'b0}}) wait_state <= wait_state - 1; else if(start) - wait_state <= 1; + wait_state <= {$bits(wait_state){1'b1}}; endmodule diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index c9e940f..4d09af8 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -3,9 +3,12 @@ module conspiracion input wire clk_clk, input wire rst_n, input wire halt, +`ifdef VERILATOR input wire step, - output wire cpu_halted, output wire breakpoint, +`endif + output wire cpu_halted, + output wire [12:0] memory_mem_a, output wire [2:0] memory_mem_ba, output wire memory_mem_ck, @@ -92,6 +95,10 @@ module conspiracion .bus_ready(ready), .bus_write(write), .bus_start(start), +`ifndef VERILATOR + .step(0), + .breakpoint(), +`endif .* ); diff --git a/tb/dsp_mul.sv b/tb/dsp_mul.sv index d6fcb6a..a46518c 100644 --- a/tb/dsp_mul.sv +++ b/tb/dsp_mul.sv @@ -26,8 +26,8 @@ module dsp_mul 2'b11: product = $signed(ext_a) * $signed(ext_b); endcase - always @(posedge clock0 or negedge aclr0) - if(!aclr0) begin + always @(posedge clock0 or posedge aclr0) + if(aclr0) begin result <= {64{1'bx}}; hold_a <= {32{1'bx}}; hold_b <= {32{1'bx}}; |