rtl/gfx: implement SP register files

4 files changed, 84 insertions, 5 deletions

diff --git a/gfx_hw.tcl b/gfx_hw.tcl
index 67bf5a9..aad3aef 100644
--- a/gfx_hw.tcl
+++ b/gfx_hw.tcl
@@ -82,6 +82,8 @@ add_fileset_file gfx_fifo.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fifo.sv
 add_fileset_file gfx_fifo_overflow.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fifo_overflow.sv
 add_fileset_file gfx_mem.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_mem.sv
 add_fileset_file gfx_sp.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_sp.sv
+add_fileset_file gfx_sp_file.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_sp_file.sv
+add_fileset_file gfx_sp_regs.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_sp_regs.sv
 add_fileset_file gfx_sp_batch.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_sp_batch.sv
 add_fileset_file gfx_sp_fetch.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_sp_fetch.sv
 add_fileset_file gfx_sp_decode.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_sp_decode.sv
diff --git a/rtl/gfx/gfx_sp.sv b/rtl/gfx/gfx_sp.sv
index 7add2db..4adac7e 100644
--- a/rtl/gfx/gfx_sp.sv
+++ b/rtl/gfx/gfx_sp.sv
@@ -65,8 +65,6 @@ module gfx_sp
 
 	gfx_sp_shuffler shuffler
 	(
-		.a(),
-		.b(),
 		.wb(shuffler_wb),
 		.deco(),
 		.in_ready(),
@@ -81,8 +79,6 @@ module gfx_sp
 
 	gfx_sp_combiner combiner
 	(
-		.a(),
-		.b(),
 		.wb(combiner_wb),
 		.deco(),
 		.in_ready(),
@@ -97,7 +93,6 @@ module gfx_sp
 
 	gfx_sp_stream stream
 	(
-		.a(),
 		.wb(stream_wb),
 		.deco(),
 		.in_ready(),
@@ -116,6 +111,17 @@ module gfx_sp
 		.*
 	);
 
+	mat4 a, b;
+
+	gfx_sp_regs regs
+	(
+		.rd_a_reg(),
+		.rd_b_reg(),
+		.rd_a_data(a),
+		.rd_b_data(b),
+		.*
+	);
+
 	logic batch_end, deco_ready;
 	assign deco_ready = 1;
 
diff --git a/rtl/gfx/gfx_sp_file.sv b/rtl/gfx/gfx_sp_file.sv
new file mode 100644
index 0000000..5dced6e
--- /dev/null
+++ b/rtl/gfx/gfx_sp_file.sv
@@ -0,0 +1,32 @@
+`include "gfx/gfx_defs.sv"
+
+module gfx_sp_file
+(
+	input  logic    clk,
+
+	input  vreg_num rd_reg,
+	output vec4     rd_data,
+
+	input  logic    wr,
+	input  vreg_num wr_reg,
+	input  vec4     wr_data
+);
+
+	vec4 file[1 << $bits(vreg_num)], hold_rd_data, hold_wr_data;
+	logic hold_wr;
+	vreg_num hold_rd_reg, hold_wr_reg;
+
+	always_ff @(posedge clk) begin
+		hold_wr <= wr;
+		hold_wr_reg <= wr_reg;
+		hold_wr_data <= wr_data;
+
+		rd_data <= hold_rd_data;
+		hold_rd_reg <= rd_reg;
+		hold_rd_data <= file[hold_rd_reg];
+
+		if (hold_wr)
+			file[hold_wr_reg] <= hold_wr_data;
+	end
+
+endmodule
diff --git a/rtl/gfx/gfx_sp_regs.sv b/rtl/gfx/gfx_sp_regs.sv
new file mode 100644
index 0000000..68aaf06
--- /dev/null
+++ b/rtl/gfx/gfx_sp_regs.sv
@@ -0,0 +1,39 @@
+`include "gfx/gfx_defs.sv"
+
+module gfx_sp_regs
+(
+	input  logic    clk,
+
+	input  vreg_num rd_a_reg,
+	output mat4     rd_a_data,
+
+	input  vreg_num rd_b_reg,
+	output mat4     rd_b_data,
+
+	input  logic    wr,
+	input  vreg_num wr_reg,
+	input  mat4     wr_data
+);
+
+	genvar i;
+	generate
+		for (i = 0; i < `GFX_SP_LANES; ++i) begin: lanes
+			gfx_sp_file a
+			(
+				.rd_reg(rd_a_reg),
+				.rd_data(rd_a_data[i]),
+				.wr_data(wr_data[i]),
+				.*
+			);
+
+			gfx_sp_file b
+			(
+				.rd_reg(rd_b_reg),
+				.rd_data(rd_b_data[i]),
+				.wr_data(wr_data[i]),
+				.*
+			);
+		end
+	endgenerate
+
+endmodule