Rename data_rw to data_wr in bus master

6 files changed, 13 insertions, 11 deletions

diff --git a/.gitignore b/.gitignore
index e9a11be..dcec9dd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -38,3 +38,4 @@ obj/
 platform/
 platform.sopcinfo
 hps_isw_handoff/
+*~
diff --git a/conspiracion.qsf b/conspiracion.qsf
index fd11788..acdf165 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -212,4 +212,5 @@ set_location_assignment PIN_W20 -to out[7]
 set_location_assignment PIN_Y21 -to done
 
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl
index 81b62d0..5f9816e 100644
--- a/conspiracion_bus_master_hw.tcl
+++ b/conspiracion_bus_master_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 20.1
-# Sun Sep 04 22:05:36 GMT 2022
+# Sun Sep 18 23:31:13 GMT 2022
 # DO NOT MODIFY
 
 
 # 
 # conspiracion_bus_master "Toplevel bus master" v1.0
-#  2022.09.04.22:05:36
+#  2022.09.18.23:31:13
 # 
 # 
 
@@ -131,7 +131,7 @@ set_interface_property core SVD_ADDRESS_GROUP ""
 
 add_interface_port core addr addr Input 30
 add_interface_port core data_rd data_rd Output 32
-add_interface_port core data_rw data_rw Input 32
+add_interface_port core data_wr data_wr Input 32
 add_interface_port core ready ready Output 1
 add_interface_port core write write Input 1
 add_interface_port core start start Input 1
diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv
index d350d80..6e29ac2 100644
--- a/rtl/bus/master.sv
+++ b/rtl/bus/master.sv
@@ -8,7 +8,7 @@ module bus_master
 	                   write,
 	output logic       ready,
 	output logic[31:0] data_rd,
-	input  logic[31:0] data_rw,
+	input  logic[31:0] data_wr,
 
 	output logic[31:0] avl_address,
 	output logic       avl_read,
@@ -33,7 +33,7 @@ module bus_master
 			avl_address <= {addr, 2'b00};
 			avl_read <= ~write;
 			avl_write <= write;
-			avl_writedata <= data_rw;
+			avl_writedata <= data_wr;
 			state <= WAIT;
 		end
 
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 174dceb..30aa95f 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -31,7 +31,7 @@ module conspiracion
 	} state;
 
 	logic[29:0] addr;
-	logic[31:0] data_rd, data_rw;
+	logic[31:0] data_rd, data_wr;
 	logic ready, write, start;
 
 	logic [7:0] leds;
@@ -40,7 +40,7 @@ module conspiracion
 	(
 		.master_0_core_addr(addr),
 		.master_0_core_data_rd(data_rd),
-		.master_0_core_data_rw(data_rw),
+		.master_0_core_data_wr(data_wr),
 		.master_0_core_ready(ready),
 		.master_0_core_write(write),
 		.master_0_core_start(start),
@@ -54,7 +54,7 @@ module conspiracion
 		done = 0;
 	end
 
-	assign data_rw[7:0] = out;
+	assign data_wr[7:0] = out;
 	assign write = dir;
 
 	always @(posedge clk_clk) unique case(state)
diff --git a/tb/platform.sv b/tb/platform.sv
index 7c2ef90..3d2521b 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -2,7 +2,7 @@ module platform (
 		input  wire        clk_clk,               //           clk.clk
 		input  wire [29:0] master_0_core_addr    /*verilator public*/,// master_0_core.addr
 		output wire [31:0] master_0_core_data_rd /*verilator public*/,//              .data_rd
-		input  wire [31:0] master_0_core_data_rw /*verilator public*/,//              .data_rw
+		input  wire [31:0] master_0_core_data_wr /*verilator public*/,//              .data_wr
 		output wire        master_0_core_ready   /*verilator public*/,//              .ready
 		input  wire        master_0_core_write   /*verilator public*/,//              .write
 		input  wire        master_0_core_start   /*verilator public*/,//              .start
@@ -42,7 +42,7 @@ module platform (
 		.write(master_0_core_write),
 		.ready(master_0_core_ready),
 		.data_rd(master_0_core_data_rd),
-		.data_rw(master_0_core_data_rw),
+		.data_wr(master_0_core_data_wr),
 		.*
 	);