Add bus master forward signals: irq, cpu_clk

4 files changed, 36 insertions, 4 deletions

diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl
index dadceca..93da31b 100644
--- a/conspiracion_bus_master_hw.tcl
+++ b/conspiracion_bus_master_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 20.1
-# Thu Nov 03 05:18:16 GMT 2022
+# Thu Nov 03 05:39:37 GMT 2022
 # DO NOT MODIFY
 
 
 # 
 # conspiracion_bus_master "Toplevel bus master" v1.0
-#  2022.11.03.05:18:16
+#  2022.11.03.05:39:37
 # 
 # 
 
@@ -135,4 +135,23 @@ add_interface_port core data_wr data_wr Input 32
 add_interface_port core ready ready Output 1
 add_interface_port core write write Input 1
 add_interface_port core start start Input 1
+add_interface_port core irq irq Output 1
+add_interface_port core cpu_clk cpu_clk Output 1
+
+
+# 
+# connection point irq
+# 
+add_interface irq interrupt start
+set_interface_property irq associatedAddressablePoint avalon_master
+set_interface_property irq associatedClock clock
+set_interface_property irq associatedReset reset_sink
+set_interface_property irq irqScheme INDIVIDUAL_REQUESTS
+set_interface_property irq ENABLED true
+set_interface_property irq EXPORT_OF ""
+set_interface_property irq PORT_NAME_MAP ""
+set_interface_property irq CMSIS_SVD_VARIABLES ""
+set_interface_property irq SVD_ADDRESS_GROUP ""
+
+add_interface_port irq avl_irq irq Input 1
 
diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
index e4a76d2..560cb67 100644
--- a/rtl/bus_master.sv
+++ b/rtl/bus_master.sv
@@ -9,6 +9,8 @@ module bus_master
 	output logic       ready,
 	output logic[31:0] data_rd,
 	input  logic[31:0] data_wr,
+	output logic       cpu_clk,
+	                   irq,
 
 	output logic[31:0] avl_address,
 	output logic       avl_read,
@@ -16,7 +18,8 @@ module bus_master
 	input  logic[31:0] avl_readdata,
 	output logic[31:0] avl_writedata,
 	input  logic       avl_waitrequest,
-	output logic[3:0]  avl_byteenable
+	output logic[3:0]  avl_byteenable,
+	input  logic       avl_irq
 );
 
 	enum {
@@ -24,6 +27,9 @@ module bus_master
 		WAIT
 	} state;
 
+	assign irq = avl_irq;
+	assign cpu_clk = clk;
+
 	assign data_rd = avl_readdata;
 	assign avl_byteenable = 4'b1111; //TODO
 
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 940e46a..41b614f 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -35,7 +35,7 @@ module conspiracion
 
 	logic[29:0] addr;
 	logic[31:0] data_rd, data_wr;
-	logic clk_core, ready, write, start;
+	logic cpu_clk, ready, write, start, irq;
 
 	arm810 core
 	(
@@ -53,12 +53,14 @@ module conspiracion
 
 	platform plat
 	(
+		.master_0_core_cpu_clk(cpu_clk),
 		.master_0_core_addr(addr),
 		.master_0_core_data_rd(data_rd),
 		.master_0_core_data_wr(data_wr),
 		.master_0_core_ready(ready),
 		.master_0_core_write(write),
 		.master_0_core_start(start),
+		.master_0_core_irq(irq),
 		.pll_0_outclk3_clk(),
 		.pio_0_external_connection_export(),
 		.*
diff --git a/tb/platform.sv b/tb/platform.sv
index 06c6ad1..41cc7bc 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -9,6 +9,8 @@ module platform (
 		output wire        master_0_core_ready   /*verilator public*/,//              .ready
 		input  wire        master_0_core_write   /*verilator public*/,//              .write
 		input  wire        master_0_core_start   /*verilator public*/,//              .start
+		output wire        master_0_core_irq,                //                          .irq
+		output wire        master_0_core_cpu_clk,            //                          .cpu_clk
 		output wire [12:0] memory_mem_a,                     //                    memory.mem_a
 		output wire [2:0]  memory_mem_ba,                    //                          .mem_ba
 		output wire        memory_mem_ck,                    //                          .mem_ck
@@ -42,6 +44,7 @@ module platform (
 	logic[31:0] avl_address /*verilator public*/;
 	logic       avl_read /*verilator public*/;
 	logic       avl_write /*verilator public*/;
+	logic       avl_irq /*verilator public_flat_rw @(negedge clk_clk)*/;
 	logic[31:0] avl_readdata /*verilator public_flat_rw @(negedge clk_clk)*/;
 	logic[31:0] avl_writedata /*verilator public*/;
 	logic       avl_waitrequest /*verilator public_flat_rw @(negedge clk_clk)*/;
@@ -57,6 +60,8 @@ module platform (
 		.ready(master_0_core_ready),
 		.data_rd(master_0_core_data_rd),
 		.data_wr(master_0_core_data_wr),
+		.cpu_clk(master_0_core_cpu_clk),
+		.irq(master_0_core_irq),
 		.*
 	);