Route cpu_rst_n signal through bus master

5 files changed, 51 insertions, 38 deletions

diff --git a/.gitignore b/.gitignore
index c204d2d..5c5f2d1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,3 +42,4 @@ hps_isw_handoff/
 *~
 *.vcd
 qmegawiz_errors_log.txt
+cr_ie_info.json
diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl
index f7f9760..2cb7f85 100644
--- a/conspiracion_bus_master_hw.tcl
+++ b/conspiracion_bus_master_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 20.1
-# Wed Nov 09 13:54:58 GMT 2022
+# Sat Nov 12 23:28:38 GMT 2022
 # DO NOT MODIFY
 
 
 # 
 # conspiracion_bus_master "Toplevel bus master" v1.0
-#  2022.11.09.13:54:58
+#  2022.11.12.23:28:37
 # 
 # 
 
@@ -101,13 +101,14 @@ add_interface_port core write write Input 1
 add_interface_port core start start Input 1
 add_interface_port core irq irq Output 1
 add_interface_port core cpu_clk cpu_clk Output 1
+add_interface_port core cpu_rst_n cpu_rst_n Output 1
 
 
 # 
 # connection point irq
 # 
 add_interface irq interrupt start
-set_interface_property irq associatedAddressablePoint avalon_master_1
+set_interface_property irq associatedAddressablePoint avalon_master_1_1
 set_interface_property irq associatedClock clock
 set_interface_property irq associatedReset reset_sink
 set_interface_property irq irqScheme INDIVIDUAL_REQUESTS
@@ -121,37 +122,37 @@ add_interface_port irq avl_irq irq Input 1
 
 
 # 
-# connection point avalon_master_1
-# 
-add_interface avalon_master_1 avalon start
-set_interface_property avalon_master_1 addressUnits SYMBOLS
-set_interface_property avalon_master_1 associatedClock clock
-set_interface_property avalon_master_1 associatedReset reset_sink
-set_interface_property avalon_master_1 bitsPerSymbol 8
-set_interface_property avalon_master_1 burstOnBurstBoundariesOnly false
-set_interface_property avalon_master_1 burstcountUnits WORDS
-set_interface_property avalon_master_1 doStreamReads false
-set_interface_property avalon_master_1 doStreamWrites false
-set_interface_property avalon_master_1 holdTime 0
-set_interface_property avalon_master_1 linewrapBursts false
-set_interface_property avalon_master_1 maximumPendingReadTransactions 0
-set_interface_property avalon_master_1 maximumPendingWriteTransactions 0
-set_interface_property avalon_master_1 readLatency 0
-set_interface_property avalon_master_1 readWaitTime 1
-set_interface_property avalon_master_1 setupTime 0
-set_interface_property avalon_master_1 timingUnits Cycles
-set_interface_property avalon_master_1 writeWaitTime 0
-set_interface_property avalon_master_1 ENABLED true
-set_interface_property avalon_master_1 EXPORT_OF ""
-set_interface_property avalon_master_1 PORT_NAME_MAP ""
-set_interface_property avalon_master_1 CMSIS_SVD_VARIABLES ""
-set_interface_property avalon_master_1 SVD_ADDRESS_GROUP ""
-
-add_interface_port avalon_master_1 avl_address address Output 32
-add_interface_port avalon_master_1 avl_read read Output 1
-add_interface_port avalon_master_1 avl_readdata readdata Input 32
-add_interface_port avalon_master_1 avl_write write Output 1
-add_interface_port avalon_master_1 avl_writedata writedata Output 32
-add_interface_port avalon_master_1 avl_byteenable byteenable Output 4
-add_interface_port avalon_master_1 avl_waitrequest waitrequest Input 1
+# connection point avalon_master_1_1
+# 
+add_interface avalon_master_1_1 avalon start
+set_interface_property avalon_master_1_1 addressUnits SYMBOLS
+set_interface_property avalon_master_1_1 associatedClock clock
+set_interface_property avalon_master_1_1 associatedReset reset_sink
+set_interface_property avalon_master_1_1 bitsPerSymbol 8
+set_interface_property avalon_master_1_1 burstOnBurstBoundariesOnly false
+set_interface_property avalon_master_1_1 burstcountUnits WORDS
+set_interface_property avalon_master_1_1 doStreamReads false
+set_interface_property avalon_master_1_1 doStreamWrites false
+set_interface_property avalon_master_1_1 holdTime 0
+set_interface_property avalon_master_1_1 linewrapBursts false
+set_interface_property avalon_master_1_1 maximumPendingReadTransactions 0
+set_interface_property avalon_master_1_1 maximumPendingWriteTransactions 0
+set_interface_property avalon_master_1_1 readLatency 0
+set_interface_property avalon_master_1_1 readWaitTime 1
+set_interface_property avalon_master_1_1 setupTime 0
+set_interface_property avalon_master_1_1 timingUnits Cycles
+set_interface_property avalon_master_1_1 writeWaitTime 0
+set_interface_property avalon_master_1_1 ENABLED true
+set_interface_property avalon_master_1_1 EXPORT_OF ""
+set_interface_property avalon_master_1_1 PORT_NAME_MAP ""
+set_interface_property avalon_master_1_1 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_master_1_1 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_master_1_1 avl_address address Output 32
+add_interface_port avalon_master_1_1 avl_read read Output 1
+add_interface_port avalon_master_1_1 avl_readdata readdata Input 32
+add_interface_port avalon_master_1_1 avl_write write Output 1
+add_interface_port avalon_master_1_1 avl_writedata writedata Output 32
+add_interface_port avalon_master_1_1 avl_byteenable byteenable Output 4
+add_interface_port avalon_master_1_1 avl_waitrequest waitrequest Input 1
 
diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
index 0a2f2ea..c61a208 100644
--- a/rtl/bus_master.sv
+++ b/rtl/bus_master.sv
@@ -10,6 +10,7 @@ module bus_master
 	output logic[31:0] data_rd,
 	input  logic[31:0] data_wr,
 	output logic       cpu_clk,
+	                   cpu_rst_n,
 	                   irq,
 
 	output logic[31:0] avl_address,
@@ -29,6 +30,7 @@ module bus_master
 
 	assign irq = avl_irq;
 	assign cpu_clk = clk;
+	assign cpu_rst_n = rst_n;
 
 	assign data_rd = avl_readdata;
 	assign avl_byteenable = 4'b1111; //TODO
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 8b29699..e6e1007 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -41,7 +41,11 @@ module conspiracion
 
 	logic[29:0] addr;
 	logic[31:0] data_rd, data_wr;
-	logic reset_reset_n, cpu_clk, ready, write, start, irq;
+	logic reset_reset_n, cpu_clk, cpu_rst_n, ready, write, start, irq;
+
+`ifndef VERILATOR`
+	assign pio_leds[0] = reset_reset_n;
+`endif
 
 `ifdef VERILATOR
 	assign reset_reset_n = rst_n;
@@ -57,7 +61,7 @@ module conspiracion
 	arm810 core
 	(
 		.clk(cpu_clk),
-		.rst_n(reset_reset_n),
+		.rst_n(cpu_rst_n),
 		.bus_addr(addr),
 		.bus_data_rd(data_rd),
 		.bus_data_wr(data_wr),
@@ -70,6 +74,7 @@ module conspiracion
 	platform plat
 	(
 		.master_0_core_cpu_clk(cpu_clk),
+		.master_0_core_cpu_rst_n(cpu_rst_n),
 		.master_0_core_addr(addr),
 		.master_0_core_data_rd(data_rd),
 		.master_0_core_data_wr(data_wr),
@@ -77,9 +82,11 @@ module conspiracion
 		.master_0_core_write(write),
 		.master_0_core_start(start),
 		.master_0_core_irq(irq),
+`ifdef VERILATOR
 		.pll_0_reset_reset(0), //TODO: reset controller, algún día
 		.pll_0_outclk3_clk(vram_wire_clk),
 		.pio_0_external_connection_export(pio_leds),
+`endif
 		.*
 	);
 
diff --git a/tb/platform.sv b/tb/platform.sv
index 21fb45b..cbf31b0 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -12,6 +12,7 @@ module platform
 	input  wire        master_0_core_start   /*verilator public*/,//              .start
 	output wire        master_0_core_irq,                //                          .irq
 	output wire        master_0_core_cpu_clk,            //                          .cpu_clk
+	output wire        master_0_core_cpu_rst_n,
 	output wire [12:0] memory_mem_a,                     //                    memory.mem_a
 	output wire [2:0]  memory_mem_ba,                    //                          .mem_ba
 	output wire        memory_mem_ck,                    //                          .mem_ck
@@ -71,6 +72,7 @@ module platform
 		.data_rd(master_0_core_data_rd),
 		.data_wr(master_0_core_data_wr),
 		.cpu_clk(master_0_core_cpu_clk),
+		.cpu_rst_n(master_0_core_cpu_rst_n),
 		.irq(master_0_core_irq),
 		.*
 	);