diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-10-26 01:33:00 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-26 01:33:00 -0600 |
| commit | 986863efed48dfba23907400beb7e5f025b75b50 (patch) | |
| tree | e0ff07cc351943639af64b4b6109e6e2c027f9e7 | |
| parent | d6c2fd1dcee4c4e413faebca2bd2cd2513132f7d (diff) | |
rtl/gfx: synchronize clock with SDRAM
| -rw-r--r-- | conspiracion.qsf | 1 | ||||
| -rw-r--r-- | ip/ip_fp_add.qip | 6 | ||||
| -rw-r--r-- | ip/ip_fp_add.v | 2 | ||||
| -rw-r--r-- | ip/ip_fp_add/ip_fp_add_0002.vhd | 814 | ||||
| -rw-r--r-- | ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl | 2 | ||||
| -rwxr-xr-x | ip/ip_fp_add_sim/cadence/ncsim_setup.sh | 4 | ||||
| -rw-r--r-- | ip/ip_fp_add_sim/ip_fp_add.vo | 2816 | ||||
| -rw-r--r-- | ip/ip_fp_add_sim/mentor/msim_setup.tcl | 2 | ||||
| -rwxr-xr-x | ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh | 4 | ||||
| -rwxr-xr-x | ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh | 4 | ||||
| -rw-r--r-- | ip/ip_fp_mul.qip | 10 | ||||
| -rw-r--r-- | ip/ip_fp_mul.v | 4 | ||||
| -rw-r--r-- | ip/ip_fp_mul/ip_fp_mul_0002.vhd | 351 | ||||
| -rw-r--r-- | ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl | 2 | ||||
| -rwxr-xr-x | ip/ip_fp_mul_sim/cadence/ncsim_setup.sh | 4 | ||||
| -rw-r--r-- | ip/ip_fp_mul_sim/ip_fp_mul.vo | 828 | ||||
| -rw-r--r-- | ip/ip_fp_mul_sim/mentor/msim_setup.tcl | 2 | ||||
| -rwxr-xr-x | ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh | 4 | ||||
| -rwxr-xr-x | ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh | 4 | ||||
| -rw-r--r-- | platform.qsys | 11 | ||||
| -rw-r--r-- | rtl/gfx/gfx_defs.sv | 6 |
21 files changed, 3057 insertions, 1824 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index 4b3f531..f24575e 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -320,6 +320,7 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_ set_global_assignment -name QIP_FILE ip/ip_fp_mul.qip set_global_assignment -name SIP_FILE ip/ip_fp_mul.sip + set_global_assignment -name QIP_FILE ip/ip_fp_add.qip set_global_assignment -name SIP_FILE ip/ip_fp_add.sip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/ip/ip_fp_add.qip b/ip/ip_fp_add.qip index 925ef31..1df7b9d 100644 --- a/ip/ip_fp_add.qip +++ b/ip/ip_fp_add.qip @@ -35,7 +35,7 @@ set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COM set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MTA=::TWFudGlzc2E=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MTA=::ZnBfbWFuX2Rlcml2ZWQ=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg=" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MjAw::VGFyZ2V0" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Mg==::VGFyZ2V0" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::ZnJlcXVlbmN5::R29hbA==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ==" @@ -53,7 +53,7 @@ set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COM set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::NA==::bGF0ZW5jeV9mZWVkYmFjaw==" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::MTA=::bGF0ZW5jeV9mZWVkYmFjaw==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50" @@ -69,7 +69,7 @@ set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COM set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MA==::TXVsdGlwbGllcw==" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MzI1::TFVUcw==" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::NDAx::TFVUcw==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" diff --git a/ip/ip_fp_add.v b/ip/ip_fp_add.v index 456dcf7..167d553 100644 --- a/ip/ip_fp_add.v +++ b/ip/ip_fp_add.v @@ -63,7 +63,7 @@ endmodule // Retrieval info: <generic name="fp_exp" value="5" /> // Retrieval info: <generic name="fp_man" value="10" /> // Retrieval info: <generic name="exponent_width" value="23" /> -// Retrieval info: <generic name="frequency_target" value="100" /> +// Retrieval info: <generic name="frequency_target" value="200" /> // Retrieval info: <generic name="latency_target" value="2" /> // Retrieval info: <generic name="performance_goal" value="frequency" /> // Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" /> diff --git a/ip/ip_fp_add/ip_fp_add_0002.vhd b/ip/ip_fp_add/ip_fp_add_0002.vhd index f44760e..3131e0f 100644 --- a/ip/ip_fp_add/ip_fp_add_0002.vhd +++ b/ip/ip_fp_add/ip_fp_add_0002.vhd @@ -16,7 +16,7 @@ -- --------------------------------------------------------------------------- -- VHDL created from ip_fp_add_0002 --- VHDL created on Sat Oct 21 14:33:41 2023 +-- VHDL created on Wed Oct 25 23:46:01 2023 library IEEE; @@ -72,16 +72,20 @@ architecture normal of ip_fp_add_0002 is signal exp_aSig_uid21_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0); signal frac_aSig_uid22_fpAddTest_in : STD_LOGIC_VECTOR (9 downto 0); signal frac_aSig_uid22_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); + signal excZ_aSig_uid16_uid23_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excZ_aSig_uid16_uid23_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal expXIsMax_uid24_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal expXIsMax_uid24_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid25_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid25_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsNotZero_uid26_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excI_aSig_uid27_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excI_aSig_uid27_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excN_aSig_uid28_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excN_aSig_uid28_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExpXIsMax_uid29_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal InvExpXIsZero_uid30_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excR_aSig_uid31_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excR_aSig_uid31_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal exp_bSig_uid35_fpAddTest_in : STD_LOGIC_VECTOR (14 downto 0); signal exp_bSig_uid35_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0); @@ -93,15 +97,16 @@ architecture normal of ip_fp_add_0002 is signal fracXIsZero_uid39_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid39_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsNotZero_uid40_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excI_bSig_uid41_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excI_bSig_uid41_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excN_bSig_uid42_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excN_bSig_uid42_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExpXIsMax_uid43_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal InvExpXIsZero_uid44_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excR_bSig_uid45_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excR_bSig_uid45_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal sigA_uid50_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); signal sigB_uid51_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); - signal effSub_uid52_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal effSub_uid52_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracBz_uid56_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); signal fracBz_uid56_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0); @@ -114,6 +119,7 @@ architecture normal of ip_fp_add_0002 is signal oFracAE_uid65_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); signal oFracBR_uid67_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); signal oFracBREX_uid68_fpAddTest_b : STD_LOGIC_VECTOR (13 downto 0); + signal oFracBREX_uid68_fpAddTest_qi : STD_LOGIC_VECTOR (13 downto 0); signal oFracBREX_uid68_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); signal oFracBREXC2_uid69_fpAddTest_a : STD_LOGIC_VECTOR (14 downto 0); signal oFracBREXC2_uid69_fpAddTest_b : STD_LOGIC_VECTOR (14 downto 0); @@ -128,6 +134,7 @@ architecture normal of ip_fp_add_0002 is signal fracAddResultNoSignExt_uid73_fpAddTest_in : STD_LOGIC_VECTOR (13 downto 0); signal fracAddResultNoSignExt_uid73_fpAddTest_b : STD_LOGIC_VECTOR (13 downto 0); signal cAmA_uid76_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); + signal aMinusA_uid77_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal aMinusA_uid77_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal expInc_uid78_fpAddTest_a : STD_LOGIC_VECTOR (5 downto 0); signal expInc_uid78_fpAddTest_b : STD_LOGIC_VECTOR (5 downto 0); @@ -156,6 +163,7 @@ architecture normal of ip_fp_add_0002 is signal excRInf_uid93_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excRNaN2_uid94_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excAIBISub_uid95_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excRNaN_uid96_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excRNaN_uid96_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal concExc_uid97_fpAddTest_q : STD_LOGIC_VECTOR (2 downto 0); signal excREnc_uid98_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0); @@ -187,11 +195,11 @@ architecture normal of ip_fp_add_0002 is signal vStagei_uid127_lzCountVal_uid74_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); signal vStagei_uid127_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0); signal zs_uid128_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); - signal vCount_uid130_lzCountVal_uid74_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal vCount_uid130_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal vStagei_uid133_lzCountVal_uid74_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); signal vStagei_uid133_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); signal zs_uid134_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0); + signal vCount_uid136_lzCountVal_uid74_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal vCount_uid136_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal vStagei_uid139_lzCountVal_uid74_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); signal vStagei_uid139_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0); @@ -264,27 +272,36 @@ architecture normal of ip_fp_add_0002 is signal rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0); signal leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0); signal leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0); - signal redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q : STD_LOGIC_VECTOR (3 downto 0); - signal redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q : STD_LOGIC_VECTOR (3 downto 0); - signal redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1_q : STD_LOGIC_VECTOR (5 downto 0); - signal redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist4_regInputs_uid88_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist5_expFracR_uid81_fpAddTest_q_1_q : STD_LOGIC_VECTOR (17 downto 0); - signal redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q : STD_LOGIC_VECTOR (13 downto 0); - signal redist7_effSub_uid52_fpAddTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist8_sigB_uid51_fpAddTest_b_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist9_sigA_uid50_fpAddTest_b_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist10_InvExpXIsZero_uid44_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist11_excI_bSig_uid41_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist12_fracXIsZero_uid39_fpAddTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist13_expXIsMax_uid38_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist16_exp_bSig_uid35_fpAddTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); - signal redist17_excI_aSig_uid27_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist18_frac_aSig_uid22_fpAddTest_b_2_q : STD_LOGIC_VECTOR (9 downto 0); - signal redist19_exp_aSig_uid21_fpAddTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); - signal redist20_exp_aSig_uid21_fpAddTest_b_3_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist0_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q : STD_LOGIC_VECTOR (1 downto 0); + signal redist1_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q : STD_LOGIC_VECTOR (1 downto 0); + signal redist2_vCount_uid130_lzCountVal_uid74_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist3_vStage_uid124_lzCountVal_uid74_fpAddTest_b_2_q : STD_LOGIC_VECTOR (5 downto 0); + signal redist4_vCount_uid122_lzCountVal_uid74_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist5_excRInfVInC_uid92_fpAddTest_q_1_q : STD_LOGIC_VECTOR (5 downto 0); + signal redist6_expRPreExc_uid87_fpAddTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist7_fracRPreExc_uid86_fpAddTest_b_1_q : STD_LOGIC_VECTOR (9 downto 0); + signal redist8_fracPostNormRndRange_uid80_fpAddTest_b_1_q : STD_LOGIC_VECTOR (10 downto 0); + signal redist9_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q : STD_LOGIC_VECTOR (13 downto 0); + signal redist10_fracAddResultNoSignExt_uid73_fpAddTest_b_3_q : STD_LOGIC_VECTOR (13 downto 0); + signal redist11_oFracBREXC2_uid70_fpAddTest_b_1_q : STD_LOGIC_VECTOR (13 downto 0); + signal redist12_effSub_uid52_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist13_effSub_uid52_fpAddTest_q_7_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist14_sigB_uid51_fpAddTest_b_7_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist15_sigA_uid50_fpAddTest_b_7_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist16_InvExpXIsZero_uid44_fpAddTest_q_6_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist17_fracXIsZero_uid39_fpAddTest_q_6_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist18_expXIsMax_uid38_fpAddTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist19_excZ_bSig_uid17_uid37_fpAddTest_q_7_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist20_exp_bSig_uid35_fpAddTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist21_fracXIsZero_uid25_fpAddTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist22_excZ_aSig_uid16_uid23_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist23_frac_aSig_uid22_fpAddTest_b_3_q : STD_LOGIC_VECTOR (9 downto 0); + signal redist24_exp_aSig_uid21_fpAddTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist25_exp_aSig_uid21_fpAddTest_b_5_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist26_sigY_uid11_fpAddTest_b_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist27_expY_uid10_fpAddTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist28_fracY_uid9_fpAddTest_b_1_q : STD_LOGIC_VECTOR (9 downto 0); + signal redist29_xIn_a_1_q : STD_LOGIC_VECTOR (15 downto 0); begin @@ -298,14 +315,34 @@ begin -- sigY_uid11_fpAddTest(BITSELECT,10)@0 sigY_uid11_fpAddTest_b <= STD_LOGIC_VECTOR(b(15 downto 15)); + -- redist26_sigY_uid11_fpAddTest_b_1(DELAY,228) + redist26_sigY_uid11_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => sigY_uid11_fpAddTest_b, xout => redist26_sigY_uid11_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + -- expY_uid10_fpAddTest(BITSELECT,9)@0 expY_uid10_fpAddTest_b <= b(14 downto 10); + -- redist27_expY_uid10_fpAddTest_b_1(DELAY,229) + redist27_expY_uid10_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => expY_uid10_fpAddTest_b, xout => redist27_expY_uid10_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + -- fracY_uid9_fpAddTest(BITSELECT,8)@0 fracY_uid9_fpAddTest_b <= b(9 downto 0); - -- ypn_uid12_fpAddTest(BITJOIN,11)@0 - ypn_uid12_fpAddTest_q <= sigY_uid11_fpAddTest_b & expY_uid10_fpAddTest_b & fracY_uid9_fpAddTest_b; + -- redist28_fracY_uid9_fpAddTest_b_1(DELAY,230) + redist28_fracY_uid9_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 10, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracY_uid9_fpAddTest_b, xout => redist28_fracY_uid9_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- ypn_uid12_fpAddTest(BITJOIN,11)@1 + ypn_uid12_fpAddTest_q <= redist26_sigY_uid11_fpAddTest_b_1_q & redist27_expY_uid10_fpAddTest_b_1_q & redist28_fracY_uid9_fpAddTest_b_1_q; + + -- redist29_xIn_a_1(DELAY,231) + redist29_xIn_a_1 : dspba_delay + GENERIC MAP ( width => 16, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => a, xout => redist29_xIn_a_1_q, ena => en(0), clk => clk, aclr => areset ); -- GND(CONSTANT,0) GND_q <= "0"; @@ -316,177 +353,197 @@ begin -- expFracX_uid6_fpAddTest(BITSELECT,5)@0 expFracX_uid6_fpAddTest_b <= a(14 downto 0); - -- xGTEy_uid8_fpAddTest(COMPARE,7)@0 + -- xGTEy_uid8_fpAddTest(COMPARE,7)@0 + 1 xGTEy_uid8_fpAddTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid6_fpAddTest_b); xGTEy_uid8_fpAddTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid7_fpAddTest_b); - xGTEy_uid8_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xGTEy_uid8_fpAddTest_a) - UNSIGNED(xGTEy_uid8_fpAddTest_b)); + xGTEy_uid8_fpAddTest_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + xGTEy_uid8_fpAddTest_o <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + xGTEy_uid8_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xGTEy_uid8_fpAddTest_a) - UNSIGNED(xGTEy_uid8_fpAddTest_b)); + END IF; + END IF; + END PROCESS; xGTEy_uid8_fpAddTest_n(0) <= not (xGTEy_uid8_fpAddTest_o(16)); - -- bSig_uid17_fpAddTest(MUX,16)@0 + -- bSig_uid17_fpAddTest(MUX,16)@1 + 1 bSig_uid17_fpAddTest_s <= xGTEy_uid8_fpAddTest_n; - bSig_uid17_fpAddTest_combproc: PROCESS (bSig_uid17_fpAddTest_s, en, a, ypn_uid12_fpAddTest_q) + bSig_uid17_fpAddTest_clkproc: PROCESS (clk, areset) BEGIN - CASE (bSig_uid17_fpAddTest_s) IS - WHEN "0" => bSig_uid17_fpAddTest_q <= a; - WHEN "1" => bSig_uid17_fpAddTest_q <= ypn_uid12_fpAddTest_q; - WHEN OTHERS => bSig_uid17_fpAddTest_q <= (others => '0'); - END CASE; + IF (areset = '1') THEN + bSig_uid17_fpAddTest_q <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + CASE (bSig_uid17_fpAddTest_s) IS + WHEN "0" => bSig_uid17_fpAddTest_q <= redist29_xIn_a_1_q; + WHEN "1" => bSig_uid17_fpAddTest_q <= ypn_uid12_fpAddTest_q; + WHEN OTHERS => bSig_uid17_fpAddTest_q <= (others => '0'); + END CASE; + END IF; + END IF; END PROCESS; - -- sigB_uid51_fpAddTest(BITSELECT,50)@0 + -- sigB_uid51_fpAddTest(BITSELECT,50)@2 sigB_uid51_fpAddTest_b <= STD_LOGIC_VECTOR(bSig_uid17_fpAddTest_q(15 downto 15)); - -- aSig_uid16_fpAddTest(MUX,15)@0 + -- aSig_uid16_fpAddTest(MUX,15)@1 + 1 aSig_uid16_fpAddTest_s <= xGTEy_uid8_fpAddTest_n; - aSig_uid16_fpAddTest_combproc: PROCESS (aSig_uid16_fpAddTest_s, en, ypn_uid12_fpAddTest_q, a) + aSig_uid16_fpAddTest_clkproc: PROCESS (clk, areset) BEGIN - CASE (aSig_uid16_fpAddTest_s) IS - WHEN "0" => aSig_uid16_fpAddTest_q <= ypn_uid12_fpAddTest_q; - WHEN "1" => aSig_uid16_fpAddTest_q <= a; - WHEN OTHERS => aSig_uid16_fpAddTest_q <= (others => '0'); - END CASE; + IF (areset = '1') THEN + aSig_uid16_fpAddTest_q <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + CASE (aSig_uid16_fpAddTest_s) IS + WHEN "0" => aSig_uid16_fpAddTest_q <= ypn_uid12_fpAddTest_q; + WHEN "1" => aSig_uid16_fpAddTest_q <= redist29_xIn_a_1_q; + WHEN OTHERS => aSig_uid16_fpAddTest_q <= (others => '0'); + END CASE; + END IF; + END IF; END PROCESS; - -- sigA_uid50_fpAddTest(BITSELECT,49)@0 + -- sigA_uid50_fpAddTest(BITSELECT,49)@2 sigA_uid50_fpAddTest_b <= STD_LOGIC_VECTOR(aSig_uid16_fpAddTest_q(15 downto 15)); - -- effSub_uid52_fpAddTest(LOGICAL,51)@0 + 1 - effSub_uid52_fpAddTest_qi <= sigA_uid50_fpAddTest_b xor sigB_uid51_fpAddTest_b; - effSub_uid52_fpAddTest_delay : dspba_delay + -- effSub_uid52_fpAddTest(LOGICAL,51)@2 + effSub_uid52_fpAddTest_q <= sigA_uid50_fpAddTest_b xor sigB_uid51_fpAddTest_b; + + -- redist12_effSub_uid52_fpAddTest_q_1(DELAY,214) + redist12_effSub_uid52_fpAddTest_q_1 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => effSub_uid52_fpAddTest_qi, xout => effSub_uid52_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); + PORT MAP ( xin => effSub_uid52_fpAddTest_q, xout => redist12_effSub_uid52_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); -- cstAllZWE_uid20_fpAddTest(CONSTANT,19) cstAllZWE_uid20_fpAddTest_q <= "00000"; - -- exp_bSig_uid35_fpAddTest(BITSELECT,34)@0 + -- exp_bSig_uid35_fpAddTest(BITSELECT,34)@2 exp_bSig_uid35_fpAddTest_in <= bSig_uid17_fpAddTest_q(14 downto 0); exp_bSig_uid35_fpAddTest_b <= exp_bSig_uid35_fpAddTest_in(14 downto 10); - -- excZ_bSig_uid17_uid37_fpAddTest(LOGICAL,36)@0 + -- excZ_bSig_uid17_uid37_fpAddTest(LOGICAL,36)@2 excZ_bSig_uid17_uid37_fpAddTest_q <= "1" WHEN exp_bSig_uid35_fpAddTest_b = cstAllZWE_uid20_fpAddTest_q ELSE "0"; - -- redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1(DELAY,216) - redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_bSig_uid17_uid37_fpAddTest_q, xout => redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - - -- InvExpXIsZero_uid44_fpAddTest(LOGICAL,43)@1 - InvExpXIsZero_uid44_fpAddTest_q <= not (redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1_q); + -- InvExpXIsZero_uid44_fpAddTest(LOGICAL,43)@2 + InvExpXIsZero_uid44_fpAddTest_q <= not (excZ_bSig_uid17_uid37_fpAddTest_q); -- cstZeroWF_uid19_fpAddTest(CONSTANT,18) cstZeroWF_uid19_fpAddTest_q <= "0000000000"; - -- frac_bSig_uid36_fpAddTest(BITSELECT,35)@0 + -- frac_bSig_uid36_fpAddTest(BITSELECT,35)@2 frac_bSig_uid36_fpAddTest_in <= bSig_uid17_fpAddTest_q(9 downto 0); frac_bSig_uid36_fpAddTest_b <= frac_bSig_uid36_fpAddTest_in(9 downto 0); - -- fracBz_uid56_fpAddTest(MUX,55)@0 + 1 + -- fracBz_uid56_fpAddTest(MUX,55)@2 fracBz_uid56_fpAddTest_s <= excZ_bSig_uid17_uid37_fpAddTest_q; - fracBz_uid56_fpAddTest_clkproc: PROCESS (clk, areset) + fracBz_uid56_fpAddTest_combproc: PROCESS (fracBz_uid56_fpAddTest_s, en, frac_bSig_uid36_fpAddTest_b, cstZeroWF_uid19_fpAddTest_q) BEGIN - IF (areset = '1') THEN - fracBz_uid56_fpAddTest_q <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - IF (en = "1") THEN - CASE (fracBz_uid56_fpAddTest_s) IS - WHEN "0" => fracBz_uid56_fpAddTest_q <= frac_bSig_uid36_fpAddTest_b; - WHEN "1" => fracBz_uid56_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q; - WHEN OTHERS => fracBz_uid56_fpAddTest_q <= (others => '0'); - END CASE; - END IF; - END IF; + CASE (fracBz_uid56_fpAddTest_s) IS + WHEN "0" => fracBz_uid56_fpAddTest_q <= frac_bSig_uid36_fpAddTest_b; + WHEN "1" => fracBz_uid56_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q; + WHEN OTHERS => fracBz_uid56_fpAddTest_q <= (others => '0'); + END CASE; END PROCESS; - -- oFracB_uid59_fpAddTest(BITJOIN,58)@1 + -- oFracB_uid59_fpAddTest(BITJOIN,58)@2 oFracB_uid59_fpAddTest_q <= InvExpXIsZero_uid44_fpAddTest_q & fracBz_uid56_fpAddTest_q; - -- oFracBR_uid67_fpAddTest(BITJOIN,66)@1 + -- oFracBR_uid67_fpAddTest(BITJOIN,66)@2 oFracBR_uid67_fpAddTest_q <= GND_q & oFracB_uid59_fpAddTest_q & GND_q & GND_q; - -- oFracBREX_uid68_fpAddTest(LOGICAL,67)@1 + -- oFracBREX_uid68_fpAddTest(LOGICAL,67)@2 + 1 oFracBREX_uid68_fpAddTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 1 => effSub_uid52_fpAddTest_q(0)) & effSub_uid52_fpAddTest_q)); - oFracBREX_uid68_fpAddTest_q <= oFracBR_uid67_fpAddTest_q xor oFracBREX_uid68_fpAddTest_b; + oFracBREX_uid68_fpAddTest_qi <= oFracBR_uid67_fpAddTest_q xor oFracBREX_uid68_fpAddTest_b; + oFracBREX_uid68_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 14, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => oFracBREX_uid68_fpAddTest_qi, xout => oFracBREX_uid68_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- oFracBREXC2_uid69_fpAddTest(ADD,68)@1 + -- oFracBREXC2_uid69_fpAddTest(ADD,68)@3 oFracBREXC2_uid69_fpAddTest_a <= STD_LOGIC_VECTOR("0" & oFracBREX_uid68_fpAddTest_q); - oFracBREXC2_uid69_fpAddTest_b <= STD_LOGIC_VECTOR("00000000000000" & effSub_uid52_fpAddTest_q); + oFracBREXC2_uid69_fpAddTest_b <= STD_LOGIC_VECTOR("00000000000000" & redist12_effSub_uid52_fpAddTest_q_1_q); oFracBREXC2_uid69_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oFracBREXC2_uid69_fpAddTest_a) + UNSIGNED(oFracBREXC2_uid69_fpAddTest_b)); oFracBREXC2_uid69_fpAddTest_q <= oFracBREXC2_uid69_fpAddTest_o(14 downto 0); - -- oFracBREXC2_uid70_fpAddTest(BITSELECT,69)@1 + -- oFracBREXC2_uid70_fpAddTest(BITSELECT,69)@3 oFracBREXC2_uid70_fpAddTest_in <= STD_LOGIC_VECTOR(oFracBREXC2_uid69_fpAddTest_q(13 downto 0)); oFracBREXC2_uid70_fpAddTest_b <= STD_LOGIC_VECTOR(oFracBREXC2_uid70_fpAddTest_in(13 downto 0)); - -- xMSB_uid145_alignmentShifter_uid71_fpAddTest(BITSELECT,144)@1 - xMSB_uid145_alignmentShifter_uid71_fpAddTest_b <= STD_LOGIC_VECTOR(oFracBREXC2_uid70_fpAddTest_b(13 downto 13)); + -- redist11_oFracBREXC2_uid70_fpAddTest_b_1(DELAY,213) + redist11_oFracBREXC2_uid70_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 14, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => oFracBREXC2_uid70_fpAddTest_b, xout => redist11_oFracBREXC2_uid70_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- xMSB_uid145_alignmentShifter_uid71_fpAddTest(BITSELECT,144)@4 + xMSB_uid145_alignmentShifter_uid71_fpAddTest_b <= STD_LOGIC_VECTOR(redist11_oFracBREXC2_uid70_fpAddTest_b_1_q(13 downto 13)); - -- shiftOutConstant_to14_uid170(BITSELECT,169)@1 + -- shiftOutConstant_to14_uid170(BITSELECT,169)@4 shiftOutConstant_to14_uid170_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); shiftOutConstant_to14_uid170_b <= STD_LOGIC_VECTOR(shiftOutConstant_to14_uid170_in(13 downto 0)); - -- seMsb_to3_uid165(BITSELECT,164)@1 + -- seMsb_to3_uid165(BITSELECT,164)@4 seMsb_to3_uid165_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((2 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); seMsb_to3_uid165_b <= STD_LOGIC_VECTOR(seMsb_to3_uid165_in(2 downto 0)); - -- rightShiftStage1Idx3Rng3_uid166_alignmentShifter_uid71_fpAddTest(BITSELECT,165)@1 + -- rightShiftStage1Idx3Rng3_uid166_alignmentShifter_uid71_fpAddTest(BITSELECT,165)@4 rightShiftStage1Idx3Rng3_uid166_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q(13 downto 3); - -- rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest(BITJOIN,166)@1 + -- rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest(BITJOIN,166)@4 rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest_q <= seMsb_to3_uid165_b & rightShiftStage1Idx3Rng3_uid166_alignmentShifter_uid71_fpAddTest_b; - -- seMsb_to2_uid162(BITSELECT,161)@1 + -- seMsb_to2_uid162(BITSELECT,161)@4 seMsb_to2_uid162_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((1 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); seMsb_to2_uid162_b <= STD_LOGIC_VECTOR(seMsb_to2_uid162_in(1 downto 0)); - -- rightShiftStage1Idx2Rng2_uid163_alignmentShifter_uid71_fpAddTest(BITSELECT,162)@1 + -- rightShiftStage1Idx2Rng2_uid163_alignmentShifter_uid71_fpAddTest(BITSELECT,162)@4 rightShiftStage1Idx2Rng2_uid163_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q(13 downto 2); - -- rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest(BITJOIN,163)@1 + -- rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest(BITJOIN,163)@4 rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest_q <= seMsb_to2_uid162_b & rightShiftStage1Idx2Rng2_uid163_alignmentShifter_uid71_fpAddTest_b; - -- rightShiftStage1Idx1Rng1_uid160_alignmentShifter_uid71_fpAddTest(BITSELECT,159)@1 + -- rightShiftStage1Idx1Rng1_uid160_alignmentShifter_uid71_fpAddTest(BITSELECT,159)@4 rightShiftStage1Idx1Rng1_uid160_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q(13 downto 1); - -- rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest(BITJOIN,160)@1 + -- rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest(BITJOIN,160)@4 rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest_q <= xMSB_uid145_alignmentShifter_uid71_fpAddTest_b & rightShiftStage1Idx1Rng1_uid160_alignmentShifter_uid71_fpAddTest_b; - -- seMsb_to12_uid155(BITSELECT,154)@1 + -- seMsb_to12_uid155(BITSELECT,154)@4 seMsb_to12_uid155_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); seMsb_to12_uid155_b <= STD_LOGIC_VECTOR(seMsb_to12_uid155_in(11 downto 0)); - -- rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest(BITSELECT,155)@1 - rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest_b <= oFracBREXC2_uid70_fpAddTest_b(13 downto 12); + -- rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest(BITSELECT,155)@4 + rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest_b <= redist11_oFracBREXC2_uid70_fpAddTest_b_1_q(13 downto 12); - -- rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest(BITJOIN,156)@1 + -- rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest(BITJOIN,156)@4 rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest_q <= seMsb_to12_uid155_b & rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest_b; - -- seMsb_to8_uid152(BITSELECT,151)@1 + -- seMsb_to8_uid152(BITSELECT,151)@4 seMsb_to8_uid152_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((7 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); seMsb_to8_uid152_b <= STD_LOGIC_VECTOR(seMsb_to8_uid152_in(7 downto 0)); - -- rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest(BITSELECT,152)@1 - rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest_b <= oFracBREXC2_uid70_fpAddTest_b(13 downto 8); + -- rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest(BITSELECT,152)@4 + rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest_b <= redist11_oFracBREXC2_uid70_fpAddTest_b_1_q(13 downto 8); - -- rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest(BITJOIN,153)@1 + -- rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest(BITJOIN,153)@4 rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest_q <= seMsb_to8_uid152_b & rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest_b; - -- seMsb_to4_uid149(BITSELECT,148)@1 + -- seMsb_to4_uid149(BITSELECT,148)@4 seMsb_to4_uid149_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((3 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); seMsb_to4_uid149_b <= STD_LOGIC_VECTOR(seMsb_to4_uid149_in(3 downto 0)); - -- rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest(BITSELECT,149)@1 - rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest_b <= oFracBREXC2_uid70_fpAddTest_b(13 downto 4); + -- rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest(BITSELECT,149)@4 + rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest_b <= redist11_oFracBREXC2_uid70_fpAddTest_b_1_q(13 downto 4); - -- rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest(BITJOIN,150)@1 + -- rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest(BITJOIN,150)@4 rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest_q <= seMsb_to4_uid149_b & rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest_b; - -- rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest(MUX,158)@1 + -- rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest(MUX,158)@4 rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_s <= rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_b; - rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_combproc: PROCESS (rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_s, en, oFracBREXC2_uid70_fpAddTest_b, rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest_q, rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest_q, rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest_q) + rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_combproc: PROCESS (rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_s, en, redist11_oFracBREXC2_uid70_fpAddTest_b_1_q, rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest_q, rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest_q, rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest_q) BEGIN CASE (rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_s) IS - WHEN "00" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= oFracBREXC2_uid70_fpAddTest_b; + WHEN "00" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= redist11_oFracBREXC2_uid70_fpAddTest_b_1_q; WHEN "01" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest_q; WHEN "10" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest_q; WHEN "11" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest_q; @@ -494,32 +551,41 @@ begin END CASE; END PROCESS; - -- redist16_exp_bSig_uid35_fpAddTest_b_1(DELAY,218) - redist16_exp_bSig_uid35_fpAddTest_b_1 : dspba_delay + -- redist20_exp_bSig_uid35_fpAddTest_b_1(DELAY,222) + redist20_exp_bSig_uid35_fpAddTest_b_1 : dspba_delay GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => exp_bSig_uid35_fpAddTest_b, xout => redist16_exp_bSig_uid35_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + PORT MAP ( xin => exp_bSig_uid35_fpAddTest_b, xout => redist20_exp_bSig_uid35_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- exp_aSig_uid21_fpAddTest(BITSELECT,20)@0 + -- exp_aSig_uid21_fpAddTest(BITSELECT,20)@2 exp_aSig_uid21_fpAddTest_in <= aSig_uid16_fpAddTest_q(14 downto 0); exp_aSig_uid21_fpAddTest_b <= exp_aSig_uid21_fpAddTest_in(14 downto 10); - -- redist19_exp_aSig_uid21_fpAddTest_b_1(DELAY,221) - redist19_exp_aSig_uid21_fpAddTest_b_1 : dspba_delay + -- redist24_exp_aSig_uid21_fpAddTest_b_1(DELAY,226) + redist24_exp_aSig_uid21_fpAddTest_b_1 : dspba_delay GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => exp_aSig_uid21_fpAddTest_b, xout => redist19_exp_aSig_uid21_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + PORT MAP ( xin => exp_aSig_uid21_fpAddTest_b, xout => redist24_exp_aSig_uid21_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- expAmExpB_uid60_fpAddTest(SUB,59)@1 - expAmExpB_uid60_fpAddTest_a <= STD_LOGIC_VECTOR("0" & redist19_exp_aSig_uid21_fpAddTest_b_1_q); - expAmExpB_uid60_fpAddTest_b <= STD_LOGIC_VECTOR("0" & redist16_exp_bSig_uid35_fpAddTest_b_1_q); - expAmExpB_uid60_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expAmExpB_uid60_fpAddTest_a) - UNSIGNED(expAmExpB_uid60_fpAddTest_b)); + -- expAmExpB_uid60_fpAddTest(SUB,59)@3 + 1 + expAmExpB_uid60_fpAddTest_a <= STD_LOGIC_VECTOR("0" & redist24_exp_aSig_uid21_fpAddTest_b_1_q); + expAmExpB_uid60_fpAddTest_b <= STD_LOGIC_VECTOR("0" & redist20_exp_bSig_uid35_fpAddTest_b_1_q); + expAmExpB_uid60_fpAddTest_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + expAmExpB_uid60_fpAddTest_o <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + expAmExpB_uid60_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expAmExpB_uid60_fpAddTest_a) - UNSIGNED(expAmExpB_uid60_fpAddTest_b)); + END IF; + END IF; + END PROCESS; expAmExpB_uid60_fpAddTest_q <= expAmExpB_uid60_fpAddTest_o(5 downto 0); - -- rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select(BITSELECT,198)@1 + -- rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select(BITSELECT,198)@4 rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_in <= expAmExpB_uid60_fpAddTest_q(3 downto 0); rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_b <= rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_in(3 downto 2); rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_c <= rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_in(1 downto 0); - -- rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest(MUX,168)@1 + -- rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest(MUX,168)@4 rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_s <= rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_c; rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_combproc: PROCESS (rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_s, en, rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest_q) BEGIN @@ -532,13 +598,13 @@ begin END CASE; END PROCESS; - -- shiftedOut_uid148_alignmentShifter_uid71_fpAddTest(COMPARE,147)@1 + -- shiftedOut_uid148_alignmentShifter_uid71_fpAddTest(COMPARE,147)@4 shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_a <= STD_LOGIC_VECTOR("00" & expAmExpB_uid60_fpAddTest_q); shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_b <= STD_LOGIC_VECTOR("0000" & cAmA_uid76_fpAddTest_q); shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_a) - UNSIGNED(shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_b)); shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_n(0) <= not (shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_o(7)); - -- r_uid172_alignmentShifter_uid71_fpAddTest(MUX,171)@1 + 1 + -- r_uid172_alignmentShifter_uid71_fpAddTest(MUX,171)@4 + 1 r_uid172_alignmentShifter_uid71_fpAddTest_s <= shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_n; r_uid172_alignmentShifter_uid71_fpAddTest_clkproc: PROCESS (clk, areset) BEGIN @@ -558,363 +624,421 @@ begin -- VCC(CONSTANT,1) VCC_q <= "1"; - -- frac_aSig_uid22_fpAddTest(BITSELECT,21)@0 + -- frac_aSig_uid22_fpAddTest(BITSELECT,21)@2 frac_aSig_uid22_fpAddTest_in <= aSig_uid16_fpAddTest_q(9 downto 0); frac_aSig_uid22_fpAddTest_b <= frac_aSig_uid22_fpAddTest_in(9 downto 0); - -- redist18_frac_aSig_uid22_fpAddTest_b_2(DELAY,220) - redist18_frac_aSig_uid22_fpAddTest_b_2 : dspba_delay - GENERIC MAP ( width => 10, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => frac_aSig_uid22_fpAddTest_b, xout => redist18_frac_aSig_uid22_fpAddTest_b_2_q, ena => en(0), clk => clk, aclr => areset ); + -- redist23_frac_aSig_uid22_fpAddTest_b_3(DELAY,225) + redist23_frac_aSig_uid22_fpAddTest_b_3 : dspba_delay + GENERIC MAP ( width => 10, depth => 3, reset_kind => "ASYNC" ) + PORT MAP ( xin => frac_aSig_uid22_fpAddTest_b, xout => redist23_frac_aSig_uid22_fpAddTest_b_3_q, ena => en(0), clk => clk, aclr => areset ); - -- oFracA_uid64_fpAddTest(BITJOIN,63)@2 - oFracA_uid64_fpAddTest_q <= VCC_q & redist18_frac_aSig_uid22_fpAddTest_b_2_q; + -- oFracA_uid64_fpAddTest(BITJOIN,63)@5 + oFracA_uid64_fpAddTest_q <= VCC_q & redist23_frac_aSig_uid22_fpAddTest_b_3_q; - -- oFracAE_uid65_fpAddTest(BITJOIN,64)@2 + -- oFracAE_uid65_fpAddTest(BITJOIN,64)@5 oFracAE_uid65_fpAddTest_q <= GND_q & oFracA_uid64_fpAddTest_q & GND_q & GND_q; - -- fracAddResult_uid72_fpAddTest(ADD,71)@2 + -- fracAddResult_uid72_fpAddTest(ADD,71)@5 fracAddResult_uid72_fpAddTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((14 downto 14 => oFracAE_uid65_fpAddTest_q(13)) & oFracAE_uid65_fpAddTest_q)); fracAddResult_uid72_fpAddTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((14 downto 14 => r_uid172_alignmentShifter_uid71_fpAddTest_q(13)) & r_uid172_alignmentShifter_uid71_fpAddTest_q)); fracAddResult_uid72_fpAddTest_o <= STD_LOGIC_VECTOR(SIGNED(fracAddResult_uid72_fpAddTest_a) + SIGNED(fracAddResult_uid72_fpAddTest_b)); fracAddResult_uid72_fpAddTest_q <= fracAddResult_uid72_fpAddTest_o(14 downto 0); - -- fracAddResultNoSignExt_uid73_fpAddTest(BITSELECT,72)@2 + -- fracAddResultNoSignExt_uid73_fpAddTest(BITSELECT,72)@5 fracAddResultNoSignExt_uid73_fpAddTest_in <= fracAddResult_uid72_fpAddTest_q(13 downto 0); fracAddResultNoSignExt_uid73_fpAddTest_b <= fracAddResultNoSignExt_uid73_fpAddTest_in(13 downto 0); - -- rVStage_uid121_lzCountVal_uid74_fpAddTest(BITSELECT,120)@2 - rVStage_uid121_lzCountVal_uid74_fpAddTest_b <= fracAddResultNoSignExt_uid73_fpAddTest_b(13 downto 6); + -- redist9_fracAddResultNoSignExt_uid73_fpAddTest_b_1(DELAY,211) + redist9_fracAddResultNoSignExt_uid73_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 14, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracAddResultNoSignExt_uid73_fpAddTest_b, xout => redist9_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- rVStage_uid121_lzCountVal_uid74_fpAddTest(BITSELECT,120)@6 + rVStage_uid121_lzCountVal_uid74_fpAddTest_b <= redist9_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q(13 downto 6); - -- vCount_uid122_lzCountVal_uid74_fpAddTest(LOGICAL,121)@2 + -- vCount_uid122_lzCountVal_uid74_fpAddTest(LOGICAL,121)@6 vCount_uid122_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid121_lzCountVal_uid74_fpAddTest_b = zs_uid120_lzCountVal_uid74_fpAddTest_q ELSE "0"; - -- redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1(DELAY,205) - redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => vCount_uid122_lzCountVal_uid74_fpAddTest_q, xout => redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); + -- redist4_vCount_uid122_lzCountVal_uid74_fpAddTest_q_2(DELAY,206) + redist4_vCount_uid122_lzCountVal_uid74_fpAddTest_q_2 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => vCount_uid122_lzCountVal_uid74_fpAddTest_q, xout => redist4_vCount_uid122_lzCountVal_uid74_fpAddTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); -- zs_uid128_lzCountVal_uid74_fpAddTest(CONSTANT,127) zs_uid128_lzCountVal_uid74_fpAddTest_q <= "0000"; - -- vStage_uid124_lzCountVal_uid74_fpAddTest(BITSELECT,123)@2 - vStage_uid124_lzCountVal_uid74_fpAddTest_in <= fracAddResultNoSignExt_uid73_fpAddTest_b(5 downto 0); + -- vStage_uid124_lzCountVal_uid74_fpAddTest(BITSELECT,123)@6 + vStage_uid124_lzCountVal_uid74_fpAddTest_in <= redist9_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q(5 downto 0); vStage_uid124_lzCountVal_uid74_fpAddTest_b <= vStage_uid124_lzCountVal_uid74_fpAddTest_in(5 downto 0); -- mO_uid123_lzCountVal_uid74_fpAddTest(CONSTANT,122) mO_uid123_lzCountVal_uid74_fpAddTest_q <= "11"; - -- cStage_uid125_lzCountVal_uid74_fpAddTest(BITJOIN,124)@2 + -- cStage_uid125_lzCountVal_uid74_fpAddTest(BITJOIN,124)@6 cStage_uid125_lzCountVal_uid74_fpAddTest_q <= vStage_uid124_lzCountVal_uid74_fpAddTest_b & mO_uid123_lzCountVal_uid74_fpAddTest_q; - -- vStagei_uid127_lzCountVal_uid74_fpAddTest(MUX,126)@2 + -- vStagei_uid127_lzCountVal_uid74_fpAddTest(MUX,126)@6 + 1 vStagei_uid127_lzCountVal_uid74_fpAddTest_s <= vCount_uid122_lzCountVal_uid74_fpAddTest_q; - vStagei_uid127_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid127_lzCountVal_uid74_fpAddTest_s, en, rVStage_uid121_lzCountVal_uid74_fpAddTest_b, cStage_uid125_lzCountVal_uid74_fpAddTest_q) + vStagei_uid127_lzCountVal_uid74_fpAddTest_clkproc: PROCESS (clk, areset) BEGIN - CASE (vStagei_uid127_lzCountVal_uid74_fpAddTest_s) IS - WHEN "0" => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= rVStage_uid121_lzCountVal_uid74_fpAddTest_b; - WHEN "1" => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= cStage_uid125_lzCountVal_uid74_fpAddTest_q; - WHEN OTHERS => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= (others => '0'); - END CASE; + IF (areset = '1') THEN + vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + CASE (vStagei_uid127_lzCountVal_uid74_fpAddTest_s) IS + WHEN "0" => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= rVStage_uid121_lzCountVal_uid74_fpAddTest_b; + WHEN "1" => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= cStage_uid125_lzCountVal_uid74_fpAddTest_q; + WHEN OTHERS => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= (others => '0'); + END CASE; + END IF; + END IF; END PROCESS; - -- rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,199)@2 + -- rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,199)@7 rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b <= vStagei_uid127_lzCountVal_uid74_fpAddTest_q(7 downto 4); rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c <= vStagei_uid127_lzCountVal_uid74_fpAddTest_q(3 downto 0); - -- vCount_uid130_lzCountVal_uid74_fpAddTest(LOGICAL,129)@2 + 1 - vCount_uid130_lzCountVal_uid74_fpAddTest_qi <= "1" WHEN rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b = zs_uid128_lzCountVal_uid74_fpAddTest_q ELSE "0"; - vCount_uid130_lzCountVal_uid74_fpAddTest_delay : dspba_delay + -- vCount_uid130_lzCountVal_uid74_fpAddTest(LOGICAL,129)@7 + vCount_uid130_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b = zs_uid128_lzCountVal_uid74_fpAddTest_q ELSE "0"; + + -- redist2_vCount_uid130_lzCountVal_uid74_fpAddTest_q_1(DELAY,204) + redist2_vCount_uid130_lzCountVal_uid74_fpAddTest_q_1 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => vCount_uid130_lzCountVal_uid74_fpAddTest_qi, xout => vCount_uid130_lzCountVal_uid74_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); + PORT MAP ( xin => vCount_uid130_lzCountVal_uid74_fpAddTest_q, xout => redist2_vCount_uid130_lzCountVal_uid74_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); -- zs_uid134_lzCountVal_uid74_fpAddTest(CONSTANT,133) zs_uid134_lzCountVal_uid74_fpAddTest_q <= "00"; - -- redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1(DELAY,203) - redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1 : dspba_delay - GENERIC MAP ( width => 4, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c, xout => redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q, ena => en(0), clk => clk, aclr => areset ); - - -- redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1(DELAY,202) - redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1 : dspba_delay - GENERIC MAP ( width => 4, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b, xout => redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q, ena => en(0), clk => clk, aclr => areset ); - - -- vStagei_uid133_lzCountVal_uid74_fpAddTest(MUX,132)@3 + -- vStagei_uid133_lzCountVal_uid74_fpAddTest(MUX,132)@7 vStagei_uid133_lzCountVal_uid74_fpAddTest_s <= vCount_uid130_lzCountVal_uid74_fpAddTest_q; - vStagei_uid133_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid133_lzCountVal_uid74_fpAddTest_s, en, redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q, redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q) + vStagei_uid133_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid133_lzCountVal_uid74_fpAddTest_s, en, rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b, rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c) BEGIN CASE (vStagei_uid133_lzCountVal_uid74_fpAddTest_s) IS - WHEN "0" => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q; - WHEN "1" => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q; + WHEN "0" => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b; + WHEN "1" => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c; WHEN OTHERS => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,200)@3 + -- rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,200)@7 rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b <= vStagei_uid133_lzCountVal_uid74_fpAddTest_q(3 downto 2); rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c <= vStagei_uid133_lzCountVal_uid74_fpAddTest_q(1 downto 0); - -- vCount_uid136_lzCountVal_uid74_fpAddTest(LOGICAL,135)@3 - vCount_uid136_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b = zs_uid134_lzCountVal_uid74_fpAddTest_q ELSE "0"; + -- vCount_uid136_lzCountVal_uid74_fpAddTest(LOGICAL,135)@7 + 1 + vCount_uid136_lzCountVal_uid74_fpAddTest_qi <= "1" WHEN rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b = zs_uid134_lzCountVal_uid74_fpAddTest_q ELSE "0"; + vCount_uid136_lzCountVal_uid74_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => vCount_uid136_lzCountVal_uid74_fpAddTest_qi, xout => vCount_uid136_lzCountVal_uid74_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); + + -- redist1_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1(DELAY,203) + redist1_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1 : dspba_delay + GENERIC MAP ( width => 2, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c, xout => redist1_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- redist0_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1(DELAY,202) + redist0_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1 : dspba_delay + GENERIC MAP ( width => 2, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b, xout => redist0_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- vStagei_uid139_lzCountVal_uid74_fpAddTest(MUX,138)@3 + -- vStagei_uid139_lzCountVal_uid74_fpAddTest(MUX,138)@8 vStagei_uid139_lzCountVal_uid74_fpAddTest_s <= vCount_uid136_lzCountVal_uid74_fpAddTest_q; - vStagei_uid139_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid139_lzCountVal_uid74_fpAddTest_s, en, rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b, rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c) + vStagei_uid139_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid139_lzCountVal_uid74_fpAddTest_s, en, redist0_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q, redist1_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q) BEGIN CASE (vStagei_uid139_lzCountVal_uid74_fpAddTest_s) IS - WHEN "0" => vStagei_uid139_lzCountVal_uid74_fpAddTest_q <= rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b; - WHEN "1" => vStagei_uid139_lzCountVal_uid74_fpAddTest_q <= rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c; + WHEN "0" => vStagei_uid139_lzCountVal_uid74_fpAddTest_q <= redist0_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q; + WHEN "1" => vStagei_uid139_lzCountVal_uid74_fpAddTest_q <= redist1_rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q; WHEN OTHERS => vStagei_uid139_lzCountVal_uid74_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- rVStage_uid141_lzCountVal_uid74_fpAddTest(BITSELECT,140)@3 + -- rVStage_uid141_lzCountVal_uid74_fpAddTest(BITSELECT,140)@8 rVStage_uid141_lzCountVal_uid74_fpAddTest_b <= vStagei_uid139_lzCountVal_uid74_fpAddTest_q(1 downto 1); - -- vCount_uid142_lzCountVal_uid74_fpAddTest(LOGICAL,141)@3 + -- vCount_uid142_lzCountVal_uid74_fpAddTest(LOGICAL,141)@8 vCount_uid142_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid141_lzCountVal_uid74_fpAddTest_b = GND_q ELSE "0"; - -- r_uid143_lzCountVal_uid74_fpAddTest(BITJOIN,142)@3 - r_uid143_lzCountVal_uid74_fpAddTest_q <= redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1_q & vCount_uid130_lzCountVal_uid74_fpAddTest_q & vCount_uid136_lzCountVal_uid74_fpAddTest_q & vCount_uid142_lzCountVal_uid74_fpAddTest_q; + -- r_uid143_lzCountVal_uid74_fpAddTest(BITJOIN,142)@8 + r_uid143_lzCountVal_uid74_fpAddTest_q <= redist4_vCount_uid122_lzCountVal_uid74_fpAddTest_q_2_q & redist2_vCount_uid130_lzCountVal_uid74_fpAddTest_q_1_q & vCount_uid136_lzCountVal_uid74_fpAddTest_q & vCount_uid142_lzCountVal_uid74_fpAddTest_q; - -- aMinusA_uid77_fpAddTest(LOGICAL,76)@3 - aMinusA_uid77_fpAddTest_q <= "1" WHEN r_uid143_lzCountVal_uid74_fpAddTest_q = cAmA_uid76_fpAddTest_q ELSE "0"; + -- aMinusA_uid77_fpAddTest(LOGICAL,76)@8 + 1 + aMinusA_uid77_fpAddTest_qi <= "1" WHEN r_uid143_lzCountVal_uid74_fpAddTest_q = cAmA_uid76_fpAddTest_q ELSE "0"; + aMinusA_uid77_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => aMinusA_uid77_fpAddTest_qi, xout => aMinusA_uid77_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- invAMinusA_uid99_fpAddTest(LOGICAL,98)@3 + -- invAMinusA_uid99_fpAddTest(LOGICAL,98)@9 invAMinusA_uid99_fpAddTest_q <= not (aMinusA_uid77_fpAddTest_q); - -- redist9_sigA_uid50_fpAddTest_b_3(DELAY,211) - redist9_sigA_uid50_fpAddTest_b_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => sigA_uid50_fpAddTest_b, xout => redist9_sigA_uid50_fpAddTest_b_3_q, ena => en(0), clk => clk, aclr => areset ); + -- redist15_sigA_uid50_fpAddTest_b_7(DELAY,217) + redist15_sigA_uid50_fpAddTest_b_7 : dspba_delay + GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" ) + PORT MAP ( xin => sigA_uid50_fpAddTest_b, xout => redist15_sigA_uid50_fpAddTest_b_7_q, ena => en(0), clk => clk, aclr => areset ); -- cstAllOWE_uid18_fpAddTest(CONSTANT,17) cstAllOWE_uid18_fpAddTest_q <= "11111"; - -- expXIsMax_uid38_fpAddTest(LOGICAL,37)@1 + 1 - expXIsMax_uid38_fpAddTest_qi <= "1" WHEN redist16_exp_bSig_uid35_fpAddTest_b_1_q = cstAllOWE_uid18_fpAddTest_q ELSE "0"; + -- expXIsMax_uid38_fpAddTest(LOGICAL,37)@3 + 1 + expXIsMax_uid38_fpAddTest_qi <= "1" WHEN redist20_exp_bSig_uid35_fpAddTest_b_1_q = cstAllOWE_uid18_fpAddTest_q ELSE "0"; expXIsMax_uid38_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => expXIsMax_uid38_fpAddTest_qi, xout => expXIsMax_uid38_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist13_expXIsMax_uid38_fpAddTest_q_2(DELAY,215) - redist13_expXIsMax_uid38_fpAddTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid38_fpAddTest_q, xout => redist13_expXIsMax_uid38_fpAddTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); + -- redist18_expXIsMax_uid38_fpAddTest_q_5(DELAY,220) + redist18_expXIsMax_uid38_fpAddTest_q_5 : dspba_delay + GENERIC MAP ( width => 1, depth => 4, reset_kind => "ASYNC" ) + PORT MAP ( xin => expXIsMax_uid38_fpAddTest_q, xout => redist18_expXIsMax_uid38_fpAddTest_q_5_q, ena => en(0), clk => clk, aclr => areset ); - -- invExpXIsMax_uid43_fpAddTest(LOGICAL,42)@3 - invExpXIsMax_uid43_fpAddTest_q <= not (redist13_expXIsMax_uid38_fpAddTest_q_2_q); + -- invExpXIsMax_uid43_fpAddTest(LOGICAL,42)@8 + invExpXIsMax_uid43_fpAddTest_q <= not (redist18_expXIsMax_uid38_fpAddTest_q_5_q); - -- redist10_InvExpXIsZero_uid44_fpAddTest_q_2(DELAY,212) - redist10_InvExpXIsZero_uid44_fpAddTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => InvExpXIsZero_uid44_fpAddTest_q, xout => redist10_InvExpXIsZero_uid44_fpAddTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); + -- redist16_InvExpXIsZero_uid44_fpAddTest_q_6(DELAY,218) + redist16_InvExpXIsZero_uid44_fpAddTest_q_6 : dspba_delay + GENERIC MAP ( width => 1, depth => 6, reset_kind => "ASYNC" ) + PORT MAP ( xin => InvExpXIsZero_uid44_fpAddTest_q, xout => redist16_InvExpXIsZero_uid44_fpAddTest_q_6_q, ena => en(0), clk => clk, aclr => areset ); - -- excR_bSig_uid45_fpAddTest(LOGICAL,44)@3 - excR_bSig_uid45_fpAddTest_q <= redist10_InvExpXIsZero_uid44_fpAddTest_q_2_q and invExpXIsMax_uid43_fpAddTest_q; + -- excR_bSig_uid45_fpAddTest(LOGICAL,44)@8 + 1 + excR_bSig_uid45_fpAddTest_qi <= redist16_InvExpXIsZero_uid44_fpAddTest_q_6_q and invExpXIsMax_uid43_fpAddTest_q; + excR_bSig_uid45_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excR_bSig_uid45_fpAddTest_qi, xout => excR_bSig_uid45_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist20_exp_aSig_uid21_fpAddTest_b_3(DELAY,222) - redist20_exp_aSig_uid21_fpAddTest_b_3 : dspba_delay - GENERIC MAP ( width => 5, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist19_exp_aSig_uid21_fpAddTest_b_1_q, xout => redist20_exp_aSig_uid21_fpAddTest_b_3_q, ena => en(0), clk => clk, aclr => areset ); + -- redist25_exp_aSig_uid21_fpAddTest_b_5(DELAY,227) + redist25_exp_aSig_uid21_fpAddTest_b_5 : dspba_delay + GENERIC MAP ( width => 5, depth => 4, reset_kind => "ASYNC" ) + PORT MAP ( xin => redist24_exp_aSig_uid21_fpAddTest_b_1_q, xout => redist25_exp_aSig_uid21_fpAddTest_b_5_q, ena => en(0), clk => clk, aclr => areset ); - -- expXIsMax_uid24_fpAddTest(LOGICAL,23)@3 - expXIsMax_uid24_fpAddTest_q <= "1" WHEN redist20_exp_aSig_uid21_fpAddTest_b_3_q = cstAllOWE_uid18_fpAddTest_q ELSE "0"; + -- expXIsMax_uid24_fpAddTest(LOGICAL,23)@7 + 1 + expXIsMax_uid24_fpAddTest_qi <= "1" WHEN redist25_exp_aSig_uid21_fpAddTest_b_5_q = cstAllOWE_uid18_fpAddTest_q ELSE "0"; + expXIsMax_uid24_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => expXIsMax_uid24_fpAddTest_qi, xout => expXIsMax_uid24_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- invExpXIsMax_uid29_fpAddTest(LOGICAL,28)@3 + -- invExpXIsMax_uid29_fpAddTest(LOGICAL,28)@8 invExpXIsMax_uid29_fpAddTest_q <= not (expXIsMax_uid24_fpAddTest_q); - -- excZ_aSig_uid16_uid23_fpAddTest(LOGICAL,22)@3 - excZ_aSig_uid16_uid23_fpAddTest_q <= "1" WHEN redist20_exp_aSig_uid21_fpAddTest_b_3_q = cstAllZWE_uid20_fpAddTest_q ELSE "0"; + -- excZ_aSig_uid16_uid23_fpAddTest(LOGICAL,22)@7 + 1 + excZ_aSig_uid16_uid23_fpAddTest_qi <= "1" WHEN redist25_exp_aSig_uid21_fpAddTest_b_5_q = cstAllZWE_uid20_fpAddTest_q ELSE "0"; + excZ_aSig_uid16_uid23_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excZ_aSig_uid16_uid23_fpAddTest_qi, xout => excZ_aSig_uid16_uid23_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- InvExpXIsZero_uid30_fpAddTest(LOGICAL,29)@3 + -- InvExpXIsZero_uid30_fpAddTest(LOGICAL,29)@8 InvExpXIsZero_uid30_fpAddTest_q <= not (excZ_aSig_uid16_uid23_fpAddTest_q); - -- excR_aSig_uid31_fpAddTest(LOGICAL,30)@3 - excR_aSig_uid31_fpAddTest_q <= InvExpXIsZero_uid30_fpAddTest_q and invExpXIsMax_uid29_fpAddTest_q; + -- excR_aSig_uid31_fpAddTest(LOGICAL,30)@8 + 1 + excR_aSig_uid31_fpAddTest_qi <= InvExpXIsZero_uid30_fpAddTest_q and invExpXIsMax_uid29_fpAddTest_q; + excR_aSig_uid31_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excR_aSig_uid31_fpAddTest_qi, xout => excR_aSig_uid31_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- signRReg_uid100_fpAddTest(LOGICAL,99)@3 - signRReg_uid100_fpAddTest_q <= excR_aSig_uid31_fpAddTest_q and excR_bSig_uid45_fpAddTest_q and redist9_sigA_uid50_fpAddTest_b_3_q and invAMinusA_uid99_fpAddTest_q; + -- signRReg_uid100_fpAddTest(LOGICAL,99)@9 + signRReg_uid100_fpAddTest_q <= excR_aSig_uid31_fpAddTest_q and excR_bSig_uid45_fpAddTest_q and redist15_sigA_uid50_fpAddTest_b_7_q and invAMinusA_uid99_fpAddTest_q; - -- redist8_sigB_uid51_fpAddTest_b_3(DELAY,210) - redist8_sigB_uid51_fpAddTest_b_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => sigB_uid51_fpAddTest_b, xout => redist8_sigB_uid51_fpAddTest_b_3_q, ena => en(0), clk => clk, aclr => areset ); + -- redist14_sigB_uid51_fpAddTest_b_7(DELAY,216) + redist14_sigB_uid51_fpAddTest_b_7 : dspba_delay + GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" ) + PORT MAP ( xin => sigB_uid51_fpAddTest_b, xout => redist14_sigB_uid51_fpAddTest_b_7_q, ena => en(0), clk => clk, aclr => areset ); - -- redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3(DELAY,217) - redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1_q, xout => redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); + -- redist19_excZ_bSig_uid17_uid37_fpAddTest_q_7(DELAY,221) + redist19_excZ_bSig_uid17_uid37_fpAddTest_q_7 : dspba_delay + GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" ) + PORT MAP ( xin => excZ_bSig_uid17_uid37_fpAddTest_q, xout => redist19_excZ_bSig_uid17_uid37_fpAddTest_q_7_q, ena => en(0), clk => clk, aclr => areset ); - -- excAZBZSigASigB_uid104_fpAddTest(LOGICAL,103)@3 - excAZBZSigASigB_uid104_fpAddTest_q <= excZ_aSig_uid16_uid23_fpAddTest_q and redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q and redist9_sigA_uid50_fpAddTest_b_3_q and redist8_sigB_uid51_fpAddTest_b_3_q; + -- redist22_excZ_aSig_uid16_uid23_fpAddTest_q_2(DELAY,224) + redist22_excZ_aSig_uid16_uid23_fpAddTest_q_2 : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excZ_aSig_uid16_uid23_fpAddTest_q, xout => redist22_excZ_aSig_uid16_uid23_fpAddTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); + + -- excAZBZSigASigB_uid104_fpAddTest(LOGICAL,103)@9 + excAZBZSigASigB_uid104_fpAddTest_q <= redist22_excZ_aSig_uid16_uid23_fpAddTest_q_2_q and redist19_excZ_bSig_uid17_uid37_fpAddTest_q_7_q and redist15_sigA_uid50_fpAddTest_b_7_q and redist14_sigB_uid51_fpAddTest_b_7_q; - -- excBZARSigA_uid105_fpAddTest(LOGICAL,104)@3 - excBZARSigA_uid105_fpAddTest_q <= redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q and excR_aSig_uid31_fpAddTest_q and redist9_sigA_uid50_fpAddTest_b_3_q; + -- excBZARSigA_uid105_fpAddTest(LOGICAL,104)@9 + excBZARSigA_uid105_fpAddTest_q <= redist19_excZ_bSig_uid17_uid37_fpAddTest_q_7_q and excR_aSig_uid31_fpAddTest_q and redist15_sigA_uid50_fpAddTest_b_7_q; - -- signRZero_uid106_fpAddTest(LOGICAL,105)@3 + -- signRZero_uid106_fpAddTest(LOGICAL,105)@9 signRZero_uid106_fpAddTest_q <= excBZARSigA_uid105_fpAddTest_q or excAZBZSigASigB_uid104_fpAddTest_q; - -- fracXIsZero_uid39_fpAddTest(LOGICAL,38)@0 + 1 + -- fracXIsZero_uid39_fpAddTest(LOGICAL,38)@2 + 1 fracXIsZero_uid39_fpAddTest_qi <= "1" WHEN cstZeroWF_uid19_fpAddTest_q = frac_bSig_uid36_fpAddTest_b ELSE "0"; fracXIsZero_uid39_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => fracXIsZero_uid39_fpAddTest_qi, xout => fracXIsZero_uid39_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist12_fracXIsZero_uid39_fpAddTest_q_3(DELAY,214) - redist12_fracXIsZero_uid39_fpAddTest_q_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid39_fpAddTest_q, xout => redist12_fracXIsZero_uid39_fpAddTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); + -- redist17_fracXIsZero_uid39_fpAddTest_q_6(DELAY,219) + redist17_fracXIsZero_uid39_fpAddTest_q_6 : dspba_delay + GENERIC MAP ( width => 1, depth => 5, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracXIsZero_uid39_fpAddTest_q, xout => redist17_fracXIsZero_uid39_fpAddTest_q_6_q, ena => en(0), clk => clk, aclr => areset ); - -- excI_bSig_uid41_fpAddTest(LOGICAL,40)@3 - excI_bSig_uid41_fpAddTest_q <= redist13_expXIsMax_uid38_fpAddTest_q_2_q and redist12_fracXIsZero_uid39_fpAddTest_q_3_q; + -- excI_bSig_uid41_fpAddTest(LOGICAL,40)@8 + 1 + excI_bSig_uid41_fpAddTest_qi <= redist18_expXIsMax_uid38_fpAddTest_q_5_q and redist17_fracXIsZero_uid39_fpAddTest_q_6_q; + excI_bSig_uid41_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excI_bSig_uid41_fpAddTest_qi, xout => excI_bSig_uid41_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- sigBBInf_uid101_fpAddTest(LOGICAL,100)@3 - sigBBInf_uid101_fpAddTest_q <= redist8_sigB_uid51_fpAddTest_b_3_q and excI_bSig_uid41_fpAddTest_q; + -- sigBBInf_uid101_fpAddTest(LOGICAL,100)@9 + sigBBInf_uid101_fpAddTest_q <= redist14_sigB_uid51_fpAddTest_b_7_q and excI_bSig_uid41_fpAddTest_q; - -- fracXIsZero_uid25_fpAddTest(LOGICAL,24)@2 + 1 - fracXIsZero_uid25_fpAddTest_qi <= "1" WHEN cstZeroWF_uid19_fpAddTest_q = redist18_frac_aSig_uid22_fpAddTest_b_2_q ELSE "0"; + -- fracXIsZero_uid25_fpAddTest(LOGICAL,24)@5 + 1 + fracXIsZero_uid25_fpAddTest_qi <= "1" WHEN cstZeroWF_uid19_fpAddTest_q = redist23_frac_aSig_uid22_fpAddTest_b_3_q ELSE "0"; fracXIsZero_uid25_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => fracXIsZero_uid25_fpAddTest_qi, xout => fracXIsZero_uid25_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excI_aSig_uid27_fpAddTest(LOGICAL,26)@3 - excI_aSig_uid27_fpAddTest_q <= expXIsMax_uid24_fpAddTest_q and fracXIsZero_uid25_fpAddTest_q; + -- redist21_fracXIsZero_uid25_fpAddTest_q_3(DELAY,223) + redist21_fracXIsZero_uid25_fpAddTest_q_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracXIsZero_uid25_fpAddTest_q, xout => redist21_fracXIsZero_uid25_fpAddTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- sigAAInf_uid102_fpAddTest(LOGICAL,101)@3 - sigAAInf_uid102_fpAddTest_q <= redist9_sigA_uid50_fpAddTest_b_3_q and excI_aSig_uid27_fpAddTest_q; + -- excI_aSig_uid27_fpAddTest(LOGICAL,26)@8 + 1 + excI_aSig_uid27_fpAddTest_qi <= expXIsMax_uid24_fpAddTest_q and redist21_fracXIsZero_uid25_fpAddTest_q_3_q; + excI_aSig_uid27_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excI_aSig_uid27_fpAddTest_qi, xout => excI_aSig_uid27_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- signRInf_uid103_fpAddTest(LOGICAL,102)@3 + -- sigAAInf_uid102_fpAddTest(LOGICAL,101)@9 + sigAAInf_uid102_fpAddTest_q <= redist15_sigA_uid50_fpAddTest_b_7_q and excI_aSig_uid27_fpAddTest_q; + + -- signRInf_uid103_fpAddTest(LOGICAL,102)@9 signRInf_uid103_fpAddTest_q <= sigAAInf_uid102_fpAddTest_q or sigBBInf_uid101_fpAddTest_q; - -- signRInfRZRReg_uid107_fpAddTest(LOGICAL,106)@3 + 1 + -- signRInfRZRReg_uid107_fpAddTest(LOGICAL,106)@9 + 1 signRInfRZRReg_uid107_fpAddTest_qi <= signRInf_uid103_fpAddTest_q or signRZero_uid106_fpAddTest_q or signRReg_uid100_fpAddTest_q; signRInfRZRReg_uid107_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => signRInfRZRReg_uid107_fpAddTest_qi, xout => signRInfRZRReg_uid107_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- fracXIsNotZero_uid40_fpAddTest(LOGICAL,39)@3 - fracXIsNotZero_uid40_fpAddTest_q <= not (redist12_fracXIsZero_uid39_fpAddTest_q_3_q); + -- fracXIsNotZero_uid40_fpAddTest(LOGICAL,39)@8 + fracXIsNotZero_uid40_fpAddTest_q <= not (redist17_fracXIsZero_uid39_fpAddTest_q_6_q); - -- excN_bSig_uid42_fpAddTest(LOGICAL,41)@3 + 1 - excN_bSig_uid42_fpAddTest_qi <= redist13_expXIsMax_uid38_fpAddTest_q_2_q and fracXIsNotZero_uid40_fpAddTest_q; + -- excN_bSig_uid42_fpAddTest(LOGICAL,41)@8 + 1 + excN_bSig_uid42_fpAddTest_qi <= redist18_expXIsMax_uid38_fpAddTest_q_5_q and fracXIsNotZero_uid40_fpAddTest_q; excN_bSig_uid42_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => excN_bSig_uid42_fpAddTest_qi, xout => excN_bSig_uid42_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- fracXIsNotZero_uid26_fpAddTest(LOGICAL,25)@3 - fracXIsNotZero_uid26_fpAddTest_q <= not (fracXIsZero_uid25_fpAddTest_q); + -- fracXIsNotZero_uid26_fpAddTest(LOGICAL,25)@8 + fracXIsNotZero_uid26_fpAddTest_q <= not (redist21_fracXIsZero_uid25_fpAddTest_q_3_q); - -- excN_aSig_uid28_fpAddTest(LOGICAL,27)@3 + 1 + -- excN_aSig_uid28_fpAddTest(LOGICAL,27)@8 + 1 excN_aSig_uid28_fpAddTest_qi <= expXIsMax_uid24_fpAddTest_q and fracXIsNotZero_uid26_fpAddTest_q; excN_aSig_uid28_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => excN_aSig_uid28_fpAddTest_qi, xout => excN_aSig_uid28_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excRNaN2_uid94_fpAddTest(LOGICAL,93)@4 + -- excRNaN2_uid94_fpAddTest(LOGICAL,93)@9 excRNaN2_uid94_fpAddTest_q <= excN_aSig_uid28_fpAddTest_q or excN_bSig_uid42_fpAddTest_q; - -- redist7_effSub_uid52_fpAddTest_q_4(DELAY,209) - redist7_effSub_uid52_fpAddTest_q_4 : dspba_delay - GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => effSub_uid52_fpAddTest_q, xout => redist7_effSub_uid52_fpAddTest_q_4_q, ena => en(0), clk => clk, aclr => areset ); + -- redist13_effSub_uid52_fpAddTest_q_7(DELAY,215) + redist13_effSub_uid52_fpAddTest_q_7 : dspba_delay + GENERIC MAP ( width => 1, depth => 6, reset_kind => "ASYNC" ) + PORT MAP ( xin => redist12_effSub_uid52_fpAddTest_q_1_q, xout => redist13_effSub_uid52_fpAddTest_q_7_q, ena => en(0), clk => clk, aclr => areset ); - -- redist11_excI_bSig_uid41_fpAddTest_q_1(DELAY,213) - redist11_excI_bSig_uid41_fpAddTest_q_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_bSig_uid41_fpAddTest_q, xout => redist11_excI_bSig_uid41_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); + -- excAIBISub_uid95_fpAddTest(LOGICAL,94)@9 + excAIBISub_uid95_fpAddTest_q <= excI_aSig_uid27_fpAddTest_q and excI_bSig_uid41_fpAddTest_q and redist13_effSub_uid52_fpAddTest_q_7_q; - -- redist17_excI_aSig_uid27_fpAddTest_q_1(DELAY,219) - redist17_excI_aSig_uid27_fpAddTest_q_1 : dspba_delay + -- excRNaN_uid96_fpAddTest(LOGICAL,95)@9 + 1 + excRNaN_uid96_fpAddTest_qi <= excAIBISub_uid95_fpAddTest_q or excRNaN2_uid94_fpAddTest_q; + excRNaN_uid96_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_aSig_uid27_fpAddTest_q, xout => redist17_excI_aSig_uid27_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - - -- excAIBISub_uid95_fpAddTest(LOGICAL,94)@4 - excAIBISub_uid95_fpAddTest_q <= redist17_excI_aSig_uid27_fpAddTest_q_1_q and redist11_excI_bSig_uid41_fpAddTest_q_1_q and redist7_effSub_uid52_fpAddTest_q_4_q; - - -- excRNaN_uid96_fpAddTest(LOGICAL,95)@4 - excRNaN_uid96_fpAddTest_q <= excAIBISub_uid95_fpAddTest_q or excRNaN2_uid94_fpAddTest_q; + PORT MAP ( xin => excRNaN_uid96_fpAddTest_qi, xout => excRNaN_uid96_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- invExcRNaN_uid108_fpAddTest(LOGICAL,107)@4 + -- invExcRNaN_uid108_fpAddTest(LOGICAL,107)@10 invExcRNaN_uid108_fpAddTest_q <= not (excRNaN_uid96_fpAddTest_q); - -- signRPostExc_uid109_fpAddTest(LOGICAL,108)@4 + -- signRPostExc_uid109_fpAddTest(LOGICAL,108)@10 signRPostExc_uid109_fpAddTest_q <= invExcRNaN_uid108_fpAddTest_q and signRInfRZRReg_uid107_fpAddTest_q; - -- expInc_uid78_fpAddTest(ADD,77)@3 - expInc_uid78_fpAddTest_a <= STD_LOGIC_VECTOR("0" & redist20_exp_aSig_uid21_fpAddTest_b_3_q); + -- expInc_uid78_fpAddTest(ADD,77)@7 + 1 + expInc_uid78_fpAddTest_a <= STD_LOGIC_VECTOR("0" & redist25_exp_aSig_uid21_fpAddTest_b_5_q); expInc_uid78_fpAddTest_b <= STD_LOGIC_VECTOR("00000" & VCC_q); - expInc_uid78_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expInc_uid78_fpAddTest_a) + UNSIGNED(expInc_uid78_fpAddTest_b)); + expInc_uid78_fpAddTest_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + expInc_uid78_fpAddTest_o <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + expInc_uid78_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expInc_uid78_fpAddTest_a) + UNSIGNED(expInc_uid78_fpAddTest_b)); + END IF; + END IF; + END PROCESS; expInc_uid78_fpAddTest_q <= expInc_uid78_fpAddTest_o(5 downto 0); - -- expPostNorm_uid79_fpAddTest(SUB,78)@3 + -- expPostNorm_uid79_fpAddTest(SUB,78)@8 + 1 expPostNorm_uid79_fpAddTest_a <= STD_LOGIC_VECTOR("0" & expInc_uid78_fpAddTest_q); expPostNorm_uid79_fpAddTest_b <= STD_LOGIC_VECTOR("000" & r_uid143_lzCountVal_uid74_fpAddTest_q); - expPostNorm_uid79_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNorm_uid79_fpAddTest_a) - UNSIGNED(expPostNorm_uid79_fpAddTest_b)); + expPostNorm_uid79_fpAddTest_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + expPostNorm_uid79_fpAddTest_o <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + expPostNorm_uid79_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNorm_uid79_fpAddTest_a) - UNSIGNED(expPostNorm_uid79_fpAddTest_b)); + END IF; + END IF; + END PROCESS; expPostNorm_uid79_fpAddTest_q <= expPostNorm_uid79_fpAddTest_o(6 downto 0); - -- leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest(BITSELECT,193)@3 + -- leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest(BITSELECT,193)@8 leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q(10 downto 0); leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_in(10 downto 0); -- leftShiftStage1Idx3Pad3_uid193_fracPostNorm_uid75_fpAddTest(CONSTANT,192) leftShiftStage1Idx3Pad3_uid193_fracPostNorm_uid75_fpAddTest_q <= "000"; - -- leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest(BITJOIN,194)@3 + -- leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest(BITJOIN,194)@8 leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_b & leftShiftStage1Idx3Pad3_uid193_fracPostNorm_uid75_fpAddTest_q; - -- leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest(BITSELECT,190)@3 + -- leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest(BITSELECT,190)@8 leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q(11 downto 0); leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_in(11 downto 0); - -- leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest(BITJOIN,191)@3 + -- leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest(BITJOIN,191)@8 leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_b & zs_uid134_lzCountVal_uid74_fpAddTest_q; - -- leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest(BITSELECT,187)@3 + -- leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest(BITSELECT,187)@8 leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q(12 downto 0); leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_in(12 downto 0); - -- leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest(BITJOIN,188)@3 + -- leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest(BITJOIN,188)@8 leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_b & GND_q; - -- leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest(BITSELECT,182)@3 - leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_in <= redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q(1 downto 0); + -- leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest(BITSELECT,182)@8 + leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_in <= redist10_fracAddResultNoSignExt_uid73_fpAddTest_b_3_q(1 downto 0); leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_in(1 downto 0); -- leftShiftStage0Idx3Pad12_uid182_fracPostNorm_uid75_fpAddTest(CONSTANT,181) leftShiftStage0Idx3Pad12_uid182_fracPostNorm_uid75_fpAddTest_q <= "000000000000"; - -- leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest(BITJOIN,183)@3 + -- leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest(BITJOIN,183)@8 leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_b & leftShiftStage0Idx3Pad12_uid182_fracPostNorm_uid75_fpAddTest_q; - -- redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1(DELAY,204) - redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1 : dspba_delay - GENERIC MAP ( width => 6, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => vStage_uid124_lzCountVal_uid74_fpAddTest_b, xout => redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + -- redist3_vStage_uid124_lzCountVal_uid74_fpAddTest_b_2(DELAY,205) + redist3_vStage_uid124_lzCountVal_uid74_fpAddTest_b_2 : dspba_delay + GENERIC MAP ( width => 6, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => vStage_uid124_lzCountVal_uid74_fpAddTest_b, xout => redist3_vStage_uid124_lzCountVal_uid74_fpAddTest_b_2_q, ena => en(0), clk => clk, aclr => areset ); - -- leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest(BITJOIN,180)@3 - leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q <= redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1_q & zs_uid120_lzCountVal_uid74_fpAddTest_q; + -- leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest(BITJOIN,180)@8 + leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q <= redist3_vStage_uid124_lzCountVal_uid74_fpAddTest_b_2_q & zs_uid120_lzCountVal_uid74_fpAddTest_q; - -- leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest(BITSELECT,176)@3 - leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_in <= redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q(9 downto 0); + -- leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest(BITSELECT,176)@8 + leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_in <= redist10_fracAddResultNoSignExt_uid73_fpAddTest_b_3_q(9 downto 0); leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_in(9 downto 0); - -- leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest(BITJOIN,177)@3 + -- leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest(BITJOIN,177)@8 leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_b & zs_uid128_lzCountVal_uid74_fpAddTest_q; - -- redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1(DELAY,208) - redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1 : dspba_delay - GENERIC MAP ( width => 14, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracAddResultNoSignExt_uid73_fpAddTest_b, xout => redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + -- redist10_fracAddResultNoSignExt_uid73_fpAddTest_b_3(DELAY,212) + redist10_fracAddResultNoSignExt_uid73_fpAddTest_b_3 : dspba_delay + GENERIC MAP ( width => 14, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => redist9_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q, xout => redist10_fracAddResultNoSignExt_uid73_fpAddTest_b_3_q, ena => en(0), clk => clk, aclr => areset ); - -- leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest(MUX,185)@3 + -- leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest(MUX,185)@8 leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_s <= leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_b; - leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_combproc: PROCESS (leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_s, en, redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q, leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest_q, leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q, leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest_q) + leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_combproc: PROCESS (leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_s, en, redist10_fracAddResultNoSignExt_uid73_fpAddTest_b_3_q, leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest_q, leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q, leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest_q) BEGIN CASE (leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_s) IS - WHEN "00" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q; + WHEN "00" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= redist10_fracAddResultNoSignExt_uid73_fpAddTest_b_3_q; WHEN "01" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest_q; WHEN "10" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q; WHEN "11" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest_q; @@ -922,11 +1046,11 @@ begin END CASE; END PROCESS; - -- leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select(BITSELECT,201)@3 + -- leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select(BITSELECT,201)@8 leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_b <= r_uid143_lzCountVal_uid74_fpAddTest_q(3 downto 2); leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_c <= r_uid143_lzCountVal_uid74_fpAddTest_q(1 downto 0); - -- leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest(MUX,196)@3 + -- leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest(MUX,196)@8 leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_s <= leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_c; leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_combproc: PROCESS (leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_s, en, leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q, leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest_q, leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest_q, leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest_q) BEGIN @@ -939,50 +1063,55 @@ begin END CASE; END PROCESS; - -- fracPostNormRndRange_uid80_fpAddTest(BITSELECT,79)@3 + -- fracPostNormRndRange_uid80_fpAddTest(BITSELECT,79)@8 fracPostNormRndRange_uid80_fpAddTest_in <= leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_q(12 downto 0); fracPostNormRndRange_uid80_fpAddTest_b <= fracPostNormRndRange_uid80_fpAddTest_in(12 downto 2); - -- expFracR_uid81_fpAddTest(BITJOIN,80)@3 - expFracR_uid81_fpAddTest_q <= expPostNorm_uid79_fpAddTest_q & fracPostNormRndRange_uid80_fpAddTest_b; + -- redist8_fracPostNormRndRange_uid80_fpAddTest_b_1(DELAY,210) + redist8_fracPostNormRndRange_uid80_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 11, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracPostNormRndRange_uid80_fpAddTest_b, xout => redist8_fracPostNormRndRange_uid80_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- redist5_expFracR_uid81_fpAddTest_q_1(DELAY,207) - redist5_expFracR_uid81_fpAddTest_q_1 : dspba_delay - GENERIC MAP ( width => 18, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expFracR_uid81_fpAddTest_q, xout => redist5_expFracR_uid81_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); + -- expFracR_uid81_fpAddTest(BITJOIN,80)@9 + expFracR_uid81_fpAddTest_q <= expPostNorm_uid79_fpAddTest_q & redist8_fracPostNormRndRange_uid80_fpAddTest_b_1_q; - -- expRPreExc_uid87_fpAddTest(BITSELECT,86)@4 - expRPreExc_uid87_fpAddTest_in <= redist5_expFracR_uid81_fpAddTest_q_1_q(15 downto 0); + -- expRPreExc_uid87_fpAddTest(BITSELECT,86)@9 + expRPreExc_uid87_fpAddTest_in <= expFracR_uid81_fpAddTest_q(15 downto 0); expRPreExc_uid87_fpAddTest_b <= expRPreExc_uid87_fpAddTest_in(15 downto 11); + -- redist6_expRPreExc_uid87_fpAddTest_b_1(DELAY,208) + redist6_expRPreExc_uid87_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => expRPreExc_uid87_fpAddTest_b, xout => redist6_expRPreExc_uid87_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + -- wEP2AllOwE_uid82_fpAddTest(CONSTANT,81) wEP2AllOwE_uid82_fpAddTest_q <= "0011111"; - -- rndExp_uid83_fpAddTest(BITSELECT,82)@4 - rndExp_uid83_fpAddTest_b <= redist5_expFracR_uid81_fpAddTest_q_1_q(17 downto 11); + -- rndExp_uid83_fpAddTest(BITSELECT,82)@9 + rndExp_uid83_fpAddTest_b <= expFracR_uid81_fpAddTest_q(17 downto 11); - -- rOvf_uid84_fpAddTest(LOGICAL,83)@4 + -- rOvf_uid84_fpAddTest(LOGICAL,83)@9 rOvf_uid84_fpAddTest_q <= "1" WHEN rndExp_uid83_fpAddTest_b = wEP2AllOwE_uid82_fpAddTest_q ELSE "0"; - -- regInputs_uid88_fpAddTest(LOGICAL,87)@3 + -- regInputs_uid88_fpAddTest(LOGICAL,87)@9 regInputs_uid88_fpAddTest_q <= excR_aSig_uid31_fpAddTest_q and excR_bSig_uid45_fpAddTest_q; - -- redist4_regInputs_uid88_fpAddTest_q_1(DELAY,206) - redist4_regInputs_uid88_fpAddTest_q_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => regInputs_uid88_fpAddTest_q, xout => redist4_regInputs_uid88_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); + -- rInfOvf_uid91_fpAddTest(LOGICAL,90)@9 + rInfOvf_uid91_fpAddTest_q <= regInputs_uid88_fpAddTest_q and rOvf_uid84_fpAddTest_q; - -- rInfOvf_uid91_fpAddTest(LOGICAL,90)@4 - rInfOvf_uid91_fpAddTest_q <= redist4_regInputs_uid88_fpAddTest_q_1_q and rOvf_uid84_fpAddTest_q; + -- excRInfVInC_uid92_fpAddTest(BITJOIN,91)@9 + excRInfVInC_uid92_fpAddTest_q <= rInfOvf_uid91_fpAddTest_q & excN_bSig_uid42_fpAddTest_q & excN_aSig_uid28_fpAddTest_q & excI_bSig_uid41_fpAddTest_q & excI_aSig_uid27_fpAddTest_q & redist13_effSub_uid52_fpAddTest_q_7_q; - -- excRInfVInC_uid92_fpAddTest(BITJOIN,91)@4 - excRInfVInC_uid92_fpAddTest_q <= rInfOvf_uid91_fpAddTest_q & excN_bSig_uid42_fpAddTest_q & excN_aSig_uid28_fpAddTest_q & redist11_excI_bSig_uid41_fpAddTest_q_1_q & redist17_excI_aSig_uid27_fpAddTest_q_1_q & redist7_effSub_uid52_fpAddTest_q_4_q; + -- redist5_excRInfVInC_uid92_fpAddTest_q_1(DELAY,207) + redist5_excRInfVInC_uid92_fpAddTest_q_1 : dspba_delay + GENERIC MAP ( width => 6, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excRInfVInC_uid92_fpAddTest_q, xout => redist5_excRInfVInC_uid92_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - -- excRInf_uid93_fpAddTest(LOOKUP,92)@4 - excRInf_uid93_fpAddTest_combproc: PROCESS (excRInfVInC_uid92_fpAddTest_q) + -- excRInf_uid93_fpAddTest(LOOKUP,92)@10 + excRInf_uid93_fpAddTest_combproc: PROCESS (redist5_excRInfVInC_uid92_fpAddTest_q_1_q) BEGIN -- Begin reserved scope level - CASE (excRInfVInC_uid92_fpAddTest_q) IS + CASE (redist5_excRInfVInC_uid92_fpAddTest_q_1_q) IS WHEN "000000" => excRInf_uid93_fpAddTest_q <= "0"; WHEN "000001" => excRInf_uid93_fpAddTest_q <= "0"; WHEN "000010" => excRInf_uid93_fpAddTest_q <= "1"; @@ -1053,13 +1182,13 @@ begin -- End reserved scope level END PROCESS; - -- rUdf_uid85_fpAddTest(BITSELECT,84)@3 + -- rUdf_uid85_fpAddTest(BITSELECT,84)@9 rUdf_uid85_fpAddTest_b <= STD_LOGIC_VECTOR(expFracR_uid81_fpAddTest_q(17 downto 17)); - -- excRZeroVInC_uid89_fpAddTest(BITJOIN,88)@3 - excRZeroVInC_uid89_fpAddTest_q <= aMinusA_uid77_fpAddTest_q & rUdf_uid85_fpAddTest_b & regInputs_uid88_fpAddTest_q & redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q & excZ_aSig_uid16_uid23_fpAddTest_q; + -- excRZeroVInC_uid89_fpAddTest(BITJOIN,88)@9 + excRZeroVInC_uid89_fpAddTest_q <= aMinusA_uid77_fpAddTest_q & rUdf_uid85_fpAddTest_b & regInputs_uid88_fpAddTest_q & redist19_excZ_bSig_uid17_uid37_fpAddTest_q_7_q & redist22_excZ_aSig_uid16_uid23_fpAddTest_q_2_q; - -- excRZero_uid90_fpAddTest(LOOKUP,89)@3 + 1 + -- excRZero_uid90_fpAddTest(LOOKUP,89)@9 + 1 excRZero_uid90_fpAddTest_clkproc: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN @@ -1106,10 +1235,10 @@ begin END IF; END PROCESS; - -- concExc_uid97_fpAddTest(BITJOIN,96)@4 + -- concExc_uid97_fpAddTest(BITJOIN,96)@10 concExc_uid97_fpAddTest_q <= excRNaN_uid96_fpAddTest_q & excRInf_uid93_fpAddTest_q & excRZero_uid90_fpAddTest_q; - -- excREnc_uid98_fpAddTest(LOOKUP,97)@4 + -- excREnc_uid98_fpAddTest(LOOKUP,97)@10 excREnc_uid98_fpAddTest_combproc: PROCESS (concExc_uid97_fpAddTest_q) BEGIN -- Begin reserved scope level @@ -1128,13 +1257,13 @@ begin -- End reserved scope level END PROCESS; - -- expRPostExc_uid117_fpAddTest(MUX,116)@4 + -- expRPostExc_uid117_fpAddTest(MUX,116)@10 expRPostExc_uid117_fpAddTest_s <= excREnc_uid98_fpAddTest_q; - expRPostExc_uid117_fpAddTest_combproc: PROCESS (expRPostExc_uid117_fpAddTest_s, en, cstAllZWE_uid20_fpAddTest_q, expRPreExc_uid87_fpAddTest_b, cstAllOWE_uid18_fpAddTest_q) + expRPostExc_uid117_fpAddTest_combproc: PROCESS (expRPostExc_uid117_fpAddTest_s, en, cstAllZWE_uid20_fpAddTest_q, redist6_expRPreExc_uid87_fpAddTest_b_1_q, cstAllOWE_uid18_fpAddTest_q) BEGIN CASE (expRPostExc_uid117_fpAddTest_s) IS WHEN "00" => expRPostExc_uid117_fpAddTest_q <= cstAllZWE_uid20_fpAddTest_q; - WHEN "01" => expRPostExc_uid117_fpAddTest_q <= expRPreExc_uid87_fpAddTest_b; + WHEN "01" => expRPostExc_uid117_fpAddTest_q <= redist6_expRPreExc_uid87_fpAddTest_b_1_q; WHEN "10" => expRPostExc_uid117_fpAddTest_q <= cstAllOWE_uid18_fpAddTest_q; WHEN "11" => expRPostExc_uid117_fpAddTest_q <= cstAllOWE_uid18_fpAddTest_q; WHEN OTHERS => expRPostExc_uid117_fpAddTest_q <= (others => '0'); @@ -1144,27 +1273,32 @@ begin -- oneFracRPostExc2_uid110_fpAddTest(CONSTANT,109) oneFracRPostExc2_uid110_fpAddTest_q <= "0000000001"; - -- fracRPreExc_uid86_fpAddTest(BITSELECT,85)@4 - fracRPreExc_uid86_fpAddTest_in <= redist5_expFracR_uid81_fpAddTest_q_1_q(10 downto 0); + -- fracRPreExc_uid86_fpAddTest(BITSELECT,85)@9 + fracRPreExc_uid86_fpAddTest_in <= expFracR_uid81_fpAddTest_q(10 downto 0); fracRPreExc_uid86_fpAddTest_b <= fracRPreExc_uid86_fpAddTest_in(10 downto 1); - -- fracRPostExc_uid113_fpAddTest(MUX,112)@4 + -- redist7_fracRPreExc_uid86_fpAddTest_b_1(DELAY,209) + redist7_fracRPreExc_uid86_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 10, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracRPreExc_uid86_fpAddTest_b, xout => redist7_fracRPreExc_uid86_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- fracRPostExc_uid113_fpAddTest(MUX,112)@10 fracRPostExc_uid113_fpAddTest_s <= excREnc_uid98_fpAddTest_q; - fracRPostExc_uid113_fpAddTest_combproc: PROCESS (fracRPostExc_uid113_fpAddTest_s, en, cstZeroWF_uid19_fpAddTest_q, fracRPreExc_uid86_fpAddTest_b, oneFracRPostExc2_uid110_fpAddTest_q) + fracRPostExc_uid113_fpAddTest_combproc: PROCESS (fracRPostExc_uid113_fpAddTest_s, en, cstZeroWF_uid19_fpAddTest_q, redist7_fracRPreExc_uid86_fpAddTest_b_1_q, oneFracRPostExc2_uid110_fpAddTest_q) BEGIN CASE (fracRPostExc_uid113_fpAddTest_s) IS WHEN "00" => fracRPostExc_uid113_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q; - WHEN "01" => fracRPostExc_uid113_fpAddTest_q <= fracRPreExc_uid86_fpAddTest_b; + WHEN "01" => fracRPostExc_uid113_fpAddTest_q <= redist7_fracRPreExc_uid86_fpAddTest_b_1_q; WHEN "10" => fracRPostExc_uid113_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q; WHEN "11" => fracRPostExc_uid113_fpAddTest_q <= oneFracRPostExc2_uid110_fpAddTest_q; WHEN OTHERS => fracRPostExc_uid113_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- R_uid118_fpAddTest(BITJOIN,117)@4 + -- R_uid118_fpAddTest(BITJOIN,117)@10 R_uid118_fpAddTest_q <= signRPostExc_uid109_fpAddTest_q & expRPostExc_uid117_fpAddTest_q & fracRPostExc_uid113_fpAddTest_q; - -- xOut(GPOUT,4)@4 + -- xOut(GPOUT,4)@10 q <= R_uid118_fpAddTest_q; END normal; diff --git a/ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl b/ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl index 30e7693..872a0c8 100644 --- a/ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl +++ b/ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- diff --git a/ip/ip_fp_add_sim/cadence/ncsim_setup.sh b/ip/ip_fp_add_sim/cadence/ncsim_setup.sh index f2c4933..73d2377 100755 --- a/ip/ip_fp_add_sim/cadence/ncsim_setup.sh +++ b/ip/ip_fp_add_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,7 +106,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_add" diff --git a/ip/ip_fp_add_sim/ip_fp_add.vo b/ip/ip_fp_add_sim/ip_fp_add.vo index 3f5f32a..956f9f3 100644 --- a/ip/ip_fp_add_sim/ip_fp_add.vo +++ b/ip/ip_fp_add_sim/ip_fp_add.vo @@ -27,7 +27,7 @@ //synopsys translate_off -//synthesis_resources = lut 135 mux21 66 oper_add 7 oper_mux 68 +//synthesis_resources = lut 341 mux21 66 oper_add 7 oper_mux 68 `timescale 1 ps / 1 ps module ip_fp_add ( @@ -44,46 +44,18 @@ module ip_fp_add input [0:0] en; output [15:0] q; - reg n000i; - reg n000l; - reg n000O; - reg n001i; - reg n001l; - reg n001O; - reg n00ii; - reg n00il; - reg n00iO; - reg n00li; - reg n00ll; - reg n00lO; - reg n00Oi; - reg n00Ol; - reg n00OO; - reg n010i; - reg n010l; - reg n010O; - reg n011i; - reg n011l; - reg n011O; - reg n01ii; - reg n01il; - reg n01iO; - reg n01li; - reg n01ll; - reg n01lO; - reg n01Oi; - reg n01Ol; - reg n01OO; - reg n0i1i; - reg n0i1l; + reg n00i; + reg n00l; + reg n00O; + reg n01i; + reg n01l; + reg n01O; reg n0ii; reg n0il; reg n0iO; reg n0li; - reg n0ll; - reg n0lO; - reg n0Oi; - reg n0Ol; + reg n0O1O; + reg n0Oil; reg n100i; reg n100l; reg n100O; @@ -135,61 +107,309 @@ module ip_fp_add reg n1l1i; reg n1l1l; reg n1l1O; + reg n1li; reg n1lii; reg n1lil; reg n1liO; + reg n1ll; reg n1lli; reg n1lll; reg n1llO; + reg n1lO; reg n1lOi; - reg n1lOl; - reg n1lOO; - reg n1O0i; - reg n1O0l; - reg n1O0O; - reg n1O1i; - reg n1O1l; - reg n1O1O; - reg n1Oii; - reg n1Oil; - reg n1OiO; - reg n1Oli; - reg n1Oll; - reg n1OlO; - reg n1OOi; - reg n1OOl; - reg n1OOO; - reg ni1i; - reg niiii; - reg niilO; - reg nl0OO; - reg nli0i; - reg nli0l; - reg nli0O; - reg nli1i; - reg nli1l; - reg nli1O; - reg nliii; - reg nliil; - reg nliiO; - reg nlili; - reg nlill; + reg n1Oi; + reg n1Ol; + reg n1OO; + reg ni00i; + reg ni00l; + reg ni00O; + reg ni01l; + reg ni01O; + reg ni0ii; + reg ni0il; + reg ni0li; + reg ni0ll; + reg ni0lO; + reg ni0Oi; + reg ni0Ol; + reg nilO; + reg nilOO; + reg niO0i; + reg niO0l; + reg niO0O; + reg niO1i; + reg niO1l; + reg niO1O; + reg niOi; + reg niOii; + reg niOl; + reg niOO; + reg nl0i; + reg nl0l; + reg nl0O; + reg nl10i; + reg nl10l; + reg nl10O; + reg nl11i; + reg nl11l; + reg nl11O; + reg nl1i; + reg nl1ii; + reg nl1il; + reg nl1iO; + reg nl1l; + reg nl1li; + reg nl1ll; + reg nl1lO; + reg nl1O; + reg nl1Oi; + reg nl1Ol; + reg nli00i; + reg nli00l; + reg nli00O; + reg nli01l; + reg nli01O; + reg nli0ii; + reg nli0il; + reg nli0iO; + reg nli0li; + reg nli0ll; + reg nli0lO; + reg nli0Oi; + reg nli0Ol; + reg nli0OO; + reg nlii; + reg nlii0i; + reg nlii0l; + reg nlii0O; + reg nlii1i; + reg nlii1l; + reg nlii1O; + reg nliiii; + reg nliiil; + reg nliiiO; + reg nliili; + reg nliill; + reg nliilO; + reg nliiOi; + reg nliiOl; + reg nliiOO; + reg nlil; + reg nlil0i; + reg nlil0l; + reg nlil0O; + reg nlil1i; + reg nlil1l; + reg nlil1O; + reg nlilii; + reg nlilil; + reg nliliO; + reg nlilli; + reg nlilll; + reg nlillO; reg nlilO; + reg nlilOi; + reg nlilOl; + reg nlilOO; + reg nliO; + reg nliO0i; + reg nliO0l; + reg nliO0O; + reg nliO1i; + reg nliO1l; + reg nliO1O; reg nliOi; + reg nliOii; + reg nliOil; + reg nliOiO; + reg nliOl; + reg nliOli; + reg nliOll; + reg nliOlO; + reg nliOO; + reg nliOOi; + reg nliOOl; + reg nliOOO; + reg nll00i; + reg nll00l; + reg nll00O; + reg nll01i; + reg nll01l; + reg nll01O; + reg nll0ii; + reg nll0il; + reg nll0iO; + reg nll0li; + reg nll0ll; + reg nll0lO; + reg nll0Oi; + reg nll0Ol; + reg nll0OO; + reg nll10i; + reg nll10l; + reg nll10O; + reg nll11i; + reg nll11l; + reg nll11O; + reg nll1i; + reg nll1ii; + reg nll1il; + reg nll1iO; + reg nll1l; + reg nll1li; + reg nll1ll; + reg nll1lO; + reg nll1Oi; + reg nll1Ol; + reg nll1OO; + reg nlli; + reg nlli0i; + reg nlli0l; + reg nlli0O; + reg nlli1i; + reg nlli1l; + reg nlli1O; + reg nlliii; + reg nlliil; + reg nlliiO; + reg nllili; + reg nllill; + reg nllilO; + reg nlliOi; + reg nlliOl; + reg nlliOO; + reg nlll; + reg nlll0i; + reg nlll0l; + reg nlll0O; + reg nlll1i; + reg nlll1l; + reg nlll1O; + reg nlllii; + reg nlllil; + reg nllliO; + reg nlllli; + reg nlllll; + reg nllllO; + reg nlllOi; + reg nlllOl; + reg nlllOO; + reg nllO0i; + reg nllO0l; + reg nllO0O; + reg nllO1i; + reg nllO1l; + reg nllO1O; + reg nllOii; + reg nllOil; + reg nllOiO; + reg nllOli; + reg nllOll; + reg nllOlO; + reg nllOOi; + reg nllOOl; + reg nllOOO; + reg nlO00i; + reg nlO00l; + reg nlO00O; + reg nlO01i; + reg nlO01l; + reg nlO01O; + reg nlO0ii; + reg nlO0il; + reg nlO0iO; + reg nlO0li; + reg nlO0ll; + reg nlO0lO; + reg nlO0Oi; + reg nlO0Ol; + reg nlO0OO; + reg nlO10i; + reg nlO10l; + reg nlO10O; + reg nlO11i; + reg nlO11l; + reg nlO11O; + reg nlO1ii; + reg nlO1il; + reg nlO1iO; + reg nlO1li; + reg nlO1ll; + reg nlO1lO; + reg nlO1Oi; + reg nlO1Ol; + reg nlO1OO; + reg nlOi; + reg nlOi0i; + reg nlOi0l; + reg nlOi0O; + reg nlOi1i; + reg nlOi1l; + reg nlOi1O; + reg nlOiii; + reg nlOiil; + reg nlOiiO; + reg nlOili; + reg nlOill; + reg nlOilO; + reg nlOiOi; + reg nlOiOl; + reg nlOiOO; + reg nlOl0i; + reg nlOl0l; + reg nlOl0O; + reg nlOl1i; + reg nlOl1l; + reg nlOl1O; + reg nlOlii; + reg nlOlil; + reg nlOliO; + reg nlOlli; + reg nlOlll; + reg nlOllO; + reg nlOlOi; + reg nlOlOl; + reg nlOlOO; + reg nlOO0i; + reg nlOO0l; + reg nlOO0O; + reg nlOO1i; + reg nlOO1l; + reg nlOO1O; + reg nlOOii; + reg nlOOil; + reg nlOOiO; + reg nlOOli; + reg nlOOll; + reg nlOOlO; reg nlOOOi; reg nlOOOl; reg nlOOOO; - wire wire_n0OO_ENA; + wire wire_nllO_ENA; wire wire_n0i_dataout; wire wire_n0l_dataout; + wire wire_n0ll_dataout; + wire wire_n0lO_dataout; wire wire_n0O_dataout; + wire wire_n0Oi_dataout; + wire wire_n0Ol_dataout; + wire wire_n0OO_dataout; + wire wire_n10i_dataout; + wire wire_n10l_dataout; + wire wire_n10O_dataout; + wire wire_n11i_dataout; + wire wire_n11l_dataout; + wire wire_n11O_dataout; wire wire_n1i_dataout; + wire wire_n1ii_dataout; + wire wire_n1il_dataout; wire wire_n1l_dataout; wire wire_n1O_dataout; wire wire_ni_dataout; wire wire_ni0i_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; + wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii_dataout; @@ -199,188 +419,141 @@ module ip_fp_add wire wire_nil_dataout; wire wire_nili_dataout; wire wire_nill_dataout; + wire wire_nilll_dataout; + wire wire_nillO_dataout; + wire wire_nilOi_dataout; + wire wire_nilOl_dataout; wire wire_niO_dataout; - wire wire_niOi_dataout; - wire wire_niOl_dataout; - wire wire_niOO_dataout; + wire wire_niOil_dataout; + wire wire_niOiO_dataout; + wire wire_niOli_dataout; + wire wire_niOll_dataout; + wire wire_niOlO_dataout; + wire wire_niOOi_dataout; + wire wire_niOOl_dataout; wire wire_nl_dataout; wire wire_nl00i_dataout; wire wire_nl00l_dataout; wire wire_nl00O_dataout; + wire wire_nl01i_dataout; + wire wire_nl01l_dataout; wire wire_nl01O_dataout; - wire wire_nl0i_dataout; wire wire_nl0ii_dataout; wire wire_nl0il_dataout; wire wire_nl0iO_dataout; - wire wire_nl0l_dataout; wire wire_nl0li_dataout; wire wire_nl0ll_dataout; wire wire_nl0lO_dataout; - wire wire_nl0O_dataout; - wire wire_nl0Oi_dataout; - wire wire_nl1i_dataout; - wire wire_nl1l_dataout; - wire wire_nl1O_dataout; + wire wire_nl1OO_dataout; wire wire_nli_dataout; - wire wire_nlii_dataout; - wire wire_nlil_dataout; - wire wire_nliO_dataout; - wire wire_nliOl_dataout; - wire wire_nliOO_dataout; wire wire_nll_dataout; - wire wire_nll0i_dataout; - wire wire_nll0l_dataout; - wire wire_nll0O_dataout; - wire wire_nll1i_dataout; - wire wire_nll1l_dataout; - wire wire_nll1O_dataout; - wire wire_nlli_dataout; - wire wire_nllii_dataout; - wire wire_nllil_dataout; - wire wire_nlliO_dataout; - wire wire_nlll_dataout; - wire wire_nllli_dataout; - wire wire_nllll_dataout; - wire wire_nllO_dataout; wire wire_nlO_dataout; - wire wire_nlOi_dataout; wire wire_nlOl_dataout; wire wire_nlOO_dataout; - wire [14:0] wire_n1li_o; - wire [7:0] wire_niO0O_o; - wire [5:0] wire_niOii_o; - wire [14:0] wire_nl0Ol_o; - wire [8:0] wire_nlllO_o; - wire [6:0] wire_nlOll_o; + wire wire_nlOOl_dataout; + wire wire_nlOOO_dataout; + wire [7:0] wire_ni0iO_o; + wire [5:0] wire_ni0OO_o; + wire [14:0] wire_niOOO_o; + wire [8:0] wire_nl0Oi_o; + wire [6:0] wire_nll1O_o; + wire [14:0] wire_nlO1l_o; wire [17:0] wire_nO_o; - wire wire_n10i_o; - wire wire_n10l_o; - wire wire_n10O_o; - wire wire_n11i_o; - wire wire_n11l_o; - wire wire_n11O_o; - wire wire_n1ii_o; - wire wire_n1il_o; - wire wire_n1iO_o; - wire wire_ni00l_o; - wire wire_ni00O_o; - wire wire_ni0ii_o; - wire wire_ni0il_o; - wire wire_ni0iO_o; - wire wire_ni0li_o; - wire wire_ni0ll_o; - wire wire_ni0lO_o; - wire wire_ni0Oi_o; - wire wire_ni0Ol_o; - wire wire_ni0OO_o; - wire wire_nii0i_o; - wire wire_nii0l_o; - wire wire_nii0O_o; - wire wire_nii1i_o; - wire wire_nii1l_o; - wire wire_nii1O_o; - wire wire_niiil_o; - wire wire_niiiO_o; - wire wire_niiOi_o; - wire wire_niiOl_o; - wire wire_niiOO_o; - wire wire_nil0i_o; - wire wire_nil0l_o; - wire wire_nil0O_o; - wire wire_nil1i_o; - wire wire_nil1l_o; - wire wire_nil1O_o; - wire wire_nilii_o; - wire wire_nilil_o; - wire wire_niliO_o; - wire wire_nilli_o; - wire wire_nilll_o; - wire wire_nillO_o; - wire wire_nilOi_o; - wire wire_nilOl_o; - wire wire_nilOO_o; - wire wire_niO0i_o; - wire wire_niO0l_o; - wire wire_niO1i_o; - wire wire_niO1l_o; - wire wire_niO1O_o; + wire wire_n0l0i_o; + wire wire_n0l0l_o; + wire wire_n0l0O_o; + wire wire_n0l1i_o; + wire wire_n0l1l_o; + wire wire_n0l1O_o; + wire wire_n0lii_o; + wire wire_n0lil_o; + wire wire_n0liO_o; + wire wire_n0lli_o; + wire wire_n0lll_o; + wire wire_n0llO_o; + wire wire_n0lOi_o; + wire wire_n0lOl_o; + wire wire_n0lOO_o; + wire wire_n0O0i_o; + wire wire_n0O0l_o; + wire wire_n0O1i_o; + wire wire_n0O1l_o; + wire wire_n0OiO_o; + wire wire_n0Oli_o; + wire wire_n0Oll_o; + wire wire_n0OlO_o; + wire wire_n0OOi_o; + wire wire_n0OOl_o; + wire wire_n0OOO_o; + wire wire_ni01i_o; + wire wire_ni10i_o; + wire wire_ni10l_o; + wire wire_ni10O_o; + wire wire_ni11i_o; + wire wire_ni11l_o; + wire wire_ni11O_o; + wire wire_ni1ii_o; + wire wire_ni1il_o; + wire wire_ni1iO_o; + wire wire_ni1li_o; + wire wire_ni1ll_o; + wire wire_ni1lO_o; + wire wire_ni1Oi_o; + wire wire_ni1Ol_o; + wire wire_ni1OO_o; + wire wire_nl0Ol_o; + wire wire_nl0OO_o; + wire wire_nli0i_o; + wire wire_nli0l_o; + wire wire_nli0O_o; + wire wire_nli1i_o; + wire wire_nli1l_o; + wire wire_nli1O_o; + wire wire_nliii_o; + wire wire_nliil_o; + wire wire_nliiO_o; + wire wire_nlili_o; + wire wire_nlill_o; + wire wire_nll0i_o; + wire wire_nll0l_o; + wire wire_nll0O_o; + wire wire_nllii_o; + wire wire_nllil_o; + wire wire_nlliO_o; + wire wire_nllli_o; + wire wire_nllll_o; + wire wire_nlllO_o; wire wire_nllOi_o; wire wire_nllOl_o; wire wire_nllOO_o; - wire wire_nlO0i_o; - wire wire_nlO0l_o; - wire wire_nlO0O_o; wire wire_nlO1i_o; - wire wire_nlO1l_o; - wire wire_nlO1O_o; - wire wire_nlOii_o; - wire wire_nlOil_o; - wire wire_nlOiO_o; - wire wire_nlOli_o; - wire wire_nlOlO_o; - wire wire_nlOOi_o; - wire wire_nlOOl_o; - wire wire_nlOOO_o; - wire nlOliO; - wire nlOlli; - wire nlOlll; - wire nlOllO; - wire nlOlOi; - wire nlOlOl; - wire nlOlOO; - wire nlOO0i; - wire nlOO0l; - wire nlOO0O; - wire nlOO1i; - wire nlOO1l; - wire nlOO1O; - wire nlOOii; - wire nlOOil; - wire nlOOiO; - wire nlOOli; + wire nli10i; + wire nli10l; + wire nli10O; + wire nli11O; + wire nli1ii; + wire nli1il; + wire nli1iO; + wire nli1li; + wire nli1ll; + wire nli1lO; + wire nli1Oi; + wire nli1Ol; initial begin - n000i = 0; - n000l = 0; - n000O = 0; - n001i = 0; - n001l = 0; - n001O = 0; - n00ii = 0; - n00il = 0; - n00iO = 0; - n00li = 0; - n00ll = 0; - n00lO = 0; - n00Oi = 0; - n00Ol = 0; - n00OO = 0; - n010i = 0; - n010l = 0; - n010O = 0; - n011i = 0; - n011l = 0; - n011O = 0; - n01ii = 0; - n01il = 0; - n01iO = 0; - n01li = 0; - n01ll = 0; - n01lO = 0; - n01Oi = 0; - n01Ol = 0; - n01OO = 0; - n0i1i = 0; - n0i1l = 0; + n00i = 0; + n00l = 0; + n00O = 0; + n01i = 0; + n01l = 0; + n01O = 0; n0ii = 0; n0il = 0; n0iO = 0; n0li = 0; - n0ll = 0; - n0lO = 0; - n0Oi = 0; - n0Ol = 0; + n0O1O = 0; + n0Oil = 0; n100i = 0; n100l = 0; n100O = 0; @@ -432,47 +605,281 @@ module ip_fp_add n1l1i = 0; n1l1l = 0; n1l1O = 0; + n1li = 0; n1lii = 0; n1lil = 0; n1liO = 0; + n1ll = 0; n1lli = 0; n1lll = 0; n1llO = 0; + n1lO = 0; n1lOi = 0; - n1lOl = 0; - n1lOO = 0; - n1O0i = 0; - n1O0l = 0; - n1O0O = 0; - n1O1i = 0; - n1O1l = 0; - n1O1O = 0; - n1Oii = 0; - n1Oil = 0; - n1OiO = 0; - n1Oli = 0; - n1Oll = 0; - n1OlO = 0; - n1OOi = 0; - n1OOl = 0; - n1OOO = 0; - ni1i = 0; - niiii = 0; - niilO = 0; - nl0OO = 0; - nli0i = 0; - nli0l = 0; - nli0O = 0; - nli1i = 0; - nli1l = 0; - nli1O = 0; - nliii = 0; - nliil = 0; - nliiO = 0; - nlili = 0; - nlill = 0; + n1Oi = 0; + n1Ol = 0; + n1OO = 0; + ni00i = 0; + ni00l = 0; + ni00O = 0; + ni01l = 0; + ni01O = 0; + ni0ii = 0; + ni0il = 0; + ni0li = 0; + ni0ll = 0; + ni0lO = 0; + ni0Oi = 0; + ni0Ol = 0; + nilO = 0; + nilOO = 0; + niO0i = 0; + niO0l = 0; + niO0O = 0; + niO1i = 0; + niO1l = 0; + niO1O = 0; + niOi = 0; + niOii = 0; + niOl = 0; + niOO = 0; + nl0i = 0; + nl0l = 0; + nl0O = 0; + nl10i = 0; + nl10l = 0; + nl10O = 0; + nl11i = 0; + nl11l = 0; + nl11O = 0; + nl1i = 0; + nl1ii = 0; + nl1il = 0; + nl1iO = 0; + nl1l = 0; + nl1li = 0; + nl1ll = 0; + nl1lO = 0; + nl1O = 0; + nl1Oi = 0; + nl1Ol = 0; + nli00i = 0; + nli00l = 0; + nli00O = 0; + nli01l = 0; + nli01O = 0; + nli0ii = 0; + nli0il = 0; + nli0iO = 0; + nli0li = 0; + nli0ll = 0; + nli0lO = 0; + nli0Oi = 0; + nli0Ol = 0; + nli0OO = 0; + nlii = 0; + nlii0i = 0; + nlii0l = 0; + nlii0O = 0; + nlii1i = 0; + nlii1l = 0; + nlii1O = 0; + nliiii = 0; + nliiil = 0; + nliiiO = 0; + nliili = 0; + nliill = 0; + nliilO = 0; + nliiOi = 0; + nliiOl = 0; + nliiOO = 0; + nlil = 0; + nlil0i = 0; + nlil0l = 0; + nlil0O = 0; + nlil1i = 0; + nlil1l = 0; + nlil1O = 0; + nlilii = 0; + nlilil = 0; + nliliO = 0; + nlilli = 0; + nlilll = 0; + nlillO = 0; nlilO = 0; + nlilOi = 0; + nlilOl = 0; + nlilOO = 0; + nliO = 0; + nliO0i = 0; + nliO0l = 0; + nliO0O = 0; + nliO1i = 0; + nliO1l = 0; + nliO1O = 0; nliOi = 0; + nliOii = 0; + nliOil = 0; + nliOiO = 0; + nliOl = 0; + nliOli = 0; + nliOll = 0; + nliOlO = 0; + nliOO = 0; + nliOOi = 0; + nliOOl = 0; + nliOOO = 0; + nll00i = 0; + nll00l = 0; + nll00O = 0; + nll01i = 0; + nll01l = 0; + nll01O = 0; + nll0ii = 0; + nll0il = 0; + nll0iO = 0; + nll0li = 0; + nll0ll = 0; + nll0lO = 0; + nll0Oi = 0; + nll0Ol = 0; + nll0OO = 0; + nll10i = 0; + nll10l = 0; + nll10O = 0; + nll11i = 0; + nll11l = 0; + nll11O = 0; + nll1i = 0; + nll1ii = 0; + nll1il = 0; + nll1iO = 0; + nll1l = 0; + nll1li = 0; + nll1ll = 0; + nll1lO = 0; + nll1Oi = 0; + nll1Ol = 0; + nll1OO = 0; + nlli = 0; + nlli0i = 0; + nlli0l = 0; + nlli0O = 0; + nlli1i = 0; + nlli1l = 0; + nlli1O = 0; + nlliii = 0; + nlliil = 0; + nlliiO = 0; + nllili = 0; + nllill = 0; + nllilO = 0; + nlliOi = 0; + nlliOl = 0; + nlliOO = 0; + nlll = 0; + nlll0i = 0; + nlll0l = 0; + nlll0O = 0; + nlll1i = 0; + nlll1l = 0; + nlll1O = 0; + nlllii = 0; + nlllil = 0; + nllliO = 0; + nlllli = 0; + nlllll = 0; + nllllO = 0; + nlllOi = 0; + nlllOl = 0; + nlllOO = 0; + nllO0i = 0; + nllO0l = 0; + nllO0O = 0; + nllO1i = 0; + nllO1l = 0; + nllO1O = 0; + nllOii = 0; + nllOil = 0; + nllOiO = 0; + nllOli = 0; + nllOll = 0; + nllOlO = 0; + nllOOi = 0; + nllOOl = 0; + nllOOO = 0; + nlO00i = 0; + nlO00l = 0; + nlO00O = 0; + nlO01i = 0; + nlO01l = 0; + nlO01O = 0; + nlO0ii = 0; + nlO0il = 0; + nlO0iO = 0; + nlO0li = 0; + nlO0ll = 0; + nlO0lO = 0; + nlO0Oi = 0; + nlO0Ol = 0; + nlO0OO = 0; + nlO10i = 0; + nlO10l = 0; + nlO10O = 0; + nlO11i = 0; + nlO11l = 0; + nlO11O = 0; + nlO1ii = 0; + nlO1il = 0; + nlO1iO = 0; + nlO1li = 0; + nlO1ll = 0; + nlO1lO = 0; + nlO1Oi = 0; + nlO1Ol = 0; + nlO1OO = 0; + nlOi = 0; + nlOi0i = 0; + nlOi0l = 0; + nlOi0O = 0; + nlOi1i = 0; + nlOi1l = 0; + nlOi1O = 0; + nlOiii = 0; + nlOiil = 0; + nlOiiO = 0; + nlOili = 0; + nlOill = 0; + nlOilO = 0; + nlOiOi = 0; + nlOiOl = 0; + nlOiOO = 0; + nlOl0i = 0; + nlOl0l = 0; + nlOl0O = 0; + nlOl1i = 0; + nlOl1l = 0; + nlOl1O = 0; + nlOlii = 0; + nlOlil = 0; + nlOliO = 0; + nlOlli = 0; + nlOlll = 0; + nlOllO = 0; + nlOlOi = 0; + nlOlOl = 0; + nlOlOO = 0; + nlOO0i = 0; + nlOO0l = 0; + nlOO0O = 0; + nlOO1i = 0; + nlOO1l = 0; + nlOO1O = 0; + nlOOii = 0; + nlOOil = 0; + nlOOiO = 0; + nlOOli = 0; + nlOOll = 0; + nlOOlO = 0; nlOOOi = 0; nlOOOl = 0; nlOOOO = 0; @@ -481,46 +888,18 @@ module ip_fp_add begin if (areset == 1'b1) begin - n000i <= 0; - n000l <= 0; - n000O <= 0; - n001i <= 0; - n001l <= 0; - n001O <= 0; - n00ii <= 0; - n00il <= 0; - n00iO <= 0; - n00li <= 0; - n00ll <= 0; - n00lO <= 0; - n00Oi <= 0; - n00Ol <= 0; - n00OO <= 0; - n010i <= 0; - n010l <= 0; - n010O <= 0; - n011i <= 0; - n011l <= 0; - n011O <= 0; - n01ii <= 0; - n01il <= 0; - n01iO <= 0; - n01li <= 0; - n01ll <= 0; - n01lO <= 0; - n01Oi <= 0; - n01Ol <= 0; - n01OO <= 0; - n0i1i <= 0; - n0i1l <= 0; + n00i <= 0; + n00l <= 0; + n00O <= 0; + n01i <= 0; + n01l <= 0; + n01O <= 0; n0ii <= 0; n0il <= 0; n0iO <= 0; n0li <= 0; - n0ll <= 0; - n0lO <= 0; - n0Oi <= 0; - n0Ol <= 0; + n0O1O <= 0; + n0Oil <= 0; n100i <= 0; n100l <= 0; n100O <= 0; @@ -572,330 +951,770 @@ module ip_fp_add n1l1i <= 0; n1l1l <= 0; n1l1O <= 0; + n1li <= 0; n1lii <= 0; n1lil <= 0; n1liO <= 0; + n1ll <= 0; n1lli <= 0; n1lll <= 0; n1llO <= 0; + n1lO <= 0; n1lOi <= 0; - n1lOl <= 0; - n1lOO <= 0; - n1O0i <= 0; - n1O0l <= 0; - n1O0O <= 0; - n1O1i <= 0; - n1O1l <= 0; - n1O1O <= 0; - n1Oii <= 0; - n1Oil <= 0; - n1OiO <= 0; - n1Oli <= 0; - n1Oll <= 0; - n1OlO <= 0; - n1OOi <= 0; - n1OOl <= 0; - n1OOO <= 0; - ni1i <= 0; - niiii <= 0; - niilO <= 0; - nl0OO <= 0; - nli0i <= 0; - nli0l <= 0; - nli0O <= 0; - nli1i <= 0; - nli1l <= 0; - nli1O <= 0; - nliii <= 0; - nliil <= 0; - nliiO <= 0; - nlili <= 0; - nlill <= 0; + n1Oi <= 0; + n1Ol <= 0; + n1OO <= 0; + ni00i <= 0; + ni00l <= 0; + ni00O <= 0; + ni01l <= 0; + ni01O <= 0; + ni0ii <= 0; + ni0il <= 0; + ni0li <= 0; + ni0ll <= 0; + ni0lO <= 0; + ni0Oi <= 0; + ni0Ol <= 0; + nilO <= 0; + nilOO <= 0; + niO0i <= 0; + niO0l <= 0; + niO0O <= 0; + niO1i <= 0; + niO1l <= 0; + niO1O <= 0; + niOi <= 0; + niOii <= 0; + niOl <= 0; + niOO <= 0; + nl0i <= 0; + nl0l <= 0; + nl0O <= 0; + nl10i <= 0; + nl10l <= 0; + nl10O <= 0; + nl11i <= 0; + nl11l <= 0; + nl11O <= 0; + nl1i <= 0; + nl1ii <= 0; + nl1il <= 0; + nl1iO <= 0; + nl1l <= 0; + nl1li <= 0; + nl1ll <= 0; + nl1lO <= 0; + nl1O <= 0; + nl1Oi <= 0; + nl1Ol <= 0; + nli00i <= 0; + nli00l <= 0; + nli00O <= 0; + nli01l <= 0; + nli01O <= 0; + nli0ii <= 0; + nli0il <= 0; + nli0iO <= 0; + nli0li <= 0; + nli0ll <= 0; + nli0lO <= 0; + nli0Oi <= 0; + nli0Ol <= 0; + nli0OO <= 0; + nlii <= 0; + nlii0i <= 0; + nlii0l <= 0; + nlii0O <= 0; + nlii1i <= 0; + nlii1l <= 0; + nlii1O <= 0; + nliiii <= 0; + nliiil <= 0; + nliiiO <= 0; + nliili <= 0; + nliill <= 0; + nliilO <= 0; + nliiOi <= 0; + nliiOl <= 0; + nliiOO <= 0; + nlil <= 0; + nlil0i <= 0; + nlil0l <= 0; + nlil0O <= 0; + nlil1i <= 0; + nlil1l <= 0; + nlil1O <= 0; + nlilii <= 0; + nlilil <= 0; + nliliO <= 0; + nlilli <= 0; + nlilll <= 0; + nlillO <= 0; nlilO <= 0; + nlilOi <= 0; + nlilOl <= 0; + nlilOO <= 0; + nliO <= 0; + nliO0i <= 0; + nliO0l <= 0; + nliO0O <= 0; + nliO1i <= 0; + nliO1l <= 0; + nliO1O <= 0; nliOi <= 0; + nliOii <= 0; + nliOil <= 0; + nliOiO <= 0; + nliOl <= 0; + nliOli <= 0; + nliOll <= 0; + nliOlO <= 0; + nliOO <= 0; + nliOOi <= 0; + nliOOl <= 0; + nliOOO <= 0; + nll00i <= 0; + nll00l <= 0; + nll00O <= 0; + nll01i <= 0; + nll01l <= 0; + nll01O <= 0; + nll0ii <= 0; + nll0il <= 0; + nll0iO <= 0; + nll0li <= 0; + nll0ll <= 0; + nll0lO <= 0; + nll0Oi <= 0; + nll0Ol <= 0; + nll0OO <= 0; + nll10i <= 0; + nll10l <= 0; + nll10O <= 0; + nll11i <= 0; + nll11l <= 0; + nll11O <= 0; + nll1i <= 0; + nll1ii <= 0; + nll1il <= 0; + nll1iO <= 0; + nll1l <= 0; + nll1li <= 0; + nll1ll <= 0; + nll1lO <= 0; + nll1Oi <= 0; + nll1Ol <= 0; + nll1OO <= 0; + nlli <= 0; + nlli0i <= 0; + nlli0l <= 0; + nlli0O <= 0; + nlli1i <= 0; + nlli1l <= 0; + nlli1O <= 0; + nlliii <= 0; + nlliil <= 0; + nlliiO <= 0; + nllili <= 0; + nllill <= 0; + nllilO <= 0; + nlliOi <= 0; + nlliOl <= 0; + nlliOO <= 0; + nlll <= 0; + nlll0i <= 0; + nlll0l <= 0; + nlll0O <= 0; + nlll1i <= 0; + nlll1l <= 0; + nlll1O <= 0; + nlllii <= 0; + nlllil <= 0; + nllliO <= 0; + nlllli <= 0; + nlllll <= 0; + nllllO <= 0; + nlllOi <= 0; + nlllOl <= 0; + nlllOO <= 0; + nllO0i <= 0; + nllO0l <= 0; + nllO0O <= 0; + nllO1i <= 0; + nllO1l <= 0; + nllO1O <= 0; + nllOii <= 0; + nllOil <= 0; + nllOiO <= 0; + nllOli <= 0; + nllOll <= 0; + nllOlO <= 0; + nllOOi <= 0; + nllOOl <= 0; + nllOOO <= 0; + nlO00i <= 0; + nlO00l <= 0; + nlO00O <= 0; + nlO01i <= 0; + nlO01l <= 0; + nlO01O <= 0; + nlO0ii <= 0; + nlO0il <= 0; + nlO0iO <= 0; + nlO0li <= 0; + nlO0ll <= 0; + nlO0lO <= 0; + nlO0Oi <= 0; + nlO0Ol <= 0; + nlO0OO <= 0; + nlO10i <= 0; + nlO10l <= 0; + nlO10O <= 0; + nlO11i <= 0; + nlO11l <= 0; + nlO11O <= 0; + nlO1ii <= 0; + nlO1il <= 0; + nlO1iO <= 0; + nlO1li <= 0; + nlO1ll <= 0; + nlO1lO <= 0; + nlO1Oi <= 0; + nlO1Ol <= 0; + nlO1OO <= 0; + nlOi <= 0; + nlOi0i <= 0; + nlOi0l <= 0; + nlOi0O <= 0; + nlOi1i <= 0; + nlOi1l <= 0; + nlOi1O <= 0; + nlOiii <= 0; + nlOiil <= 0; + nlOiiO <= 0; + nlOili <= 0; + nlOill <= 0; + nlOilO <= 0; + nlOiOi <= 0; + nlOiOl <= 0; + nlOiOO <= 0; + nlOl0i <= 0; + nlOl0l <= 0; + nlOl0O <= 0; + nlOl1i <= 0; + nlOl1l <= 0; + nlOl1O <= 0; + nlOlii <= 0; + nlOlil <= 0; + nlOliO <= 0; + nlOlli <= 0; + nlOlll <= 0; + nlOllO <= 0; + nlOlOi <= 0; + nlOlOl <= 0; + nlOlOO <= 0; + nlOO0i <= 0; + nlOO0l <= 0; + nlOO0O <= 0; + nlOO1i <= 0; + nlOO1l <= 0; + nlOO1O <= 0; + nlOOii <= 0; + nlOOil <= 0; + nlOOiO <= 0; + nlOOli <= 0; + nlOOll <= 0; + nlOOlO <= 0; nlOOOi <= 0; nlOOOl <= 0; nlOOOO <= 0; end - else if (wire_n0OO_ENA == 1'b1) + else if (wire_nllO_ENA == 1'b1) begin - n000i <= wire_nil1l_o; - n000l <= wire_nil1O_o; - n000O <= wire_nil0i_o; - n001i <= wire_niiOl_o; - n001l <= wire_niiOO_o; - n001O <= wire_nil1i_o; - n00ii <= wire_nil0l_o; - n00il <= wire_nil0O_o; - n00iO <= wire_nilii_o; - n00li <= wire_niO0O_o[1]; - n00ll <= wire_niO0O_o[2]; - n00lO <= wire_niO0O_o[3]; - n00Oi <= wire_niO0O_o[4]; - n00Ol <= wire_niO0O_o[5]; - n00OO <= wire_niO0O_o[6]; - n010i <= wire_nl0Ol_o[2]; - n010l <= wire_nl0Ol_o[3]; - n010O <= wire_nl0Ol_o[4]; - n011i <= wire_nl0Ol_o[4]; - n011l <= wire_nl0Ol_o[0]; - n011O <= wire_nl0Ol_o[1]; - n01ii <= wire_nl0Ol_o[5]; - n01il <= wire_nl0Ol_o[6]; - n01iO <= wire_nl0Ol_o[7]; - n01li <= wire_nl0Ol_o[8]; - n01ll <= wire_nl0Ol_o[9]; - n01lO <= wire_nl0Ol_o[10]; - n01Oi <= wire_nl0Ol_o[11]; - n01Ol <= wire_nl0Ol_o[12]; - n01OO <= wire_niiOi_o; - n0i1i <= wire_niO0O_o[7]; - n0i1l <= nlOlOl; - n0ii <= wire_ni1O_dataout; - n0il <= wire_ni0i_dataout; - n0iO <= wire_ni0l_dataout; - n0li <= wire_ni0O_dataout; - n0ll <= wire_niii_dataout; - n0lO <= wire_niil_dataout; - n0Oi <= wire_niiO_dataout; - n0Ol <= wire_nili_dataout; - n100i <= n10Ol; - n100l <= wire_niOi_dataout; - n100O <= wire_niOl_dataout; - n101i <= n10ll; - n101l <= n10lO; - n101O <= n10Oi; - n10ii <= wire_niOO_dataout; - n10il <= wire_nl1i_dataout; - n10iO <= wire_nl1l_dataout; - n10li <= wire_nl1O_dataout; - n10ll <= wire_nl0i_dataout; - n10lO <= wire_nl0l_dataout; - n10Oi <= wire_nl0O_dataout; - n10Ol <= wire_nlii_dataout; - n10OO <= nlOOil; - n110i <= wire_ni_dataout; - n110l <= wire_nlil_dataout; - n110O <= wire_nliO_dataout; - n111i <= wire_nli_dataout; - n111l <= wire_nll_dataout; - n111O <= wire_nlO_dataout; - n11ii <= wire_nlli_dataout; - n11il <= wire_nlll_dataout; - n11iO <= wire_nllO_dataout; - n11li <= n100l; - n11ll <= n100O; - n11lO <= n10ii; - n11Oi <= n10il; - n11Ol <= n10iO; - n11OO <= n10li; - n1i0i <= wire_nl0iO_dataout; - n1i0l <= wire_nl0ll_dataout; - n1i0O <= wire_nl0lO_dataout; - n1i1i <= ((((~ wire_nl0Oi_dataout) & (~ wire_nl0lO_dataout)) & (~ wire_nl0ll_dataout)) & (~ wire_nl0li_dataout)); - n1i1l <= wire_nl0ii_dataout; - n1i1O <= wire_nl0il_dataout; - n1iii <= wire_nl0Oi_dataout; - n1iil <= n1iiO; - n1iiO <= n1ili; - n1ili <= wire_nlOi_dataout; - n1ill <= nlOlll; - n1ilO <= n1ill; - n1iOi <= n1iOl; - n1iOl <= (~ nlOOOl); - n1iOO <= n1l0l; - n1l0i <= n1liO; - n1l0l <= n110l; - n1l0O <= n110O; - n1l1i <= n1l0O; - n1l1l <= n1lii; - n1l1O <= n1lil; - n1lii <= n11ii; - n1lil <= n11il; - n1liO <= n11iO; - n1lli <= n1lll; - n1lll <= n1llO; - n1llO <= wire_nl_dataout; - n1lOi <= n1lOl; - n1lOl <= nlOOOl; - n1lOO <= nlOlli; - n1O0i <= ((((nlOO0O & nlOO1O) & n1iil) & (~ nlOllO)) | (((((nlOO0i & n1lOi) & n1iil) & n1lli) | ((nlOO1O & n1lOi) & n1iil)) | ((nlOO1l & n1lli) | (nlOO1i & n1iil)))); - n1O0l <= (n1ilO & (~ n1O1i)); - n1O0O <= (nlOO0l & (~ n1O1O)); - n1O1i <= n1O1l; - n1O1l <= n1lOO; - n1O1O <= nlOliO; - n1Oii <= n1Oil; - n1Oil <= n1OiO; - n1OiO <= nlOOOi; - n1Oli <= nlOO1l; - n1Oll <= nlOO1i; - n1OlO <= wire_nl0Ol_o[0]; - n1OOi <= wire_nl0Ol_o[1]; - n1OOl <= wire_nl0Ol_o[2]; - n1OOO <= wire_nl0Ol_o[3]; - ni1i <= wire_nill_dataout; - niiii <= wire_nliOl_dataout; - niilO <= wire_niiil_o; - nl0OO <= wire_nliOO_dataout; - nli0i <= wire_nll0i_dataout; - nli0l <= wire_nll0l_dataout; - nli0O <= wire_nll0O_dataout; - nli1i <= wire_nll1i_dataout; - nli1l <= wire_nll1l_dataout; - nli1O <= wire_nll1O_dataout; - nliii <= wire_nllii_dataout; - nliil <= wire_nllil_dataout; - nliiO <= wire_nlliO_dataout; - nlili <= wire_nllli_dataout; - nlill <= wire_nllll_dataout; - nlilO <= wire_n1li_o[13]; - nliOi <= wire_ni1l_dataout; - nlOOOi <= (wire_nl_dataout ^ wire_nlOi_dataout); - nlOOOl <= nlOOli; - nlOOOO <= wire_niO_dataout; + n00i <= wire_ni0O_dataout; + n00l <= wire_niii_dataout; + n00O <= wire_niil_dataout; + n01i <= wire_ni1O_dataout; + n01l <= wire_ni0i_dataout; + n01O <= wire_ni0l_dataout; + n0ii <= wire_niiO_dataout; + n0il <= wire_nili_dataout; + n0iO <= wire_nill_dataout; + n0li <= wire_nlOl_dataout; + n0O1O <= wire_ni0iO_o[1]; + n0Oil <= wire_n0O0i_o; + n100i <= nlll1l; + n100l <= nlll1O; + n100O <= nlll0i; + n101i <= nlliOl; + n101l <= nlliOO; + n101O <= nlll1i; + n10ii <= nlll0l; + n10il <= nlll0O; + n10iO <= nlllii; + n10li <= nlllil; + n10ll <= nllliO; + n10lO <= nlllli; + n10Oi <= wire_n0OiO_o; + n10Ol <= wire_n0Oli_o; + n10OO <= wire_n0Oll_o; + n110i <= n101l; + n110l <= n101O; + n110O <= n100i; + n111i <= nlll1l; + n111l <= n11OO; + n111O <= n101i; + n11ii <= n100l; + n11il <= n100O; + n11iO <= n10ii; + n11li <= n10il; + n11ll <= n10iO; + n11lO <= n10li; + n11Oi <= n10ll; + n11Ol <= n10lO; + n11OO <= nlliOi; + n1i0i <= wire_n0OOO_o; + n1i0l <= wire_ni11i_o; + n1i0O <= wire_ni11l_o; + n1i1i <= wire_n0OlO_o; + n1i1l <= wire_n0OOi_o; + n1i1O <= wire_n0OOl_o; + n1iii <= wire_ni11O_o; + n1iil <= n0O1O; + n1iiO <= ni01l; + n1ili <= ni01O; + n1ill <= ni00i; + n1ilO <= ni00l; + n1iOi <= nlOlOO; + n1iOl <= nlOlll; + n1iOO <= nlOlii; + n1l0i <= n10Oi; + n1l0l <= n10Ol; + n1l0O <= n10OO; + n1l1i <= nlOlOl; + n1l1l <= nlOlOi; + n1l1O <= (nli1iO & nli11O); + n1li <= wire_n0lO_dataout; + n1lii <= n1i1i; + n1lil <= n1i1l; + n1liO <= n1i1O; + n1ll <= wire_n0Oi_dataout; + n1lli <= n1i0i; + n1lll <= n1i0l; + n1llO <= n1i0O; + n1lO <= wire_n0Ol_dataout; + n1lOi <= n1iii; + n1Oi <= wire_n0OO_dataout; + n1Ol <= wire_ni1i_dataout; + n1OO <= wire_ni1l_dataout; + ni00i <= wire_ni0iO_o[4]; + ni00l <= wire_ni0iO_o[5]; + ni00O <= wire_ni0iO_o[6]; + ni01l <= wire_ni0iO_o[2]; + ni01O <= wire_ni0iO_o[3]; + ni0ii <= wire_ni0iO_o[7]; + ni0il <= wire_ni0OO_o[0]; + ni0li <= wire_ni0OO_o[1]; + ni0ll <= wire_ni0OO_o[2]; + ni0lO <= wire_ni0OO_o[3]; + ni0Oi <= wire_ni0OO_o[4]; + ni0Ol <= wire_ni0OO_o[5]; + nilO <= wire_nlOO_dataout; + nilOO <= wire_niOil_dataout; + niO0i <= wire_niOlO_dataout; + niO0l <= wire_niOOi_dataout; + niO0O <= wire_niOOl_dataout; + niO1i <= wire_niOiO_dataout; + niO1l <= wire_niOli_dataout; + niO1O <= wire_niOll_dataout; + niOi <= wire_n1i_dataout; + niOii <= wire_nl1OO_dataout; + niOl <= wire_n1l_dataout; + niOO <= wire_n1O_dataout; + nl0i <= wire_nii_dataout; + nl0l <= wire_nil_dataout; + nl0O <= wire_niO_dataout; + nl10i <= wire_nl00i_dataout; + nl10l <= wire_nl00l_dataout; + nl10O <= wire_nl00O_dataout; + nl11i <= wire_nl01i_dataout; + nl11l <= wire_nl01l_dataout; + nl11O <= wire_nl01O_dataout; + nl1i <= wire_n0i_dataout; + nl1ii <= wire_nl0ii_dataout; + nl1il <= wire_nl0il_dataout; + nl1iO <= wire_nl0iO_dataout; + nl1l <= wire_n0l_dataout; + nl1li <= wire_nl0li_dataout; + nl1ll <= wire_nl0ll_dataout; + nl1lO <= wire_nl0lO_dataout; + nl1O <= wire_n0O_dataout; + nl1Oi <= nll11l; + nl1Ol <= wire_nll1O_o[1]; + nli00i <= b[11]; + nli00l <= b[12]; + nli00O <= b[13]; + nli01l <= b[15]; + nli01O <= b[10]; + nli0ii <= b[14]; + nli0il <= b[0]; + nli0iO <= b[1]; + nli0li <= b[2]; + nli0ll <= b[3]; + nli0lO <= b[4]; + nli0Oi <= b[5]; + nli0Ol <= b[6]; + nli0OO <= b[7]; + nlii <= wire_nli_dataout; + nlii0i <= a[1]; + nlii0l <= a[2]; + nlii0O <= a[3]; + nlii1i <= b[8]; + nlii1l <= b[9]; + nlii1O <= a[0]; + nliiii <= a[4]; + nliiil <= a[5]; + nliiiO <= a[6]; + nliili <= a[7]; + nliill <= a[8]; + nliilO <= a[9]; + nliiOi <= a[10]; + nliiOl <= a[11]; + nliiOO <= a[12]; + nlil <= wire_nll_dataout; + nlil0i <= nli1Oi; + nlil0l <= nli1Oi; + nlil0O <= nli1Oi; + nlil1i <= a[13]; + nlil1l <= a[14]; + nlil1O <= a[15]; + nlilii <= (nli1Oi ^ wire_nlOOl_dataout); + nlilil <= (nli1Oi ^ wire_nlOOO_dataout); + nliliO <= (nli1Oi ^ wire_n11i_dataout); + nlilli <= (nli1Oi ^ wire_n11l_dataout); + nlilll <= (nli1Oi ^ wire_n11O_dataout); + nlillO <= (nli1Oi ^ wire_n10i_dataout); + nlilO <= wire_nll1O_o[2]; + nlilOi <= (nli1Oi ^ wire_n10l_dataout); + nlilOl <= (nli1Oi ^ wire_n10O_dataout); + nlilOO <= (nli1Oi ^ wire_n1ii_dataout); + nliO <= wire_nlO_dataout; + nliO0i <= wire_nlO1l_o[0]; + nliO0l <= wire_nlO1l_o[1]; + nliO0O <= wire_nlO1l_o[2]; + nliO1i <= (nli1Oi ^ wire_n1il_dataout); + nliO1l <= (nli1Oi ^ (~ nli1lO)); + nliO1O <= nli1Oi; + nliOi <= wire_nll1O_o[3]; + nliOii <= wire_nlO1l_o[3]; + nliOil <= wire_nlO1l_o[4]; + nliOiO <= wire_nlO1l_o[5]; + nliOl <= wire_nll1O_o[4]; + nliOli <= wire_nlO1l_o[6]; + nliOll <= wire_nlO1l_o[7]; + nliOlO <= wire_nlO1l_o[8]; + nliOO <= wire_nll1O_o[5]; + nliOOi <= wire_nlO1l_o[9]; + nliOOl <= wire_nlO1l_o[10]; + nliOOO <= wire_nlO1l_o[11]; + nll00i <= nll0Ol; + nll00l <= nll0OO; + nll00O <= nlli1i; + nll01i <= nll0ll; + nll01l <= nll0lO; + nll01O <= nll0Oi; + nll0ii <= nlli1l; + nll0il <= nlli1O; + nll0iO <= nlli0i; + nll0li <= nlli0l; + nll0ll <= nlli0O; + nll0lO <= nlliii; + nll0Oi <= nlliil; + nll0Ol <= nlliiO; + nll0OO <= nllili; + nll10i <= nlii; + nll10l <= nlil; + nll10O <= nliO; + nll11i <= wire_nlO1l_o[12]; + nll11l <= wire_nlO1l_o[13]; + nll11O <= nl0O; + nll1i <= wire_nll1O_o[6]; + nll1ii <= nlli; + nll1il <= n00i; + nll1iO <= n00l; + nll1l <= wire_n0ll_dataout; + nll1li <= n00O; + nll1ll <= n0ii; + nll1lO <= n0il; + nll1Oi <= nll0il; + nll1Ol <= nll0iO; + nll1OO <= nll0li; + nlli <= wire_ni_dataout; + nlli0i <= n1li; + nlli0l <= n1ll; + nlli0O <= n1lO; + nlli1i <= nllill; + nlli1l <= nllilO; + nlli1O <= nll1l; + nlliii <= n1Oi; + nlliil <= n1Ol; + nlliiO <= n1OO; + nllili <= n01i; + nllill <= n01l; + nllilO <= n01O; + nlliOi <= wire_niOOO_o[0]; + nlliOl <= wire_niOOO_o[1]; + nlliOO <= wire_niOOO_o[2]; + nlll <= wire_nl_dataout; + nlll0i <= wire_niOOO_o[6]; + nlll0l <= wire_niOOO_o[7]; + nlll0O <= wire_niOOO_o[8]; + nlll1i <= wire_niOOO_o[3]; + nlll1l <= wire_niOOO_o[4]; + nlll1O <= wire_niOOO_o[5]; + nlllii <= wire_niOOO_o[9]; + nlllil <= wire_niOOO_o[10]; + nllliO <= wire_niOOO_o[11]; + nlllli <= wire_niOOO_o[12]; + nlllll <= wire_niOOO_o[13]; + nllllO <= nlllOi; + nlllOi <= nli1ll; + nlllOl <= nli1li; + nlllOO <= ((~ wire_nilOl_dataout) & (~ wire_nilOi_dataout)); + nllO0i <= nllO0l; + nllO0l <= nllO0O; + nllO0O <= nllOii; + nllO1i <= wire_nillO_dataout; + nllO1l <= wire_nilOl_dataout; + nllO1O <= (((wire_nilll_dataout & nllllO) & nlllOl) & nlllOO); + nllOii <= nllOil; + nllOil <= nllOiO; + nllOiO <= nllOli; + nllOli <= n0iO; + nllOll <= nli1il; + nllOlO <= nllOOi; + nllOOi <= nllOOl; + nllOOl <= nllOOO; + nllOOO <= nllOll; + nlO00i <= nlO0iO; + nlO00l <= nlO0li; + nlO00O <= nlO0ll; + nlO01i <= nlO00O; + nlO01l <= nlO0ii; + nlO01O <= nlO0il; + nlO0ii <= nlO0lO; + nlO0il <= nll1il; + nlO0iO <= nll1iO; + nlO0li <= nll1li; + nlO0ll <= nll1ll; + nlO0lO <= nll1lO; + nlO0Oi <= nli1ii; + nlO0Ol <= nli10O; + nlO0OO <= ((~ nlO0Oi) & (~ nlO0Ol)); + nlO10i <= nlO10l; + nlO10l <= nlO10O; + nlO10O <= (~ nli1lO); + nlO11i <= nlO11l; + nlO11l <= nlO11O; + nlO11O <= nlO10i; + nlO1ii <= ((~ nllOlO) & nlO11i); + nlO1il <= nlO1Oi; + nlO1iO <= nlO1Ol; + nlO1li <= nlO1OO; + nlO1ll <= nlO01i; + nlO1lO <= nlO01l; + nlO1Oi <= nlO01O; + nlO1Ol <= nlO00i; + nlO1OO <= nlO00l; + nlOi <= wire_nO_o[17]; + nlOi0i <= nlOi0l; + nlOi0l <= nlOi0O; + nlOi0O <= nlOiii; + nlOi1i <= nlOi1l; + nlOi1l <= nlOi1O; + nlOi1O <= nlOi0i; + nlOiii <= nlll; + nlOiil <= nlOiiO; + nlOiiO <= nlOili; + nlOili <= nlOill; + nlOill <= nlOilO; + nlOilO <= nlOiOi; + nlOiOi <= nlOiOl; + nlOiOl <= nli1lO; + nlOiOO <= nlO0Ol; + nlOl0i <= nlOl0l; + nlOl0l <= nlOl0O; + nlOl0O <= nlOl1i; + nlOl1i <= nli10l; + nlOl1l <= nlOl1O; + nlOl1O <= nlOl0i; + nlOlii <= (nllOlO & nlOl1l); + nlOlil <= nli10i; + nlOliO <= nlOlli; + nlOlli <= nlOlil; + nlOlll <= (nlO0Oi & nlOliO); + nlOllO <= ((((nlO1ii & nlO0OO) & nllO0i) & (~ nllO1O)) | (((((nlOiil & nlOiOO) & nllO0i) & nlOi1i) | ((nlO0OO & nlOiil) & nllO0i)) | ((nlOi1i & nlOlii) | (nllO0i & nlOlll)))); + nlOlOi <= (nllOlO & (~ nlOl1l)); + nlOlOl <= (nlO0Oi & (~ nlOliO)); + nlOlOO <= nlOO1i; + nlOO0i <= nlOO0l; + nlOO0l <= nlil0i; + nlOO0O <= ((nlOlOi | nlOlOl) | ((nlOlii & nlOlll) & nlOlOO)); + nlOO1i <= nlOO1l; + nlOO1l <= nlOO1O; + nlOO1O <= nlOO0i; + nlOOii <= nlOOlO; + nlOOil <= nlOOOi; + nlOOiO <= nlOOOl; + nlOOli <= nlOOOO; + nlOOll <= n111i; + nlOOlO <= nlliOi; + nlOOOi <= nlliOl; + nlOOOl <= nlliOO; + nlOOOO <= nlll1i; end end assign - wire_n0OO_ENA = en[0]; - assign wire_n0i_dataout = (wire_nO_o[17] === 1'b1) ? a[5] : b[5]; - assign wire_n0l_dataout = (wire_nO_o[17] === 1'b1) ? a[6] : b[6]; - assign wire_n0O_dataout = (wire_nO_o[17] === 1'b1) ? a[7] : b[7]; - assign wire_n1i_dataout = (wire_nO_o[17] === 1'b1) ? a[2] : b[2]; - assign wire_n1l_dataout = (wire_nO_o[17] === 1'b1) ? a[3] : b[3]; - assign wire_n1O_dataout = (wire_nO_o[17] === 1'b1) ? a[4] : b[4]; - assign wire_ni_dataout = (wire_nO_o[17] === 1'b1) ? a[14] : b[14]; - and(wire_ni0i_dataout, wire_n1i_dataout, (~ nlOOli)); - and(wire_ni0l_dataout, wire_n1l_dataout, (~ nlOOli)); - and(wire_ni0O_dataout, wire_n1O_dataout, (~ nlOOli)); - and(wire_ni1l_dataout, wire_nlOl_dataout, (~ nlOOli)); - and(wire_ni1O_dataout, wire_nlOO_dataout, (~ nlOOli)); - assign wire_nii_dataout = (wire_nO_o[17] === 1'b1) ? a[8] : b[8]; - and(wire_niii_dataout, wire_n0i_dataout, (~ nlOOli)); - and(wire_niil_dataout, wire_n0l_dataout, (~ nlOOli)); - and(wire_niiO_dataout, wire_n0O_dataout, (~ nlOOli)); - assign wire_nil_dataout = (wire_nO_o[17] === 1'b1) ? a[9] : b[9]; - and(wire_nili_dataout, wire_nii_dataout, (~ nlOOli)); - and(wire_nill_dataout, wire_nil_dataout, (~ nlOOli)); - assign wire_niO_dataout = (wire_nO_o[17] === 1'b1) ? a[10] : b[10]; - assign wire_niOi_dataout = (wire_nO_o[17] === 1'b1) ? b[0] : a[0]; - assign wire_niOl_dataout = (wire_nO_o[17] === 1'b1) ? b[1] : a[1]; - assign wire_niOO_dataout = (wire_nO_o[17] === 1'b1) ? b[2] : a[2]; - assign wire_nl_dataout = (wire_nO_o[17] === 1'b1) ? a[15] : b[15]; - assign wire_nl00i_dataout = ((~ n1i1i) === 1'b1) ? n1i0l : n1i1l; - assign wire_nl00l_dataout = ((~ n1i1i) === 1'b1) ? n1i0O : n1i1O; - assign wire_nl00O_dataout = ((~ n1i1i) === 1'b1) ? n1iii : n1i0i; - assign wire_nl01O_dataout = ((~ nlOOii) === 1'b1) ? wire_nl00O_dataout : wire_nl00i_dataout; - assign wire_nl0i_dataout = (wire_nO_o[17] === 1'b1) ? b[6] : a[6]; - or(wire_nl0ii_dataout, wire_nl0Ol_o[7], ~((~ nlOOil))); - assign wire_nl0il_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[8] : wire_nl0Ol_o[0]; - assign wire_nl0iO_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[9] : wire_nl0Ol_o[1]; - assign wire_nl0l_dataout = (wire_nO_o[17] === 1'b1) ? b[7] : a[7]; - assign wire_nl0li_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[10] : wire_nl0Ol_o[2]; - assign wire_nl0ll_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[11] : wire_nl0Ol_o[3]; - assign wire_nl0lO_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[12] : wire_nl0Ol_o[4]; - assign wire_nl0O_dataout = (wire_nO_o[17] === 1'b1) ? b[8] : a[8]; - assign wire_nl0Oi_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[13] : wire_nl0Ol_o[5]; - assign wire_nl1i_dataout = (wire_nO_o[17] === 1'b1) ? b[3] : a[3]; - assign wire_nl1l_dataout = (wire_nO_o[17] === 1'b1) ? b[4] : a[4]; - assign wire_nl1O_dataout = (wire_nO_o[17] === 1'b1) ? b[5] : a[5]; - assign wire_nli_dataout = (wire_nO_o[17] === 1'b1) ? a[11] : b[11]; - assign wire_nlii_dataout = (wire_nO_o[17] === 1'b1) ? b[9] : a[9]; - assign wire_nlil_dataout = (wire_nO_o[17] === 1'b1) ? b[10] : a[10]; - assign wire_nliO_dataout = (wire_nO_o[17] === 1'b1) ? b[11] : a[11]; - assign wire_nliOl_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOi_o : wire_n1li_o[13]; - assign wire_nliOO_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOl_o : wire_n1li_o[13]; - assign wire_nll_dataout = (wire_nO_o[17] === 1'b1) ? a[12] : b[12]; - assign wire_nll0i_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1O_o : wire_n1li_o[13]; - assign wire_nll0l_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0i_o : wire_n1li_o[13]; - assign wire_nll0O_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0l_o : wire_n1li_o[13]; - assign wire_nll1i_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOO_o : wire_n1li_o[13]; - assign wire_nll1l_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1i_o : wire_n1li_o[13]; - assign wire_nll1O_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1l_o : wire_n1li_o[13]; - assign wire_nlli_dataout = (wire_nO_o[17] === 1'b1) ? b[12] : a[12]; - assign wire_nllii_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0O_o : wire_n1li_o[13]; - assign wire_nllil_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOii_o : wire_n1li_o[13]; - assign wire_nlliO_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOil_o : wire_n1li_o[13]; - assign wire_nlll_dataout = (wire_nO_o[17] === 1'b1) ? b[13] : a[13]; - assign wire_nllli_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOiO_o : wire_n1li_o[13]; - assign wire_nllll_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOli_o : wire_n1li_o[13]; - assign wire_nllO_dataout = (wire_nO_o[17] === 1'b1) ? b[14] : a[14]; - assign wire_nlO_dataout = (wire_nO_o[17] === 1'b1) ? a[13] : b[13]; - assign wire_nlOi_dataout = (wire_nO_o[17] === 1'b1) ? b[15] : a[15]; - assign wire_nlOl_dataout = (wire_nO_o[17] === 1'b1) ? a[0] : b[0]; - assign wire_nlOO_dataout = (wire_nO_o[17] === 1'b1) ? a[1] : b[1]; - oper_add n1li - ( - .a({1'b0, nlOOOi, (nlOOOi ^ (~ nlOOOl)), (ni1i ^ nlOOOi), (n0Ol ^ nlOOOi), (n0Oi ^ nlOOOi), (n0lO ^ nlOOOi), (n0ll ^ nlOOOi), (n0li ^ nlOOOi), (n0iO ^ nlOOOi), (n0il ^ nlOOOi), (n0ii ^ nlOOOi), (nliOi ^ nlOOOi), {2{nlOOOi}}}), - .b({{14{1'b0}}, nlOOOi}), + wire_nllO_ENA = en[0]; + assign wire_n0i_dataout = (nlOi === 1'b1) ? nliiil : nli0Oi; + assign wire_n0l_dataout = (nlOi === 1'b1) ? nliiiO : nli0Ol; + assign wire_n0ll_dataout = (nlOi === 1'b1) ? nli0il : nlii1O; + assign wire_n0lO_dataout = (nlOi === 1'b1) ? nli0iO : nlii0i; + assign wire_n0O_dataout = (nlOi === 1'b1) ? nliili : nli0OO; + assign wire_n0Oi_dataout = (nlOi === 1'b1) ? nli0li : nlii0l; + assign wire_n0Ol_dataout = (nlOi === 1'b1) ? nli0ll : nlii0O; + assign wire_n0OO_dataout = (nlOi === 1'b1) ? nli0lO : nliiii; + and(wire_n10i_dataout, nl1i, (~ nli1lO)); + and(wire_n10l_dataout, nl1l, (~ nli1lO)); + and(wire_n10O_dataout, nl1O, (~ nli1lO)); + and(wire_n11i_dataout, niOi, (~ nli1lO)); + and(wire_n11l_dataout, niOl, (~ nli1lO)); + and(wire_n11O_dataout, niOO, (~ nli1lO)); + assign wire_n1i_dataout = (nlOi === 1'b1) ? nlii0l : nli0li; + and(wire_n1ii_dataout, nl0i, (~ nli1lO)); + and(wire_n1il_dataout, nl0l, (~ nli1lO)); + assign wire_n1l_dataout = (nlOi === 1'b1) ? nlii0O : nli0ll; + assign wire_n1O_dataout = (nlOi === 1'b1) ? nliiii : nli0lO; + assign wire_ni_dataout = (nlOi === 1'b1) ? nlil1l : nli0ii; + assign wire_ni0i_dataout = (nlOi === 1'b1) ? nlii1i : nliill; + assign wire_ni0l_dataout = (nlOi === 1'b1) ? nlii1l : nliilO; + assign wire_ni0O_dataout = (nlOi === 1'b1) ? nli01O : nliiOi; + assign wire_ni1i_dataout = (nlOi === 1'b1) ? nli0Oi : nliiil; + assign wire_ni1l_dataout = (nlOi === 1'b1) ? nli0Ol : nliiiO; + assign wire_ni1O_dataout = (nlOi === 1'b1) ? nli0OO : nliili; + assign wire_nii_dataout = (nlOi === 1'b1) ? nliill : nlii1i; + assign wire_niii_dataout = (nlOi === 1'b1) ? nli00i : nliiOl; + assign wire_niil_dataout = (nlOi === 1'b1) ? nli00l : nliiOO; + assign wire_niiO_dataout = (nlOi === 1'b1) ? nli00O : nlil1i; + assign wire_nil_dataout = (nlOi === 1'b1) ? nliilO : nlii1l; + assign wire_nili_dataout = (nlOi === 1'b1) ? nli0ii : nlil1l; + assign wire_nill_dataout = (nlOi === 1'b1) ? nli01l : nlil1O; + assign wire_nilll_dataout = ((~ nlllOO) === 1'b1) ? nllO1l : nllO1i; + assign wire_nillO_dataout = ((~ nli1li) === 1'b1) ? niO0i : nilOO; + assign wire_nilOi_dataout = ((~ nli1li) === 1'b1) ? niO0l : niO1i; + assign wire_nilOl_dataout = ((~ nli1li) === 1'b1) ? niO0O : niO1l; + assign wire_niO_dataout = (nlOi === 1'b1) ? nliiOi : nli01O; + or(wire_niOil_dataout, nlll0l, ~((~ nli1ll))); + assign wire_niOiO_dataout = ((~ nli1ll) === 1'b1) ? nlll0O : nlliOi; + assign wire_niOli_dataout = ((~ nli1ll) === 1'b1) ? nlllii : nlliOl; + assign wire_niOll_dataout = ((~ nli1ll) === 1'b1) ? nlllil : nlliOO; + assign wire_niOlO_dataout = ((~ nli1ll) === 1'b1) ? nllliO : nlll1i; + assign wire_niOOi_dataout = ((~ nli1ll) === 1'b1) ? nlllli : nlll1l; + assign wire_niOOl_dataout = ((~ nli1ll) === 1'b1) ? nlllll : nlll1O; + assign wire_nl_dataout = (nlOi === 1'b1) ? nlil1O : nli01l; + assign wire_nl00i_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nli1O_o : nll11l; + assign wire_nl00l_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nli0i_o : nll11l; + assign wire_nl00O_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nli0l_o : nll11l; + assign wire_nl01i_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nl0OO_o : nll11l; + assign wire_nl01l_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nli1i_o : nll11l; + assign wire_nl01O_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nli1l_o : nll11l; + assign wire_nl0ii_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nli0O_o : nll11l; + assign wire_nl0il_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nliii_o : nll11l; + assign wire_nl0iO_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nliil_o : nll11l; + assign wire_nl0li_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nliiO_o : nll11l; + assign wire_nl0ll_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nlili_o : nll11l; + assign wire_nl0lO_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nlill_o : nll11l; + assign wire_nl1OO_dataout = (wire_nl0Oi_o[8] === 1'b1) ? wire_nl0Ol_o : nll11l; + assign wire_nli_dataout = (nlOi === 1'b1) ? nliiOl : nli00i; + assign wire_nll_dataout = (nlOi === 1'b1) ? nliiOO : nli00l; + assign wire_nlO_dataout = (nlOi === 1'b1) ? nlil1i : nli00O; + assign wire_nlOl_dataout = (nlOi === 1'b1) ? nlii1O : nli0il; + assign wire_nlOO_dataout = (nlOi === 1'b1) ? nlii0i : nli0iO; + and(wire_nlOOl_dataout, n0li, (~ nli1lO)); + and(wire_nlOOO_dataout, nilO, (~ nli1lO)); + oper_add ni0iO + ( + .a({1'b0, ni0Ol, ni0Oi, ni0lO, ni0ll, ni0li, ni0il, 1'b1}), + .b({{3{1'b1}}, (~ nllllO), (~ nlllOl), (~ nlllOO), wire_nilll_dataout, 1'b1}), .cin(1'b0), .cout(), - .o(wire_n1li_o)); + .o(wire_ni0iO_o)); defparam - n1li.sgate_representation = 0, - n1li.width_a = 15, - n1li.width_b = 15, - n1li.width_o = 15; - oper_add niO0O + ni0iO.sgate_representation = 0, + ni0iO.width_a = 8, + ni0iO.width_b = 8, + ni0iO.width_o = 8; + oper_add ni0OO ( - .a({1'b0, wire_niOii_o[5:0], 1'b1}), - .b({{3{1'b1}}, (~ n10OO), (~ n1i1i), (~ nlOOii), wire_nl01O_dataout, 1'b1}), + .a({1'b0, nlO1lO, nlO1ll, nlO1li, nlO1iO, nlO1il}), + .b({{5{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_niO0O_o)); + .o(wire_ni0OO_o)); defparam - niO0O.sgate_representation = 0, - niO0O.width_a = 8, - niO0O.width_b = 8, - niO0O.width_o = 8; - oper_add niOii + ni0OO.sgate_representation = 0, + ni0OO.width_a = 6, + ni0OO.width_b = 6, + ni0OO.width_o = 6; + oper_add niOOO ( - .a({1'b0, n1l0i, n1l1O, n1l1l, n1l1i, n1iOO}), - .b({{5{1'b0}}, 1'b1}), + .a({{2{1'b0}}, 1'b1, nll0ii, nll00O, nll00l, nll00i, nll01O, nll01l, nll01i, nll1OO, nll1Ol, nll1Oi, {2{1'b0}}}), + .b({{2{nl1Oi}}, nl1lO, nl1ll, nl1li, nl1iO, nl1il, nl1ii, nl10O, nl10l, nl10i, nl11O, nl11l, nl11i, niOii}), .cin(1'b0), .cout(), - .o(wire_niOii_o)); + .o(wire_niOOO_o)); defparam - niOii.sgate_representation = 0, - niOii.width_a = 6, - niOii.width_b = 6, - niOii.width_o = 6; - oper_add nl0Ol + niOOO.sgate_representation = 0, + niOOO.width_a = 15, + niOOO.width_b = 15, + niOOO.width_o = 15; + oper_add nl0Oi ( - .a({{2{1'b0}}, 1'b1, n100i, n101O, n101l, n101i, n11OO, n11Ol, n11Oi, n11lO, n11ll, n11li, {2{1'b0}}}), - .b({{2{nlilO}}, nlill, nlili, nliiO, nliil, nliii, nli0O, nli0l, nli0i, nli1O, nli1l, nli1i, nl0OO, niiii}), + .a({{2{1'b0}}, nll1i, nliOO, nliOl, nliOi, nlilO, nl1Ol, 1'b1}), + .b({{4{1'b1}}, {3{1'b0}}, {2{1'b1}}}), .cin(1'b0), .cout(), - .o(wire_nl0Ol_o)); + .o(wire_nl0Oi_o)); defparam - nl0Ol.sgate_representation = 0, - nl0Ol.width_a = 15, - nl0Ol.width_b = 15, - nl0Ol.width_o = 15; - oper_add nlllO + nl0Oi.sgate_representation = 0, + nl0Oi.width_a = 9, + nl0Oi.width_b = 9, + nl0Oi.width_o = 9; + oper_add nll1O ( - .a({{2{1'b0}}, wire_nlOll_o[6:1], 1'b1}), - .b({{4{1'b1}}, {3{1'b0}}, {2{1'b1}}}), + .a({1'b0, nll1lO, nll1ll, nll1li, nll1iO, nll1il, 1'b1}), + .b({1'b1, (~ nll1ii), (~ nll10O), (~ nll10l), (~ nll10i), (~ nll11O), 1'b1}), .cin(1'b0), .cout(), - .o(wire_nlllO_o)); + .o(wire_nll1O_o)); defparam - nlllO.sgate_representation = 0, - nlllO.width_a = 9, - nlllO.width_b = 9, - nlllO.width_o = 9; - oper_add nlOll + nll1O.sgate_representation = 0, + nll1O.width_a = 7, + nll1O.width_b = 7, + nll1O.width_o = 7; + oper_add nlO1l ( - .a({1'b0, n11iO, n11il, n11ii, n110O, n110l, 1'b1}), - .b({1'b1, (~ n110i), (~ n111O), (~ n111l), (~ n111i), (~ nlOOOO), 1'b1}), + .a({1'b0, nliO1O, nliO1l, nliO1i, nlilOO, nlilOl, nlilOi, nlillO, nlilll, nlilli, nliliO, nlilil, nlilii, nlil0O, nlil0l}), + .b({{14{1'b0}}, nlil0i}), .cin(1'b0), .cout(), - .o(wire_nlOll_o)); + .o(wire_nlO1l_o)); defparam - nlOll.sgate_representation = 0, - nlOll.width_a = 7, - nlOll.width_b = 7, - nlOll.width_o = 7; + nlO1l.sgate_representation = 0, + nlO1l.width_a = 15, + nlO1l.width_b = 15, + nlO1l.width_o = 15; oper_add nO ( .a({{2{1'b0}}, a[14:0], 1'b1}), @@ -908,569 +1727,564 @@ module ip_fp_add nO.width_a = 18, nO.width_b = 18, nO.width_o = 18; - oper_mux n10i + oper_mux n0l0i ( - .data({{2{wire_n1li_o[13]}}, wire_n1li_o[11], wire_n1li_o[7]}), - .o(wire_n10i_o), - .sel({wire_nlOll_o[4:3]})); + .data({{2{1'b0}}, n1lii, 1'b0}), + .o(wire_n0l0i_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n10i.width_data = 4, - n10i.width_sel = 2; - oper_mux n10l + n0l0i.width_data = 4, + n0l0i.width_sel = 2; + oper_mux n0l0l ( - .data({wire_n1li_o[13], wire_n1li_o[13:12], wire_n1li_o[8]}), - .o(wire_n10l_o), - .sel({wire_nlOll_o[4:3]})); + .data({{2{1'b0}}, n1lil, 1'b0}), + .o(wire_n0l0l_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n10l.width_data = 4, - n10l.width_sel = 2; - oper_mux n10O + n0l0l.width_data = 4, + n0l0l.width_sel = 2; + oper_mux n0l0O ( - .data({{3{wire_n1li_o[13]}}, wire_n1li_o[9]}), - .o(wire_n10O_o), - .sel({wire_nlOll_o[4:3]})); + .data({{2{1'b0}}, n1liO, 1'b0}), + .o(wire_n0l0O_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n10O.width_data = 4, - n10O.width_sel = 2; - oper_mux n11i + n0l0O.width_data = 4, + n0l0O.width_sel = 2; + oper_mux n0l1i ( - .data({wire_n1li_o[13:12], wire_n1li_o[8], wire_n1li_o[4]}), - .o(wire_n11i_o), - .sel({wire_nlOll_o[4:3]})); + .data({1'b1, 1'b0, n1l0i, 1'b0}), + .o(wire_n0l1i_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n11i.width_data = 4, - n11i.width_sel = 2; - oper_mux n11l + n0l1i.width_data = 4, + n0l1i.width_sel = 2; + oper_mux n0l1l ( - .data({{2{wire_n1li_o[13]}}, wire_n1li_o[9], wire_n1li_o[5]}), - .o(wire_n11l_o), - .sel({wire_nlOll_o[4:3]})); + .data({{2{1'b0}}, n1l0l, 1'b0}), + .o(wire_n0l1l_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n11l.width_data = 4, - n11l.width_sel = 2; - oper_mux n11O + n0l1l.width_data = 4, + n0l1l.width_sel = 2; + oper_mux n0l1O ( - .data({{2{wire_n1li_o[13]}}, wire_n1li_o[10], wire_n1li_o[6]}), - .o(wire_n11O_o), - .sel({wire_nlOll_o[4:3]})); + .data({{2{1'b0}}, n1l0O, 1'b0}), + .o(wire_n0l1O_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n11O.width_data = 4, - n11O.width_sel = 2; - oper_mux n1ii + n0l1O.width_data = 4, + n0l1O.width_sel = 2; + oper_mux n0lii ( - .data({{3{wire_n1li_o[13]}}, wire_n1li_o[10]}), - .o(wire_n1ii_o), - .sel({wire_nlOll_o[4:3]})); + .data({{2{1'b0}}, n1lli, 1'b0}), + .o(wire_n0lii_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n1ii.width_data = 4, - n1ii.width_sel = 2; - oper_mux n1il + n0lii.width_data = 4, + n0lii.width_sel = 2; + oper_mux n0lil ( - .data({{3{wire_n1li_o[13]}}, wire_n1li_o[11]}), - .o(wire_n1il_o), - .sel({wire_nlOll_o[4:3]})); + .data({{2{1'b0}}, n1lll, 1'b0}), + .o(wire_n0lil_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n1il.width_data = 4, - n1il.width_sel = 2; - oper_mux n1iO + n0lil.width_data = 4, + n0lil.width_sel = 2; + oper_mux n0liO ( - .data({{2{wire_n1li_o[13]}}, wire_n1li_o[13:12]}), - .o(wire_n1iO_o), - .sel({wire_nlOll_o[4:3]})); + .data({{2{1'b0}}, n1llO, 1'b0}), + .o(wire_n0liO_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - n1iO.width_data = 4, - n1iO.width_sel = 2; - oper_mux ni00l + n0liO.width_data = 4, + n0liO.width_sel = 2; + oper_mux n0lli ( - .data({1'b1, 1'b0, n01OO, 1'b0}), - .o(wire_ni00l_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{2{1'b0}}, n1lOi, 1'b0}), + .o(wire_n0lli_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - ni00l.width_data = 4, - ni00l.width_sel = 2; - oper_mux ni00O + n0lli.width_data = 4, + n0lli.width_sel = 2; + oper_mux n0lll ( - .data({{2{1'b0}}, n001i, 1'b0}), - .o(wire_ni00O_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{2{1'b1}}, n1iil, 1'b0}), + .o(wire_n0lll_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - ni00O.width_data = 4, - ni00O.width_sel = 2; - oper_mux ni0ii + n0lll.width_data = 4, + n0lll.width_sel = 2; + oper_mux n0llO ( - .data({{2{1'b0}}, n001l, 1'b0}), - .o(wire_ni0ii_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{2{1'b1}}, n1iiO, 1'b0}), + .o(wire_n0llO_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - ni0ii.width_data = 4, - ni0ii.width_sel = 2; - oper_mux ni0il + n0llO.width_data = 4, + n0llO.width_sel = 2; + oper_mux n0lOi ( - .data({{2{1'b0}}, n001O, 1'b0}), - .o(wire_ni0il_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{2{1'b1}}, n1ili, 1'b0}), + .o(wire_n0lOi_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - ni0il.width_data = 4, - ni0il.width_sel = 2; - oper_mux ni0iO + n0lOi.width_data = 4, + n0lOi.width_sel = 2; + oper_mux n0lOl ( - .data({{2{1'b0}}, n000i, 1'b0}), - .o(wire_ni0iO_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{2{1'b1}}, n1ill, 1'b0}), + .o(wire_n0lOl_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - ni0iO.width_data = 4, - ni0iO.width_sel = 2; - oper_mux ni0li + n0lOl.width_data = 4, + n0lOl.width_sel = 2; + oper_mux n0lOO ( - .data({{2{1'b0}}, n000l, 1'b0}), - .o(wire_ni0li_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{2{1'b1}}, n1ilO, 1'b0}), + .o(wire_n0lOO_o), + .sel({wire_n0O1l_o, wire_n0O1i_o})); defparam - ni0li.width_data = 4, - ni0li.width_sel = 2; - oper_mux ni0ll + n0lOO.width_data = 4, + n0lOO.width_sel = 2; + oper_mux n0O0i ( - .data({{2{1'b0}}, n000O, 1'b0}), - .o(wire_ni0ll_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{3{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {7{1'b0}}, 1'b1, {3{1'b0}}}), + .o(wire_n0O0i_o), + .sel({nllO1O, ni0ii, nli1iO, nlOiil, nlOiOO})); defparam - ni0ll.width_data = 4, - ni0ll.width_sel = 2; - oper_mux ni0lO + n0O0i.width_data = 32, + n0O0i.width_sel = 5; + oper_mux n0O0l ( - .data({{2{1'b0}}, n00ii, 1'b0}), - .o(wire_ni0lO_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{31{1'b0}}, 1'b1, {25{1'b0}}, {5{1'b1}}, {2{1'b0}}}), + .o(wire_n0O0l_o), + .sel({n1l1O, n1l1l, n1l1i, n1iOO, n1iOl, n1iOi})); defparam - ni0lO.width_data = 4, - ni0lO.width_sel = 2; - oper_mux ni0Oi + n0O0l.width_data = 64, + n0O0l.width_sel = 6; + oper_mux n0O1i ( - .data({{2{1'b0}}, n00il, 1'b0}), - .o(wire_ni0Oi_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{4{1'b1}}, {3{1'b0}}, 1'b1}), + .o(wire_n0O1i_o), + .sel({nlOO0O, wire_n0O0l_o, n0Oil})); defparam - ni0Oi.width_data = 4, - ni0Oi.width_sel = 2; - oper_mux ni0Ol + n0O1i.width_data = 8, + n0O1i.width_sel = 3; + oper_mux n0O1l ( - .data({{2{1'b0}}, n00iO, 1'b0}), - .o(wire_ni0Ol_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({{3{1'b1}}, 1'b0}), + .o(wire_n0O1l_o), + .sel({nlOO0O, wire_n0O0l_o})); defparam - ni0Ol.width_data = 4, - ni0Ol.width_sel = 2; - oper_mux ni0OO + n0O1l.width_data = 4, + n0O1l.width_sel = 2; + oper_mux n0OiO ( - .data({{2{1'b1}}, n00li, 1'b0}), - .o(wire_ni0OO_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({wire_ni10l_o, wire_ni10i_o, wire_ni1ii_o, wire_ni10O_o}), + .o(wire_n0OiO_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - ni0OO.width_data = 4, - ni0OO.width_sel = 2; - oper_mux nii0i + n0OiO.width_data = 4, + n0OiO.width_sel = 2; + oper_mux n0Oli ( - .data({{2{1'b1}}, n00Ol, 1'b0}), - .o(wire_nii0i_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({wire_ni10O_o, wire_ni10l_o, wire_ni1il_o, wire_ni1ii_o}), + .o(wire_n0Oli_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - nii0i.width_data = 4, - nii0i.width_sel = 2; - oper_mux nii0l + n0Oli.width_data = 4, + n0Oli.width_sel = 2; + oper_mux n0Oll ( - .data({{4{1'b1}}, {3{1'b0}}, 1'b1}), - .o(wire_nii0l_o), - .sel({nlOlOO, wire_niiiO_o, niilO})); + .data({wire_ni1ii_o, wire_ni10O_o, wire_ni1iO_o, wire_ni1il_o}), + .o(wire_n0Oll_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - nii0l.width_data = 8, - nii0l.width_sel = 3; - oper_mux nii0O + n0Oll.width_data = 4, + n0Oll.width_sel = 2; + oper_mux n0OlO ( - .data({{3{1'b1}}, 1'b0}), - .o(wire_nii0O_o), - .sel({nlOlOO, wire_niiiO_o})); + .data({wire_ni1il_o, wire_ni1ii_o, wire_ni1li_o, wire_ni1iO_o}), + .o(wire_n0OlO_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - nii0O.width_data = 4, - nii0O.width_sel = 2; - oper_mux nii1i + n0OlO.width_data = 4, + n0OlO.width_sel = 2; + oper_mux n0OOi ( - .data({{2{1'b1}}, n00ll, 1'b0}), - .o(wire_nii1i_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({wire_ni1iO_o, wire_ni1il_o, wire_ni1ll_o, wire_ni1li_o}), + .o(wire_n0OOi_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - nii1i.width_data = 4, - nii1i.width_sel = 2; - oper_mux nii1l + n0OOi.width_data = 4, + n0OOi.width_sel = 2; + oper_mux n0OOl ( - .data({{2{1'b1}}, n00lO, 1'b0}), - .o(wire_nii1l_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({wire_ni1li_o, wire_ni1iO_o, wire_ni1lO_o, wire_ni1ll_o}), + .o(wire_n0OOl_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - nii1l.width_data = 4, - nii1l.width_sel = 2; - oper_mux nii1O + n0OOl.width_data = 4, + n0OOl.width_sel = 2; + oper_mux n0OOO ( - .data({{2{1'b1}}, n00Oi, 1'b0}), - .o(wire_nii1O_o), - .sel({wire_nii0O_o, wire_nii0l_o})); + .data({wire_ni1ll_o, wire_ni1li_o, wire_ni1Oi_o, wire_ni1lO_o}), + .o(wire_n0OOO_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - nii1O.width_data = 4, - nii1O.width_sel = 2; - oper_mux niiil + n0OOO.width_data = 4, + n0OOO.width_sel = 2; + oper_mux ni01i ( - .data({{3{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {7{1'b0}}, 1'b1, {3{1'b0}}}), - .o(wire_niiil_o), - .sel({nlOllO, wire_niO0O_o[7], nlOlOl, n1lOi, nlOO0i})); + .data({n111l, nlOOll, n11li, n11Ol}), + .o(wire_ni01i_o), + .sel({nllllO, nlllOl})); defparam - niiil.width_data = 32, - niiil.width_sel = 5; - oper_mux niiiO + ni01i.width_data = 4, + ni01i.width_sel = 2; + oper_mux ni10i ( - .data({{31{1'b0}}, 1'b1, {25{1'b0}}, {5{1'b1}}, {2{1'b0}}}), - .o(wire_niiiO_o), - .sel({(nlOlOi & n0i1l), n1O0l, n1O0O, n1Oli, n1Oll, n1Oii})); + .data({{3{1'b0}}, n111l}), + .o(wire_ni10i_o), + .sel({nllllO, nlllOl})); defparam - niiiO.width_data = 64, - niiiO.width_sel = 6; - oper_mux niiOi + ni10i.width_data = 4, + ni10i.width_sel = 2; + oper_mux ni10l ( - .data({wire_niliO_o, wire_nilil_o, wire_nilll_o, wire_nilli_o}), - .o(wire_niiOi_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({{3{1'b0}}, n111O}), + .o(wire_ni10l_o), + .sel({nllllO, nlllOl})); defparam - niiOi.width_data = 4, - niiOi.width_sel = 2; - oper_mux niiOl + ni10l.width_data = 4, + ni10l.width_sel = 2; + oper_mux ni10O ( - .data({wire_nilli_o, wire_niliO_o, wire_nillO_o, wire_nilll_o}), - .o(wire_niiOl_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({{3{1'b0}}, n110i}), + .o(wire_ni10O_o), + .sel({nllllO, nlllOl})); defparam - niiOl.width_data = 4, - niiOl.width_sel = 2; - oper_mux niiOO + ni10O.width_data = 4, + ni10O.width_sel = 2; + oper_mux ni11i ( - .data({wire_nilll_o, wire_nilli_o, wire_nilOi_o, wire_nillO_o}), - .o(wire_niiOO_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({wire_ni1lO_o, wire_ni1ll_o, wire_ni1Ol_o, wire_ni1Oi_o}), + .o(wire_ni11i_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - niiOO.width_data = 4, - niiOO.width_sel = 2; - oper_mux nil0i + ni11i.width_data = 4, + ni11i.width_sel = 2; + oper_mux ni11l ( - .data({wire_nilOO_o, wire_nilOl_o, wire_niO1l_o, wire_niO1i_o}), - .o(wire_nil0i_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({wire_ni1Oi_o, wire_ni1lO_o, wire_ni1OO_o, wire_ni1Ol_o}), + .o(wire_ni11l_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - nil0i.width_data = 4, - nil0i.width_sel = 2; - oper_mux nil0l + ni11l.width_data = 4, + ni11l.width_sel = 2; + oper_mux ni11O ( - .data({wire_niO1i_o, wire_nilOO_o, wire_niO1O_o, wire_niO1l_o}), - .o(wire_nil0l_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({wire_ni1Ol_o, wire_ni1Oi_o, wire_ni01i_o, wire_ni1OO_o}), + .o(wire_ni11O_o), + .sel({nlllOO, wire_nilll_dataout})); defparam - nil0l.width_data = 4, - nil0l.width_sel = 2; - oper_mux nil0O + ni11O.width_data = 4, + ni11O.width_sel = 2; + oper_mux ni1ii ( - .data({wire_niO1l_o, wire_niO1i_o, wire_niO0i_o, wire_niO1O_o}), - .o(wire_nil0O_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({{3{1'b0}}, n110l}), + .o(wire_ni1ii_o), + .sel({nllllO, nlllOl})); defparam - nil0O.width_data = 4, - nil0O.width_sel = 2; - oper_mux nil1i + ni1ii.width_data = 4, + ni1ii.width_sel = 2; + oper_mux ni1il ( - .data({wire_nillO_o, wire_nilll_o, wire_nilOl_o, wire_nilOi_o}), - .o(wire_nil1i_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({{2{1'b0}}, n111l, n110O}), + .o(wire_ni1il_o), + .sel({nllllO, nlllOl})); defparam - nil1i.width_data = 4, - nil1i.width_sel = 2; - oper_mux nil1l + ni1il.width_data = 4, + ni1il.width_sel = 2; + oper_mux ni1iO ( - .data({wire_nilOi_o, wire_nillO_o, wire_nilOO_o, wire_nilOl_o}), - .o(wire_nil1l_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({{2{1'b0}}, n111O, n11ii}), + .o(wire_ni1iO_o), + .sel({nllllO, nlllOl})); defparam - nil1l.width_data = 4, - nil1l.width_sel = 2; - oper_mux nil1O + ni1iO.width_data = 4, + ni1iO.width_sel = 2; + oper_mux ni1li ( - .data({wire_nilOl_o, wire_nilOi_o, wire_niO1i_o, wire_nilOO_o}), - .o(wire_nil1O_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({{2{1'b0}}, n110i, n11il}), + .o(wire_ni1li_o), + .sel({nllllO, nlllOl})); defparam - nil1O.width_data = 4, - nil1O.width_sel = 2; - oper_mux nilii + ni1li.width_data = 4, + ni1li.width_sel = 2; + oper_mux ni1ll ( - .data({wire_niO1O_o, wire_niO1l_o, wire_niO0l_o, wire_niO0i_o}), - .o(wire_nilii_o), - .sel({nlOOii, wire_nl01O_dataout})); + .data({{2{1'b0}}, n110l, n11iO}), + .o(wire_ni1ll_o), + .sel({nllllO, nlllOl})); defparam - nilii.width_data = 4, - nilii.width_sel = 2; - oper_mux nilil + ni1ll.width_data = 4, + ni1ll.width_sel = 2; + oper_mux ni1lO ( - .data({{3{1'b0}}, n011l}), - .o(wire_nilil_o), - .sel({n10OO, n1i1i})); + .data({1'b0, nlOOii, n110O, n11li}), + .o(wire_ni1lO_o), + .sel({nllllO, nlllOl})); defparam - nilil.width_data = 4, - nilil.width_sel = 2; - oper_mux niliO + ni1lO.width_data = 4, + ni1lO.width_sel = 2; + oper_mux ni1Oi ( - .data({{3{1'b0}}, n011O}), - .o(wire_niliO_o), - .sel({n10OO, n1i1i})); + .data({1'b0, nlOOil, n11ii, n11ll}), + .o(wire_ni1Oi_o), + .sel({nllllO, nlllOl})); defparam - niliO.width_data = 4, - niliO.width_sel = 2; - oper_mux nilli + ni1Oi.width_data = 4, + ni1Oi.width_sel = 2; + oper_mux ni1Ol ( - .data({{3{1'b0}}, n010i}), - .o(wire_nilli_o), - .sel({n10OO, n1i1i})); + .data({1'b0, nlOOiO, n11il, n11lO}), + .o(wire_ni1Ol_o), + .sel({nllllO, nlllOl})); defparam - nilli.width_data = 4, - nilli.width_sel = 2; - oper_mux nilll + ni1Ol.width_data = 4, + ni1Ol.width_sel = 2; + oper_mux ni1OO ( - .data({{3{1'b0}}, n010l}), - .o(wire_nilll_o), - .sel({n10OO, n1i1i})); + .data({1'b0, nlOOli, n11iO, n11Oi}), + .o(wire_ni1OO_o), + .sel({nllllO, nlllOl})); defparam - nilll.width_data = 4, - nilll.width_sel = 2; - oper_mux nillO + ni1OO.width_data = 4, + ni1OO.width_sel = 2; + oper_mux nl0Ol ( - .data({{2{1'b0}}, n011l, n010O}), - .o(wire_nillO_o), - .sel({n10OO, n1i1i})); + .data({wire_nllii_o, wire_nll0O_o, wire_nll0l_o, wire_nll0i_o}), + .o(wire_nl0Ol_o), + .sel({nlilO, nl1Ol})); defparam - nillO.width_data = 4, - nillO.width_sel = 2; - oper_mux nilOi + nl0Ol.width_data = 4, + nl0Ol.width_sel = 2; + oper_mux nl0OO ( - .data({{2{1'b0}}, n011O, n01ii}), - .o(wire_nilOi_o), - .sel({n10OO, n1i1i})); + .data({wire_nllil_o, wire_nllii_o, wire_nll0O_o, wire_nll0l_o}), + .o(wire_nl0OO_o), + .sel({nlilO, nl1Ol})); defparam - nilOi.width_data = 4, - nilOi.width_sel = 2; - oper_mux nilOl + nl0OO.width_data = 4, + nl0OO.width_sel = 2; + oper_mux nli0i ( - .data({{2{1'b0}}, n010i, n01il}), - .o(wire_nilOl_o), - .sel({n10OO, n1i1i})); + .data({wire_nlllO_o, wire_nllll_o, wire_nllli_o, wire_nlliO_o}), + .o(wire_nli0i_o), + .sel({nlilO, nl1Ol})); defparam - nilOl.width_data = 4, - nilOl.width_sel = 2; - oper_mux nilOO + nli0i.width_data = 4, + nli0i.width_sel = 2; + oper_mux nli0l ( - .data({{2{1'b0}}, n010l, n01iO}), - .o(wire_nilOO_o), - .sel({n10OO, n1i1i})); + .data({wire_nllOi_o, wire_nlllO_o, wire_nllll_o, wire_nllli_o}), + .o(wire_nli0l_o), + .sel({nlilO, nl1Ol})); defparam - nilOO.width_data = 4, - nilOO.width_sel = 2; - oper_mux niO0i + nli0l.width_data = 4, + nli0l.width_sel = 2; + oper_mux nli0O ( - .data({1'b0, n1OOO, n01iO, n01Oi}), - .o(wire_niO0i_o), - .sel({n10OO, n1i1i})); + .data({wire_nllOl_o, wire_nllOi_o, wire_nlllO_o, wire_nllll_o}), + .o(wire_nli0O_o), + .sel({nlilO, nl1Ol})); defparam - niO0i.width_data = 4, - niO0i.width_sel = 2; - oper_mux niO0l + nli0O.width_data = 4, + nli0O.width_sel = 2; + oper_mux nli1i ( - .data({n011l, n011i, n01li, n01Ol}), - .o(wire_niO0l_o), - .sel({n10OO, n1i1i})); + .data({wire_nlliO_o, wire_nllil_o, wire_nllii_o, wire_nll0O_o}), + .o(wire_nli1i_o), + .sel({nlilO, nl1Ol})); defparam - niO0l.width_data = 4, - niO0l.width_sel = 2; - oper_mux niO1i + nli1i.width_data = 4, + nli1i.width_sel = 2; + oper_mux nli1l ( - .data({1'b0, n1OlO, n010O, n01li}), - .o(wire_niO1i_o), - .sel({n10OO, n1i1i})); + .data({wire_nllli_o, wire_nlliO_o, wire_nllil_o, wire_nllii_o}), + .o(wire_nli1l_o), + .sel({nlilO, nl1Ol})); defparam - niO1i.width_data = 4, - niO1i.width_sel = 2; - oper_mux niO1l + nli1l.width_data = 4, + nli1l.width_sel = 2; + oper_mux nli1O ( - .data({1'b0, n1OOi, n01ii, n01ll}), - .o(wire_niO1l_o), - .sel({n10OO, n1i1i})); + .data({wire_nllll_o, wire_nllli_o, wire_nlliO_o, wire_nllil_o}), + .o(wire_nli1O_o), + .sel({nlilO, nl1Ol})); defparam - niO1l.width_data = 4, - niO1l.width_sel = 2; - oper_mux niO1O + nli1O.width_data = 4, + nli1O.width_sel = 2; + oper_mux nliii ( - .data({1'b0, n1OOl, n01il, n01lO}), - .o(wire_niO1O_o), - .sel({n10OO, n1i1i})); + .data({wire_nllOO_o, wire_nllOl_o, wire_nllOi_o, wire_nlllO_o}), + .o(wire_nliii_o), + .sel({nlilO, nl1Ol})); defparam - niO1O.width_data = 4, - niO1O.width_sel = 2; - oper_mux nllOi + nliii.width_data = 4, + nliii.width_sel = 2; + oper_mux nliil ( - .data({wire_nlOOO_o, wire_nlOOl_o, wire_nlOOi_o, wire_nlOlO_o}), - .o(wire_nllOi_o), - .sel({wire_nlOll_o[2:1]})); + .data({wire_nlO1i_o, wire_nllOO_o, wire_nllOl_o, wire_nllOi_o}), + .o(wire_nliil_o), + .sel({nlilO, nl1Ol})); defparam - nllOi.width_data = 4, - nllOi.width_sel = 2; - oper_mux nllOl + nliil.width_data = 4, + nliil.width_sel = 2; + oper_mux nliiO ( - .data({wire_n11i_o, wire_nlOOO_o, wire_nlOOl_o, wire_nlOOi_o}), - .o(wire_nllOl_o), - .sel({wire_nlOll_o[2:1]})); + .data({nll11l, wire_nlO1i_o, wire_nllOO_o, wire_nllOl_o}), + .o(wire_nliiO_o), + .sel({nlilO, nl1Ol})); defparam - nllOl.width_data = 4, - nllOl.width_sel = 2; - oper_mux nllOO + nliiO.width_data = 4, + nliiO.width_sel = 2; + oper_mux nlili ( - .data({wire_n11l_o, wire_n11i_o, wire_nlOOO_o, wire_nlOOl_o}), - .o(wire_nllOO_o), - .sel({wire_nlOll_o[2:1]})); + .data({{2{nll11l}}, wire_nlO1i_o, wire_nllOO_o}), + .o(wire_nlili_o), + .sel({nlilO, nl1Ol})); defparam - nllOO.width_data = 4, - nllOO.width_sel = 2; - oper_mux nlO0i + nlili.width_data = 4, + nlili.width_sel = 2; + oper_mux nlill ( - .data({wire_n10O_o, wire_n10l_o, wire_n10i_o, wire_n11O_o}), - .o(wire_nlO0i_o), - .sel({wire_nlOll_o[2:1]})); + .data({{3{nll11l}}, wire_nlO1i_o}), + .o(wire_nlill_o), + .sel({nlilO, nl1Ol})); defparam - nlO0i.width_data = 4, - nlO0i.width_sel = 2; - oper_mux nlO0l + nlill.width_data = 4, + nlill.width_sel = 2; + oper_mux nll0i ( - .data({wire_n1ii_o, wire_n10O_o, wire_n10l_o, wire_n10i_o}), - .o(wire_nlO0l_o), - .sel({wire_nlOll_o[2:1]})); + .data({nll11i, nliOlO, nliOil, nliO0i}), + .o(wire_nll0i_o), + .sel({nliOl, nliOi})); defparam - nlO0l.width_data = 4, - nlO0l.width_sel = 2; - oper_mux nlO0O + nll0i.width_data = 4, + nll0i.width_sel = 2; + oper_mux nll0l ( - .data({wire_n1il_o, wire_n1ii_o, wire_n10O_o, wire_n10l_o}), - .o(wire_nlO0O_o), - .sel({wire_nlOll_o[2:1]})); + .data({nll11l, nliOOi, nliOiO, nliO0l}), + .o(wire_nll0l_o), + .sel({nliOl, nliOi})); defparam - nlO0O.width_data = 4, - nlO0O.width_sel = 2; - oper_mux nlO1i + nll0l.width_data = 4, + nll0l.width_sel = 2; + oper_mux nll0O ( - .data({wire_n11O_o, wire_n11l_o, wire_n11i_o, wire_nlOOO_o}), - .o(wire_nlO1i_o), - .sel({wire_nlOll_o[2:1]})); + .data({nll11l, nliOOl, nliOli, nliO0O}), + .o(wire_nll0O_o), + .sel({nliOl, nliOi})); defparam - nlO1i.width_data = 4, - nlO1i.width_sel = 2; - oper_mux nlO1l + nll0O.width_data = 4, + nll0O.width_sel = 2; + oper_mux nllii ( - .data({wire_n10i_o, wire_n11O_o, wire_n11l_o, wire_n11i_o}), - .o(wire_nlO1l_o), - .sel({wire_nlOll_o[2:1]})); + .data({nll11l, nliOOO, nliOll, nliOii}), + .o(wire_nllii_o), + .sel({nliOl, nliOi})); defparam - nlO1l.width_data = 4, - nlO1l.width_sel = 2; - oper_mux nlO1O + nllii.width_data = 4, + nllii.width_sel = 2; + oper_mux nllil ( - .data({wire_n10l_o, wire_n10i_o, wire_n11O_o, wire_n11l_o}), - .o(wire_nlO1O_o), - .sel({wire_nlOll_o[2:1]})); + .data({nll11l, nll11i, nliOlO, nliOil}), + .o(wire_nllil_o), + .sel({nliOl, nliOi})); defparam - nlO1O.width_data = 4, - nlO1O.width_sel = 2; - oper_mux nlOii + nllil.width_data = 4, + nllil.width_sel = 2; + oper_mux nlliO ( - .data({wire_n1iO_o, wire_n1il_o, wire_n1ii_o, wire_n10O_o}), - .o(wire_nlOii_o), - .sel({wire_nlOll_o[2:1]})); + .data({{2{nll11l}}, nliOOi, nliOiO}), + .o(wire_nlliO_o), + .sel({nliOl, nliOi})); defparam - nlOii.width_data = 4, - nlOii.width_sel = 2; - oper_mux nlOil + nlliO.width_data = 4, + nlliO.width_sel = 2; + oper_mux nllli ( - .data({wire_n1li_o[13], wire_n1iO_o, wire_n1il_o, wire_n1ii_o}), - .o(wire_nlOil_o), - .sel({wire_nlOll_o[2:1]})); + .data({{2{nll11l}}, nliOOl, nliOli}), + .o(wire_nllli_o), + .sel({nliOl, nliOi})); defparam - nlOil.width_data = 4, - nlOil.width_sel = 2; - oper_mux nlOiO + nllli.width_data = 4, + nllli.width_sel = 2; + oper_mux nllll ( - .data({{2{wire_n1li_o[13]}}, wire_n1iO_o, wire_n1il_o}), - .o(wire_nlOiO_o), - .sel({wire_nlOll_o[2:1]})); + .data({{2{nll11l}}, nliOOO, nliOll}), + .o(wire_nllll_o), + .sel({nliOl, nliOi})); defparam - nlOiO.width_data = 4, - nlOiO.width_sel = 2; - oper_mux nlOli + nllll.width_data = 4, + nllll.width_sel = 2; + oper_mux nlllO ( - .data({{3{wire_n1li_o[13]}}, wire_n1iO_o}), - .o(wire_nlOli_o), - .sel({wire_nlOll_o[2:1]})); + .data({{2{nll11l}}, nll11i, nliOlO}), + .o(wire_nlllO_o), + .sel({nliOl, nliOi})); defparam - nlOli.width_data = 4, - nlOli.width_sel = 2; - oper_mux nlOlO + nlllO.width_data = 4, + nlllO.width_sel = 2; + oper_mux nllOi ( - .data({wire_n1li_o[12], wire_n1li_o[8], wire_n1li_o[4], wire_n1li_o[0]}), - .o(wire_nlOlO_o), - .sel({wire_nlOll_o[4:3]})); + .data({{3{nll11l}}, nliOOi}), + .o(wire_nllOi_o), + .sel({nliOl, nliOi})); defparam - nlOlO.width_data = 4, - nlOlO.width_sel = 2; - oper_mux nlOOi + nllOi.width_data = 4, + nllOi.width_sel = 2; + oper_mux nllOl ( - .data({wire_n1li_o[13], wire_n1li_o[9], wire_n1li_o[5], wire_n1li_o[1]}), - .o(wire_nlOOi_o), - .sel({wire_nlOll_o[4:3]})); + .data({{3{nll11l}}, nliOOl}), + .o(wire_nllOl_o), + .sel({nliOl, nliOi})); defparam - nlOOi.width_data = 4, - nlOOi.width_sel = 2; - oper_mux nlOOl + nllOl.width_data = 4, + nllOl.width_sel = 2; + oper_mux nllOO ( - .data({wire_n1li_o[13], wire_n1li_o[10], wire_n1li_o[6], wire_n1li_o[2]}), - .o(wire_nlOOl_o), - .sel({wire_nlOll_o[4:3]})); + .data({{3{nll11l}}, nliOOO}), + .o(wire_nllOO_o), + .sel({nliOl, nliOi})); defparam - nlOOl.width_data = 4, - nlOOl.width_sel = 2; - oper_mux nlOOO + nllOO.width_data = 4, + nllOO.width_sel = 2; + oper_mux nlO1i ( - .data({wire_n1li_o[13], wire_n1li_o[11], wire_n1li_o[7], wire_n1li_o[3]}), - .o(wire_nlOOO_o), - .sel({wire_nlOll_o[4:3]})); + .data({{3{nll11l}}, nll11i}), + .o(wire_nlO1i_o), + .sel({nliOl, nliOi})); defparam - nlOOO.width_data = 4, - nlOOO.width_sel = 2; + nlO1i.width_data = 4, + nlO1i.width_sel = 2; assign - nlOliO = ((((((((((~ n100i) & (~ n101O)) & (~ n101l)) & (~ n101i)) & (~ n11OO)) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)), - nlOlli = ((((((((((~ wire_nil_dataout) & (~ wire_nii_dataout)) & (~ wire_n0O_dataout)) & (~ wire_n0l_dataout)) & (~ wire_n0i_dataout)) & (~ wire_n1O_dataout)) & (~ wire_n1l_dataout)) & (~ wire_n1i_dataout)) & (~ wire_nlOO_dataout)) & (~ wire_nlOl_dataout)), - nlOlll = ((((n110i & n111O) & n111l) & n111i) & nlOOOO), - nlOllO = (((wire_nl01O_dataout & nlOOii) & n10OO) & n1i1i), - nlOlOi = (((((((~ n0i1i) & (~ n00OO)) & n00Ol) & n00Oi) & n00lO) & n00ll) & n00li), - nlOlOl = (nlOO0O & nlOO1O), - nlOlOO = ((n1O0l | n1O0O) | ((n1Oli & n1Oll) & n1Oii)), - nlOO0i = (((((~ n1l0i) & (~ n1l1O)) & (~ n1l1l)) & (~ n1l1i)) & (~ n1iOO)), - nlOO0l = ((((n1l0i & n1l1O) & n1l1l) & n1l1i) & n1iOO), - nlOO0O = ((~ n1ilO) & n1iOi), - nlOO1i = (nlOO0l & n1O1O), - nlOO1l = (n1ilO & n1O1i), - nlOO1O = ((~ nlOO0l) & (~ nlOO0i)), - nlOOii = ((~ wire_nl00O_dataout) & (~ wire_nl00l_dataout)), - nlOOil = ((((((((~ wire_nl0Ol_o[6]) & (~ wire_nl0Ol_o[7])) & (~ wire_nl0Ol_o[8])) & (~ wire_nl0Ol_o[9])) & (~ wire_nl0Ol_o[10])) & (~ wire_nl0Ol_o[11])) & (~ wire_nl0Ol_o[12])) & (~ wire_nl0Ol_o[13])), - nlOOiO = 1'b1, - nlOOli = (((((~ wire_ni_dataout) & (~ wire_nlO_dataout)) & (~ wire_nll_dataout)) & (~ wire_nli_dataout)) & (~ wire_niO_dataout)), - q = {((~ nlOlOO) & n1O0i), wire_nii0i_o, wire_nii1O_o, wire_nii1l_o, wire_nii1i_o, wire_ni0OO_o, wire_ni0Ol_o, wire_ni0Oi_o, wire_ni0lO_o, wire_ni0ll_o, wire_ni0li_o, wire_ni0iO_o, wire_ni0il_o, wire_ni0ii_o, wire_ni00O_o, wire_ni00l_o}; + nli10i = ((((((((((~ nll0ii) & (~ nll00O)) & (~ nll00l)) & (~ nll00i)) & (~ nll01O)) & (~ nll01l)) & (~ nll01i)) & (~ nll1OO)) & (~ nll1Ol)) & (~ nll1Oi)), + nli10l = ((((((((((~ nl0l) & (~ nl0i)) & (~ nl1O)) & (~ nl1l)) & (~ nl1i)) & (~ niOO)) & (~ niOl)) & (~ niOi)) & (~ nilO)) & (~ n0li)), + nli10O = (((((~ nlO1lO) & (~ nlO1ll)) & (~ nlO1li)) & (~ nlO1iO)) & (~ nlO1il)), + nli11O = (((((((~ ni0ii) & (~ ni00O)) & ni00l) & ni00i) & ni01O) & ni01l) & n0O1O), + nli1ii = ((((nlO1lO & nlO1ll) & nlO1li) & nlO1iO) & nlO1il), + nli1il = ((((nll1ii & nll10O) & nll10l) & nll10i) & nll11O), + nli1iO = (nlO1ii & nlO0OO), + nli1li = ((((~ niO0O) & (~ niO0l)) & (~ niO0i)) & (~ niO1O)), + nli1ll = ((((((((~ nlllll) & (~ nlllli)) & (~ nllliO)) & (~ nlllil)) & (~ nlllii)) & (~ nlll0O)) & (~ nlll0l)) & (~ nlll0i)), + nli1lO = (((((~ nlli) & (~ nliO)) & (~ nlil)) & (~ nlii)) & (~ nl0O)), + nli1Oi = (nlll ^ n0iO), + nli1Ol = 1'b1, + q = {(nlOllO & (~ nlOO0O)), wire_n0lOO_o, wire_n0lOl_o, wire_n0lOi_o, wire_n0llO_o, wire_n0lll_o, wire_n0lli_o, wire_n0liO_o, wire_n0lil_o, wire_n0lii_o, wire_n0l0O_o, wire_n0l0l_o, wire_n0l0i_o, wire_n0l1O_o, wire_n0l1l_o, wire_n0l1i_o}; endmodule //ip_fp_add //synopsys translate_on //VALID FILE diff --git a/ip/ip_fp_add_sim/mentor/msim_setup.tcl b/ip/ip_fp_add_sim/mentor/msim_setup.tcl index 3cc824c..38204c6 100644 --- a/ip/ip_fp_add_sim/mentor/msim_setup.tcl +++ b/ip/ip_fp_add_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # Initialize variables diff --git a/ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh b/ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh index 6ccf6e2..860cb30 100755 --- a/ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh +++ b/ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # vcs - auto-generated simulation script @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_add" diff --git a/ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh index 72d3aea..2debcf8 100755 --- a/ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_add" diff --git a/ip/ip_fp_mul.qip b/ip/ip_fp_mul.qip index f6114d9..845398a 100644 --- a/ip/ip_fp_mul.qip +++ b/ip/ip_fp_mul.qip @@ -35,8 +35,8 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MTA=::TWFudGlzc2E=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MTA=::ZnBfbWFuX2Rlcml2ZWQ=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg=" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::NA==::VGFyZ2V0" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MjAw::VGFyZ2V0" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Mg==::VGFyZ2V0" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::ZnJlcXVlbmN5::R29hbA==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ==" @@ -52,8 +52,8 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg==" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MTA4::ZnJlcXVlbmN5X2ZlZWRiYWNr" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::Mw==::bGF0ZW5jeV9mZWVkYmFjaw==" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::NQ==::bGF0ZW5jeV9mZWVkYmFjaw==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50" @@ -69,7 +69,7 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MQ==::TXVsdGlwbGllcw==" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MTE5::TFVUcw==" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MTQ0::TFVUcw==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" diff --git a/ip/ip_fp_mul.v b/ip/ip_fp_mul.v index 22fa2bb..d8f0e67 100644 --- a/ip/ip_fp_mul.v +++ b/ip/ip_fp_mul.v @@ -63,8 +63,8 @@ endmodule // Retrieval info: <generic name="fp_exp" value="5" /> // Retrieval info: <generic name="fp_man" value="10" /> // Retrieval info: <generic name="exponent_width" value="23" /> -// Retrieval info: <generic name="frequency_target" value="100" /> -// Retrieval info: <generic name="latency_target" value="4" /> +// Retrieval info: <generic name="frequency_target" value="200" /> +// Retrieval info: <generic name="latency_target" value="2" /> // Retrieval info: <generic name="performance_goal" value="frequency" /> // Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" /> // Retrieval info: <generic name="faithful_rounding" value="true" /> diff --git a/ip/ip_fp_mul/ip_fp_mul_0002.vhd b/ip/ip_fp_mul/ip_fp_mul_0002.vhd index 582906b..443f819 100644 --- a/ip/ip_fp_mul/ip_fp_mul_0002.vhd +++ b/ip/ip_fp_mul/ip_fp_mul_0002.vhd @@ -16,7 +16,7 @@ -- --------------------------------------------------------------------------- -- VHDL created from ip_fp_mul_0002 --- VHDL created on Sat Oct 21 14:27:40 2023 +-- VHDL created on Wed Oct 25 23:48:20 2023 library IEEE; @@ -67,6 +67,7 @@ architecture normal of ip_fp_mul_0002 is signal fracXIsZero_uid17_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsNotZero_uid18_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excI_x_uid19_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excN_x_uid20_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excN_x_uid20_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExpXIsMax_uid21_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal InvExpXIsZero_uid22_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); @@ -80,6 +81,7 @@ architecture normal of ip_fp_mul_0002 is signal fracXIsZero_uid31_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsNotZero_uid32_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excI_y_uid33_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excN_y_uid34_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excN_y_uid34_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExpXIsMax_uid35_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal InvExpXIsZero_uid36_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); @@ -123,18 +125,27 @@ architecture normal of ip_fp_mul_0002 is signal expOvf_uid64_fpMulTest_b : STD_LOGIC_VECTOR (10 downto 0); signal expOvf_uid64_fpMulTest_o : STD_LOGIC_VECTOR (10 downto 0); signal expOvf_uid64_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0); + signal excXZAndExcYZ_uid65_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excXZAndExcYZ_uid65_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excXZAndExcYR_uid66_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excXZAndExcYR_uid66_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excYZAndExcXR_uid67_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excYZAndExcXR_uid67_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excZC3_uid68_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excZC3_uid68_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excRZero_uid69_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excXIAndExcYI_uid70_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excXIAndExcYI_uid70_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excXRAndExcYI_uid71_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excXRAndExcYI_uid71_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal excYRAndExcXI_uid72_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excYRAndExcXI_uid72_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal ExcROvfAndInReg_uid73_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal ExcROvfAndInReg_uid73_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excRInf_uid74_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excYZAndExcXI_uid75_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excXZAndExcYI_uid76_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); + signal ZeroTimesInf_uid77_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal ZeroTimesInf_uid77_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excRNaN_uid78_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal concExc_uid79_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0); @@ -166,17 +177,19 @@ architecture normal of ip_fp_mul_0002 is signal prodXY_uid94_prod_uid47_fpMulTest_cma_q : STD_LOGIC_VECTOR (21 downto 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 : std_logic; signal prodXY_uid94_prod_uid47_fpMulTest_cma_ena1 : std_logic; - signal redist0_expRPreExcExt_uid60_fpMulTest_b_1_q : STD_LOGIC_VECTOR (8 downto 0); - signal redist1_fracRPreExc_uid59_fpMulTest_b_1_q : STD_LOGIC_VECTOR (9 downto 0); - signal redist2_signR_uid48_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist3_fracXIsZero_uid31_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist4_expXIsMax_uid30_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist5_excZ_y_uid29_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist6_fracXIsZero_uid17_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist7_expXIsMax_uid16_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist8_excZ_x_uid15_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist9_expY_uid7_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); - signal redist10_expX_uid6_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist0_expRPreExc_uid61_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist1_expRPreExcExt_uid60_fpMulTest_b_1_q : STD_LOGIC_VECTOR (8 downto 0); + signal redist2_fracRPreExc_uid59_fpMulTest_b_2_q : STD_LOGIC_VECTOR (9 downto 0); + signal redist3_normalizeBit_uid49_fpMulTest_b_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist4_signR_uid48_fpMulTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist5_fracXIsZero_uid31_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist6_expXIsMax_uid30_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist7_excZ_y_uid29_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist8_fracXIsZero_uid17_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist9_expXIsMax_uid16_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist10_excZ_x_uid15_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist11_expY_uid7_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist12_expX_uid6_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); begin @@ -193,10 +206,10 @@ begin GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_qi, xout => fracXIsZero_uid17_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist6_fracXIsZero_uid17_fpMulTest_q_3(DELAY,103) - redist6_fracXIsZero_uid17_fpMulTest_q_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist6_fracXIsZero_uid17_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); + -- redist8_fracXIsZero_uid17_fpMulTest_q_4(DELAY,105) + redist8_fracXIsZero_uid17_fpMulTest_q_4 : dspba_delay + GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist8_fracXIsZero_uid17_fpMulTest_q_4_q, ena => en(0), clk => clk, aclr => areset ); -- cstAllOWE_uid10_fpMulTest(CONSTANT,9) cstAllOWE_uid10_fpMulTest_q <= "11111"; @@ -204,24 +217,24 @@ begin -- expX_uid6_fpMulTest(BITSELECT,5)@0 expX_uid6_fpMulTest_b <= a(14 downto 10); - -- redist10_expX_uid6_fpMulTest_b_1(DELAY,107) - redist10_expX_uid6_fpMulTest_b_1 : dspba_delay + -- redist12_expX_uid6_fpMulTest_b_1(DELAY,109) + redist12_expX_uid6_fpMulTest_b_1 : dspba_delay GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expX_uid6_fpMulTest_b, xout => redist10_expX_uid6_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + PORT MAP ( xin => expX_uid6_fpMulTest_b, xout => redist12_expX_uid6_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); -- expXIsMax_uid16_fpMulTest(LOGICAL,15)@1 + 1 - expXIsMax_uid16_fpMulTest_qi <= "1" WHEN redist10_expX_uid6_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0"; + expXIsMax_uid16_fpMulTest_qi <= "1" WHEN redist12_expX_uid6_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0"; expXIsMax_uid16_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => expXIsMax_uid16_fpMulTest_qi, xout => expXIsMax_uid16_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist7_expXIsMax_uid16_fpMulTest_q_2(DELAY,104) - redist7_expXIsMax_uid16_fpMulTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist7_expXIsMax_uid16_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); + -- redist9_expXIsMax_uid16_fpMulTest_q_3(DELAY,106) + redist9_expXIsMax_uid16_fpMulTest_q_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist9_expXIsMax_uid16_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- excI_x_uid19_fpMulTest(LOGICAL,18)@3 - excI_x_uid19_fpMulTest_q <= redist7_expXIsMax_uid16_fpMulTest_q_2_q and redist6_fracXIsZero_uid17_fpMulTest_q_3_q; + -- excI_x_uid19_fpMulTest(LOGICAL,18)@4 + excI_x_uid19_fpMulTest_q <= redist9_expXIsMax_uid16_fpMulTest_q_3_q and redist8_fracXIsZero_uid17_fpMulTest_q_4_q; -- cstAllZWE_uid12_fpMulTest(CONSTANT,11) cstAllZWE_uid12_fpMulTest_q <= "00000"; @@ -229,24 +242,24 @@ begin -- expY_uid7_fpMulTest(BITSELECT,6)@0 expY_uid7_fpMulTest_b <= b(14 downto 10); - -- redist9_expY_uid7_fpMulTest_b_1(DELAY,106) - redist9_expY_uid7_fpMulTest_b_1 : dspba_delay + -- redist11_expY_uid7_fpMulTest_b_1(DELAY,108) + redist11_expY_uid7_fpMulTest_b_1 : dspba_delay GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expY_uid7_fpMulTest_b, xout => redist9_expY_uid7_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + PORT MAP ( xin => expY_uid7_fpMulTest_b, xout => redist11_expY_uid7_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); -- excZ_y_uid29_fpMulTest(LOGICAL,28)@1 + 1 - excZ_y_uid29_fpMulTest_qi <= "1" WHEN redist9_expY_uid7_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0"; + excZ_y_uid29_fpMulTest_qi <= "1" WHEN redist11_expY_uid7_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0"; excZ_y_uid29_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => excZ_y_uid29_fpMulTest_qi, xout => excZ_y_uid29_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist5_excZ_y_uid29_fpMulTest_q_2(DELAY,102) - redist5_excZ_y_uid29_fpMulTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist5_excZ_y_uid29_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); + -- redist7_excZ_y_uid29_fpMulTest_q_3(DELAY,104) + redist7_excZ_y_uid29_fpMulTest_q_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist7_excZ_y_uid29_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@3 - excYZAndExcXI_uid75_fpMulTest_q <= redist5_excZ_y_uid29_fpMulTest_q_2_q and excI_x_uid19_fpMulTest_q; + -- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@4 + excYZAndExcXI_uid75_fpMulTest_q <= redist7_excZ_y_uid29_fpMulTest_q_3_q and excI_x_uid19_fpMulTest_q; -- frac_y_uid28_fpMulTest(BITSELECT,27)@0 frac_y_uid28_fpMulTest_b <= b(9 downto 0); @@ -257,58 +270,67 @@ begin GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_qi, xout => fracXIsZero_uid31_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist3_fracXIsZero_uid31_fpMulTest_q_3(DELAY,100) - redist3_fracXIsZero_uid31_fpMulTest_q_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist3_fracXIsZero_uid31_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); + -- redist5_fracXIsZero_uid31_fpMulTest_q_4(DELAY,102) + redist5_fracXIsZero_uid31_fpMulTest_q_4 : dspba_delay + GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist5_fracXIsZero_uid31_fpMulTest_q_4_q, ena => en(0), clk => clk, aclr => areset ); -- expXIsMax_uid30_fpMulTest(LOGICAL,29)@1 + 1 - expXIsMax_uid30_fpMulTest_qi <= "1" WHEN redist9_expY_uid7_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0"; + expXIsMax_uid30_fpMulTest_qi <= "1" WHEN redist11_expY_uid7_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0"; expXIsMax_uid30_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => expXIsMax_uid30_fpMulTest_qi, xout => expXIsMax_uid30_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist4_expXIsMax_uid30_fpMulTest_q_2(DELAY,101) - redist4_expXIsMax_uid30_fpMulTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist4_expXIsMax_uid30_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); + -- redist6_expXIsMax_uid30_fpMulTest_q_3(DELAY,103) + redist6_expXIsMax_uid30_fpMulTest_q_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist6_expXIsMax_uid30_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- excI_y_uid33_fpMulTest(LOGICAL,32)@3 - excI_y_uid33_fpMulTest_q <= redist4_expXIsMax_uid30_fpMulTest_q_2_q and redist3_fracXIsZero_uid31_fpMulTest_q_3_q; + -- excI_y_uid33_fpMulTest(LOGICAL,32)@4 + excI_y_uid33_fpMulTest_q <= redist6_expXIsMax_uid30_fpMulTest_q_3_q and redist5_fracXIsZero_uid31_fpMulTest_q_4_q; -- excZ_x_uid15_fpMulTest(LOGICAL,14)@1 + 1 - excZ_x_uid15_fpMulTest_qi <= "1" WHEN redist10_expX_uid6_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0"; + excZ_x_uid15_fpMulTest_qi <= "1" WHEN redist12_expX_uid6_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0"; excZ_x_uid15_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => excZ_x_uid15_fpMulTest_qi, xout => excZ_x_uid15_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist8_excZ_x_uid15_fpMulTest_q_2(DELAY,105) - redist8_excZ_x_uid15_fpMulTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist8_excZ_x_uid15_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); + -- redist10_excZ_x_uid15_fpMulTest_q_3(DELAY,107) + redist10_excZ_x_uid15_fpMulTest_q_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist10_excZ_x_uid15_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@3 - excXZAndExcYI_uid76_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and excI_y_uid33_fpMulTest_q; + -- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@4 + excXZAndExcYI_uid76_fpMulTest_q <= redist10_excZ_x_uid15_fpMulTest_q_3_q and excI_y_uid33_fpMulTest_q; - -- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@3 - ZeroTimesInf_uid77_fpMulTest_q <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q; + -- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@4 + 1 + ZeroTimesInf_uid77_fpMulTest_qi <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q; + ZeroTimesInf_uid77_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => ZeroTimesInf_uid77_fpMulTest_qi, xout => ZeroTimesInf_uid77_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@3 - fracXIsNotZero_uid32_fpMulTest_q <= not (redist3_fracXIsZero_uid31_fpMulTest_q_3_q); + -- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@4 + fracXIsNotZero_uid32_fpMulTest_q <= not (redist5_fracXIsZero_uid31_fpMulTest_q_4_q); - -- excN_y_uid34_fpMulTest(LOGICAL,33)@3 - excN_y_uid34_fpMulTest_q <= redist4_expXIsMax_uid30_fpMulTest_q_2_q and fracXIsNotZero_uid32_fpMulTest_q; + -- excN_y_uid34_fpMulTest(LOGICAL,33)@4 + 1 + excN_y_uid34_fpMulTest_qi <= redist6_expXIsMax_uid30_fpMulTest_q_3_q and fracXIsNotZero_uid32_fpMulTest_q; + excN_y_uid34_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excN_y_uid34_fpMulTest_qi, xout => excN_y_uid34_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@3 - fracXIsNotZero_uid18_fpMulTest_q <= not (redist6_fracXIsZero_uid17_fpMulTest_q_3_q); + -- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@4 + fracXIsNotZero_uid18_fpMulTest_q <= not (redist8_fracXIsZero_uid17_fpMulTest_q_4_q); - -- excN_x_uid20_fpMulTest(LOGICAL,19)@3 - excN_x_uid20_fpMulTest_q <= redist7_expXIsMax_uid16_fpMulTest_q_2_q and fracXIsNotZero_uid18_fpMulTest_q; + -- excN_x_uid20_fpMulTest(LOGICAL,19)@4 + 1 + excN_x_uid20_fpMulTest_qi <= redist9_expXIsMax_uid16_fpMulTest_q_3_q and fracXIsNotZero_uid18_fpMulTest_q; + excN_x_uid20_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excN_x_uid20_fpMulTest_qi, xout => excN_x_uid20_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excRNaN_uid78_fpMulTest(LOGICAL,77)@3 + -- excRNaN_uid78_fpMulTest(LOGICAL,77)@5 excRNaN_uid78_fpMulTest_q <= excN_x_uid20_fpMulTest_q or excN_y_uid34_fpMulTest_q or ZeroTimesInf_uid77_fpMulTest_q; - -- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@3 + -- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@5 invExcRNaN_uid90_fpMulTest_q <= not (excRNaN_uid78_fpMulTest_q); -- signY_uid9_fpMulTest(BITSELECT,8)@0 @@ -323,13 +345,13 @@ begin GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) PORT MAP ( xin => signR_uid48_fpMulTest_qi, xout => signR_uid48_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist2_signR_uid48_fpMulTest_q_3(DELAY,99) - redist2_signR_uid48_fpMulTest_q_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist2_signR_uid48_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); + -- redist4_signR_uid48_fpMulTest_q_5(DELAY,101) + redist4_signR_uid48_fpMulTest_q_5 : dspba_delay + GENERIC MAP ( width => 1, depth => 4, reset_kind => "ASYNC" ) + PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist4_signR_uid48_fpMulTest_q_5_q, ena => en(0), clk => clk, aclr => areset ); - -- signRPostExc_uid91_fpMulTest(LOGICAL,90)@3 - signRPostExc_uid91_fpMulTest_q <= redist2_signR_uid48_fpMulTest_q_3_q and invExcRNaN_uid90_fpMulTest_q; + -- signRPostExc_uid91_fpMulTest(LOGICAL,90)@5 + signRPostExc_uid91_fpMulTest_q <= redist4_signR_uid48_fpMulTest_q_5_q and invExcRNaN_uid90_fpMulTest_q; -- GND(CONSTANT,0) GND_q <= "0"; @@ -382,18 +404,23 @@ begin -- normalizeBit_uid49_fpMulTest(BITSELECT,48)@2 normalizeBit_uid49_fpMulTest_b <= STD_LOGIC_VECTOR(osig_uid95_prod_uid47_fpMulTest_b(12 downto 12)); + -- redist3_normalizeBit_uid49_fpMulTest_b_1(DELAY,100) + redist3_normalizeBit_uid49_fpMulTest_b_1 : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => normalizeBit_uid49_fpMulTest_b, xout => redist3_normalizeBit_uid49_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + -- VCC(CONSTANT,1) VCC_q <= "1"; - -- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@2 - roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & normalizeBit_uid49_fpMulTest_b & cstZeroWF_uid11_fpMulTest_q & VCC_q; + -- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@3 + roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & redist3_normalizeBit_uid49_fpMulTest_b_1_q & cstZeroWF_uid11_fpMulTest_q & VCC_q; -- biasInc_uid45_fpMulTest(CONSTANT,44) biasInc_uid45_fpMulTest_q <= "0001111"; -- expSum_uid44_fpMulTest(ADD,43)@1 + 1 - expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & redist10_expX_uid6_fpMulTest_b_1_q); - expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & redist9_expY_uid7_fpMulTest_b_1_q); + expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & redist12_expX_uid6_fpMulTest_b_1_q); + expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & redist11_expY_uid7_fpMulTest_b_1_q); expSum_uid44_fpMulTest_clkproc: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN @@ -406,10 +433,19 @@ begin END PROCESS; expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(5 downto 0); - -- expSumMBias_uid46_fpMulTest(SUB,45)@2 + -- expSumMBias_uid46_fpMulTest(SUB,45)@2 + 1 expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000" & expSum_uid44_fpMulTest_q)); expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((8 downto 7 => biasInc_uid45_fpMulTest_q(6)) & biasInc_uid45_fpMulTest_q)); - expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b)); + expSumMBias_uid46_fpMulTest_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + expSumMBias_uid46_fpMulTest_o <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b)); + END IF; + END IF; + END PROCESS; expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(7 downto 0); -- fracRPostNormHigh_uid51_fpMulTest(BITSELECT,50)@2 @@ -420,102 +456,137 @@ begin fracRPostNormLow_uid52_fpMulTest_in <= osig_uid95_prod_uid47_fpMulTest_b(10 downto 0); fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(10 downto 0); - -- fracRPostNorm_uid53_fpMulTest(MUX,52)@2 + -- fracRPostNorm_uid53_fpMulTest(MUX,52)@2 + 1 fracRPostNorm_uid53_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b; - fracRPostNorm_uid53_fpMulTest_combproc: PROCESS (fracRPostNorm_uid53_fpMulTest_s, en, fracRPostNormLow_uid52_fpMulTest_b, fracRPostNormHigh_uid51_fpMulTest_b) + fracRPostNorm_uid53_fpMulTest_clkproc: PROCESS (clk, areset) BEGIN - CASE (fracRPostNorm_uid53_fpMulTest_s) IS - WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b; - WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b; - WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0'); - END CASE; + IF (areset = '1') THEN + fracRPostNorm_uid53_fpMulTest_q <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + CASE (fracRPostNorm_uid53_fpMulTest_s) IS + WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b; + WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b; + WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0'); + END CASE; + END IF; + END IF; END PROCESS; - -- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@2 + -- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@3 expFracPreRound_uid55_fpMulTest_q <= expSumMBias_uid46_fpMulTest_q & fracRPostNorm_uid53_fpMulTest_q; - -- expFracRPostRounding_uid58_fpMulTest(ADD,57)@2 + -- expFracRPostRounding_uid58_fpMulTest(ADD,57)@3 expFracRPostRounding_uid58_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((20 downto 19 => expFracPreRound_uid55_fpMulTest_q(18)) & expFracPreRound_uid55_fpMulTest_q)); expFracRPostRounding_uid58_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("00000000" & roundBitAndNormalizationOp_uid57_fpMulTest_q)); expFracRPostRounding_uid58_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid58_fpMulTest_a) + SIGNED(expFracRPostRounding_uid58_fpMulTest_b)); expFracRPostRounding_uid58_fpMulTest_q <= expFracRPostRounding_uid58_fpMulTest_o(19 downto 0); - -- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@2 + -- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@3 expRPreExcExt_uid60_fpMulTest_b <= STD_LOGIC_VECTOR(expFracRPostRounding_uid58_fpMulTest_q(19 downto 11)); - -- redist0_expRPreExcExt_uid60_fpMulTest_b_1(DELAY,97) - redist0_expRPreExcExt_uid60_fpMulTest_b_1 : dspba_delay + -- redist1_expRPreExcExt_uid60_fpMulTest_b_1(DELAY,98) + redist1_expRPreExcExt_uid60_fpMulTest_b_1 : dspba_delay GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expRPreExcExt_uid60_fpMulTest_b, xout => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + PORT MAP ( xin => expRPreExcExt_uid60_fpMulTest_b, xout => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- expRPreExc_uid61_fpMulTest(BITSELECT,60)@3 - expRPreExc_uid61_fpMulTest_in <= redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(4 downto 0); + -- expRPreExc_uid61_fpMulTest(BITSELECT,60)@4 + expRPreExc_uid61_fpMulTest_in <= redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(4 downto 0); expRPreExc_uid61_fpMulTest_b <= expRPreExc_uid61_fpMulTest_in(4 downto 0); - -- expOvf_uid64_fpMulTest(COMPARE,63)@3 - expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist0_expRPreExcExt_uid60_fpMulTest_b_1_q)); + -- redist0_expRPreExc_uid61_fpMulTest_b_1(DELAY,97) + redist0_expRPreExc_uid61_fpMulTest_b_1 : dspba_delay + GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => expRPreExc_uid61_fpMulTest_b, xout => redist0_expRPreExc_uid61_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- expOvf_uid64_fpMulTest(COMPARE,63)@4 + expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist1_expRPreExcExt_uid60_fpMulTest_b_1_q)); expOvf_uid64_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000000" & cstAllOWE_uid10_fpMulTest_q)); expOvf_uid64_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid64_fpMulTest_a) - SIGNED(expOvf_uid64_fpMulTest_b)); expOvf_uid64_fpMulTest_n(0) <= not (expOvf_uid64_fpMulTest_o(10)); - -- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@3 - invExpXIsMax_uid35_fpMulTest_q <= not (redist4_expXIsMax_uid30_fpMulTest_q_2_q); + -- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@4 + invExpXIsMax_uid35_fpMulTest_q <= not (redist6_expXIsMax_uid30_fpMulTest_q_3_q); - -- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@3 - InvExpXIsZero_uid36_fpMulTest_q <= not (redist5_excZ_y_uid29_fpMulTest_q_2_q); + -- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@4 + InvExpXIsZero_uid36_fpMulTest_q <= not (redist7_excZ_y_uid29_fpMulTest_q_3_q); - -- excR_y_uid37_fpMulTest(LOGICAL,36)@3 + -- excR_y_uid37_fpMulTest(LOGICAL,36)@4 excR_y_uid37_fpMulTest_q <= InvExpXIsZero_uid36_fpMulTest_q and invExpXIsMax_uid35_fpMulTest_q; - -- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@3 - invExpXIsMax_uid21_fpMulTest_q <= not (redist7_expXIsMax_uid16_fpMulTest_q_2_q); + -- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@4 + invExpXIsMax_uid21_fpMulTest_q <= not (redist9_expXIsMax_uid16_fpMulTest_q_3_q); - -- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@3 - InvExpXIsZero_uid22_fpMulTest_q <= not (redist8_excZ_x_uid15_fpMulTest_q_2_q); + -- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@4 + InvExpXIsZero_uid22_fpMulTest_q <= not (redist10_excZ_x_uid15_fpMulTest_q_3_q); - -- excR_x_uid23_fpMulTest(LOGICAL,22)@3 + -- excR_x_uid23_fpMulTest(LOGICAL,22)@4 excR_x_uid23_fpMulTest_q <= InvExpXIsZero_uid22_fpMulTest_q and invExpXIsMax_uid21_fpMulTest_q; - -- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@3 - ExcROvfAndInReg_uid73_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n; + -- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@4 + 1 + ExcROvfAndInReg_uid73_fpMulTest_qi <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n; + ExcROvfAndInReg_uid73_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => ExcROvfAndInReg_uid73_fpMulTest_qi, xout => ExcROvfAndInReg_uid73_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@3 - excYRAndExcXI_uid72_fpMulTest_q <= excR_y_uid37_fpMulTest_q and excI_x_uid19_fpMulTest_q; + -- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@4 + 1 + excYRAndExcXI_uid72_fpMulTest_qi <= excR_y_uid37_fpMulTest_q and excI_x_uid19_fpMulTest_q; + excYRAndExcXI_uid72_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excYRAndExcXI_uid72_fpMulTest_qi, xout => excYRAndExcXI_uid72_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@3 - excXRAndExcYI_uid71_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excI_y_uid33_fpMulTest_q; + -- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@4 + 1 + excXRAndExcYI_uid71_fpMulTest_qi <= excR_x_uid23_fpMulTest_q and excI_y_uid33_fpMulTest_q; + excXRAndExcYI_uid71_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excXRAndExcYI_uid71_fpMulTest_qi, xout => excXRAndExcYI_uid71_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@3 - excXIAndExcYI_uid70_fpMulTest_q <= excI_x_uid19_fpMulTest_q and excI_y_uid33_fpMulTest_q; + -- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@4 + 1 + excXIAndExcYI_uid70_fpMulTest_qi <= excI_x_uid19_fpMulTest_q and excI_y_uid33_fpMulTest_q; + excXIAndExcYI_uid70_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excXIAndExcYI_uid70_fpMulTest_qi, xout => excXIAndExcYI_uid70_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excRInf_uid74_fpMulTest(LOGICAL,73)@3 + -- excRInf_uid74_fpMulTest(LOGICAL,73)@5 excRInf_uid74_fpMulTest_q <= excXIAndExcYI_uid70_fpMulTest_q or excXRAndExcYI_uid71_fpMulTest_q or excYRAndExcXI_uid72_fpMulTest_q or ExcROvfAndInReg_uid73_fpMulTest_q; - -- expUdf_uid62_fpMulTest(COMPARE,61)@3 + -- expUdf_uid62_fpMulTest(COMPARE,61)@4 expUdf_uid62_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0000000000" & GND_q)); - expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist0_expRPreExcExt_uid60_fpMulTest_b_1_q)); + expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist1_expRPreExcExt_uid60_fpMulTest_b_1_q)); expUdf_uid62_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid62_fpMulTest_a) - SIGNED(expUdf_uid62_fpMulTest_b)); expUdf_uid62_fpMulTest_n(0) <= not (expUdf_uid62_fpMulTest_o(10)); - -- excZC3_uid68_fpMulTest(LOGICAL,67)@3 - excZC3_uid68_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n; + -- excZC3_uid68_fpMulTest(LOGICAL,67)@4 + 1 + excZC3_uid68_fpMulTest_qi <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n; + excZC3_uid68_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excZC3_uid68_fpMulTest_qi, xout => excZC3_uid68_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@3 - excYZAndExcXR_uid67_fpMulTest_q <= redist5_excZ_y_uid29_fpMulTest_q_2_q and excR_x_uid23_fpMulTest_q; + -- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@4 + 1 + excYZAndExcXR_uid67_fpMulTest_qi <= redist7_excZ_y_uid29_fpMulTest_q_3_q and excR_x_uid23_fpMulTest_q; + excYZAndExcXR_uid67_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excYZAndExcXR_uid67_fpMulTest_qi, xout => excYZAndExcXR_uid67_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@3 - excXZAndExcYR_uid66_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and excR_y_uid37_fpMulTest_q; + -- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@4 + 1 + excXZAndExcYR_uid66_fpMulTest_qi <= redist10_excZ_x_uid15_fpMulTest_q_3_q and excR_y_uid37_fpMulTest_q; + excXZAndExcYR_uid66_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excXZAndExcYR_uid66_fpMulTest_qi, xout => excXZAndExcYR_uid66_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@3 - excXZAndExcYZ_uid65_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and redist5_excZ_y_uid29_fpMulTest_q_2_q; + -- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@4 + 1 + excXZAndExcYZ_uid65_fpMulTest_qi <= redist10_excZ_x_uid15_fpMulTest_q_3_q and redist7_excZ_y_uid29_fpMulTest_q_3_q; + excXZAndExcYZ_uid65_fpMulTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excXZAndExcYZ_uid65_fpMulTest_qi, xout => excXZAndExcYZ_uid65_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excRZero_uid69_fpMulTest(LOGICAL,68)@3 + -- excRZero_uid69_fpMulTest(LOGICAL,68)@5 excRZero_uid69_fpMulTest_q <= excXZAndExcYZ_uid65_fpMulTest_q or excXZAndExcYR_uid66_fpMulTest_q or excYZAndExcXR_uid67_fpMulTest_q or excZC3_uid68_fpMulTest_q; - -- concExc_uid79_fpMulTest(BITJOIN,78)@3 + -- concExc_uid79_fpMulTest(BITJOIN,78)@5 concExc_uid79_fpMulTest_q <= excRNaN_uid78_fpMulTest_q & excRInf_uid74_fpMulTest_q & excRZero_uid69_fpMulTest_q; - -- excREnc_uid80_fpMulTest(LOOKUP,79)@3 + -- excREnc_uid80_fpMulTest(LOOKUP,79)@5 excREnc_uid80_fpMulTest_combproc: PROCESS (concExc_uid79_fpMulTest_q) BEGIN -- Begin reserved scope level @@ -534,13 +605,13 @@ begin -- End reserved scope level END PROCESS; - -- expRPostExc_uid89_fpMulTest(MUX,88)@3 + -- expRPostExc_uid89_fpMulTest(MUX,88)@5 expRPostExc_uid89_fpMulTest_s <= excREnc_uid80_fpMulTest_q; - expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, en, cstAllZWE_uid12_fpMulTest_q, expRPreExc_uid61_fpMulTest_b, cstAllOWE_uid10_fpMulTest_q) + expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, en, cstAllZWE_uid12_fpMulTest_q, redist0_expRPreExc_uid61_fpMulTest_b_1_q, cstAllOWE_uid10_fpMulTest_q) BEGIN CASE (expRPostExc_uid89_fpMulTest_s) IS WHEN "00" => expRPostExc_uid89_fpMulTest_q <= cstAllZWE_uid12_fpMulTest_q; - WHEN "01" => expRPostExc_uid89_fpMulTest_q <= expRPreExc_uid61_fpMulTest_b; + WHEN "01" => expRPostExc_uid89_fpMulTest_q <= redist0_expRPreExc_uid61_fpMulTest_b_1_q; WHEN "10" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q; WHEN "11" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q; WHEN OTHERS => expRPostExc_uid89_fpMulTest_q <= (others => '0'); @@ -550,32 +621,32 @@ begin -- oneFracRPostExc2_uid81_fpMulTest(CONSTANT,80) oneFracRPostExc2_uid81_fpMulTest_q <= "0000000001"; - -- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@2 + -- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@3 fracRPreExc_uid59_fpMulTest_in <= expFracRPostRounding_uid58_fpMulTest_q(10 downto 0); fracRPreExc_uid59_fpMulTest_b <= fracRPreExc_uid59_fpMulTest_in(10 downto 1); - -- redist1_fracRPreExc_uid59_fpMulTest_b_1(DELAY,98) - redist1_fracRPreExc_uid59_fpMulTest_b_1 : dspba_delay - GENERIC MAP ( width => 10, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracRPreExc_uid59_fpMulTest_b, xout => redist1_fracRPreExc_uid59_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + -- redist2_fracRPreExc_uid59_fpMulTest_b_2(DELAY,99) + redist2_fracRPreExc_uid59_fpMulTest_b_2 : dspba_delay + GENERIC MAP ( width => 10, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracRPreExc_uid59_fpMulTest_b, xout => redist2_fracRPreExc_uid59_fpMulTest_b_2_q, ena => en(0), clk => clk, aclr => areset ); - -- fracRPostExc_uid84_fpMulTest(MUX,83)@3 + -- fracRPostExc_uid84_fpMulTest(MUX,83)@5 fracRPostExc_uid84_fpMulTest_s <= excREnc_uid80_fpMulTest_q; - fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, en, cstZeroWF_uid11_fpMulTest_q, redist1_fracRPreExc_uid59_fpMulTest_b_1_q, oneFracRPostExc2_uid81_fpMulTest_q) + fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, en, cstZeroWF_uid11_fpMulTest_q, redist2_fracRPreExc_uid59_fpMulTest_b_2_q, oneFracRPostExc2_uid81_fpMulTest_q) BEGIN CASE (fracRPostExc_uid84_fpMulTest_s) IS WHEN "00" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q; - WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= redist1_fracRPreExc_uid59_fpMulTest_b_1_q; + WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= redist2_fracRPreExc_uid59_fpMulTest_b_2_q; WHEN "10" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q; WHEN "11" => fracRPostExc_uid84_fpMulTest_q <= oneFracRPostExc2_uid81_fpMulTest_q; WHEN OTHERS => fracRPostExc_uid84_fpMulTest_q <= (others => '0'); END CASE; END PROCESS; - -- R_uid92_fpMulTest(BITJOIN,91)@3 + -- R_uid92_fpMulTest(BITJOIN,91)@5 R_uid92_fpMulTest_q <= signRPostExc_uid91_fpMulTest_q & expRPostExc_uid89_fpMulTest_q & fracRPostExc_uid84_fpMulTest_q; - -- xOut(GPOUT,4)@3 + -- xOut(GPOUT,4)@5 q <= R_uid92_fpMulTest_q; END normal; diff --git a/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl b/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl index ed471bb..e597209 100644 --- a/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl +++ b/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.20:27:56 +# ACDS 20.1 720 linux 2023.10.26.05:48:33 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- diff --git a/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh b/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh index e4268b4..dd6a06c 100755 --- a/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh +++ b/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.20:27:56 +# ACDS 20.1 720 linux 2023.10.26.05:48:33 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,7 +106,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:27:56 +# ACDS 20.1 720 linux 2023.10.26.05:48:33 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_mul" diff --git a/ip/ip_fp_mul_sim/ip_fp_mul.vo b/ip/ip_fp_mul_sim/ip_fp_mul.vo index a9b9007..6101c63 100644 --- a/ip/ip_fp_mul_sim/ip_fp_mul.vo +++ b/ip/ip_fp_mul_sim/ip_fp_mul.vo @@ -27,7 +27,7 @@ //synopsys translate_off -//synthesis_resources = lut 87 mux21 11 oper_add 5 oper_mult 1 oper_mux 17 +//synthesis_resources = lut 141 mux21 11 oper_add 5 oper_mult 1 oper_mux 17 `timescale 1 ps / 1 ps module ip_fp_mul ( @@ -44,19 +44,68 @@ module ip_fp_mul input [0:0] en; output [15:0] q; + reg n00i; + reg n00l; + reg n01i; + reg n01l; + reg n01O; reg n0ii; + reg n0iiO; reg n0il; + reg n0ili; + reg n0ill; + reg n0ilO; reg n0iO; + reg n0iOi; + reg n0iOl; + reg n0iOO; + reg n0l0i; + reg n0l0l; + reg n0l0O; + reg n0l1i; + reg n0l1l; + reg n0l1O; reg n0li; + reg n0lii; + reg n0lil; + reg n0liO; reg n0ll; + reg n0lli; + reg n0lll; + reg n0llO; + reg n0lOi; + reg n0lOl; + reg n0lOO; + reg n0O0i; + reg n0O0l; + reg n0O0O; + reg n0O1i; + reg n0O1l; + reg n0O1O; reg n0Oi; + reg n0Oii; + reg n0Oil; + reg n0OiO; reg n0Ol; + reg n0Oli; + reg n0Oll; + reg n0OlO; reg n0OO; + reg n0OOi; + reg n0OOl; + reg n0OOO; + reg n11i; reg n1i; reg n1O; + reg n1Oi; + reg n1Ol; + reg n1OO; reg ni00i; reg ni00l; reg ni00O; + reg ni01i; + reg ni01l; + reg ni01O; reg ni0i; reg ni0ii; reg ni0il; @@ -69,9 +118,24 @@ module ip_fp_mul reg ni0Oi; reg ni0Ol; reg ni0OO; + reg ni10i; + reg ni10l; + reg ni10O; + reg ni11i; + reg ni11l; + reg ni11O; reg ni1i; + reg ni1ii; + reg ni1il; + reg ni1iO; reg ni1l; + reg ni1li; + reg ni1ll; + reg ni1lO; reg ni1O; + reg ni1Oi; + reg ni1Ol; + reg ni1OO; reg nii0i; reg nii0l; reg nii0O; @@ -89,29 +153,9 @@ module ip_fp_mul reg niiO; reg niiOi; reg niiOl; - reg niiOO; - reg nil0i; - reg nil0l; - reg nil0O; - reg nil1i; - reg nil1l; - reg nil1O; reg nili; - reg nilii; - reg nilil; - reg niliO; reg nill; - reg nilli; - reg nilll; - reg nillO; reg nilO; - reg nilOi; - reg nilOl; - reg nilOO; - reg niO0i; - reg niO1i; - reg niO1l; - reg niO1O; reg niOi; reg niOl; reg niOO; @@ -125,78 +169,136 @@ module ip_fp_mul reg nlil; reg nliO; reg nlli; + reg nllil; reg nlll; reg nllO; + reg nlO0O; reg nlOi; + reg nlOii; + reg nlOil; + reg nlOiO; reg nlOl; + reg nlOli; + reg nlOll; reg nlOlO; reg nlOO; + reg nlOOi; + reg nlOOl; + reg nlOOO; wire wire_n1l_ENA; - wire wire_n00i_dataout; - wire wire_n00l_dataout; - wire wire_n01i_dataout; - wire wire_n01l_dataout; - wire wire_n01O_dataout; + wire wire_n10i_dataout; + wire wire_n10l_dataout; + wire wire_n10O_dataout; + wire wire_n11l_dataout; + wire wire_n11O_dataout; + wire wire_n1ii_dataout; + wire wire_n1il_dataout; + wire wire_n1iO_dataout; wire wire_n1li_dataout; wire wire_n1ll_dataout; wire wire_n1lO_dataout; - wire wire_n1Oi_dataout; - wire wire_n1Ol_dataout; - wire wire_n1OO_dataout; wire [9:0] wire_n00O_o; wire [5:0] wire_n0lO_o; - wire [11:0] wire_n1il_o; - wire [20:0] wire_n1iO_o; - wire [11:0] wire_nlOll_o; + wire [11:0] wire_nllii_o; + wire [11:0] wire_nlO0i_o; + wire [20:0] wire_nlO0l_o; wire [21:0] wire_n0i_o; - wire wire_nll0i_o; - wire wire_nll0l_o; - wire wire_nll0O_o; - wire wire_nll1l_o; - wire wire_nll1O_o; - wire wire_nllii_o; - wire wire_nllil_o; - wire wire_nlliO_o; - wire wire_nllli_o; - wire wire_nllll_o; - wire wire_nlllO_o; - wire wire_nllOi_o; - wire wire_nllOl_o; - wire wire_nllOO_o; - wire wire_nlO1i_o; - wire wire_nlO1l_o; - wire wire_nlO1O_o; - wire ni01i; - wire ni10i; - wire ni10l; - wire ni10O; - wire ni11l; - wire ni11O; - wire ni1ii; - wire ni1il; - wire ni1iO; - wire ni1li; - wire ni1ll; - wire ni1lO; - wire ni1Oi; - wire ni1Ol; - wire ni1OO; + wire wire_nl0lO_o; + wire wire_nl0Oi_o; + wire wire_nl0Ol_o; + wire wire_nl0OO_o; + wire wire_nli0i_o; + wire wire_nli0l_o; + wire wire_nli0O_o; + wire wire_nli1i_o; + wire wire_nli1l_o; + wire wire_nli1O_o; + wire wire_nliii_o; + wire wire_nliil_o; + wire wire_nliiO_o; + wire wire_nlili_o; + wire wire_nlill_o; + wire wire_nlilO_o; + wire wire_nliOi_o; + wire n00il; + wire n00iO; + wire n00li; + wire n00ll; + wire n00lO; + wire n00Oi; + wire n00Ol; + wire n00OO; + wire n0i0i; + wire n0i0l; + wire n0i0O; + wire n0i1i; + wire n0i1l; + wire n0i1O; initial begin + n00i = 0; + n00l = 0; + n01i = 0; + n01l = 0; + n01O = 0; n0ii = 0; + n0iiO = 0; n0il = 0; + n0ili = 0; + n0ill = 0; + n0ilO = 0; n0iO = 0; + n0iOi = 0; + n0iOl = 0; + n0iOO = 0; + n0l0i = 0; + n0l0l = 0; + n0l0O = 0; + n0l1i = 0; + n0l1l = 0; + n0l1O = 0; n0li = 0; + n0lii = 0; + n0lil = 0; + n0liO = 0; n0ll = 0; + n0lli = 0; + n0lll = 0; + n0llO = 0; + n0lOi = 0; + n0lOl = 0; + n0lOO = 0; + n0O0i = 0; + n0O0l = 0; + n0O0O = 0; + n0O1i = 0; + n0O1l = 0; + n0O1O = 0; n0Oi = 0; + n0Oii = 0; + n0Oil = 0; + n0OiO = 0; n0Ol = 0; + n0Oli = 0; + n0Oll = 0; + n0OlO = 0; n0OO = 0; + n0OOi = 0; + n0OOl = 0; + n0OOO = 0; + n11i = 0; n1i = 0; n1O = 0; + n1Oi = 0; + n1Ol = 0; + n1OO = 0; ni00i = 0; ni00l = 0; ni00O = 0; + ni01i = 0; + ni01l = 0; + ni01O = 0; ni0i = 0; ni0ii = 0; ni0il = 0; @@ -209,9 +311,24 @@ module ip_fp_mul ni0Oi = 0; ni0Ol = 0; ni0OO = 0; + ni10i = 0; + ni10l = 0; + ni10O = 0; + ni11i = 0; + ni11l = 0; + ni11O = 0; ni1i = 0; + ni1ii = 0; + ni1il = 0; + ni1iO = 0; ni1l = 0; + ni1li = 0; + ni1ll = 0; + ni1lO = 0; ni1O = 0; + ni1Oi = 0; + ni1Ol = 0; + ni1OO = 0; nii0i = 0; nii0l = 0; nii0O = 0; @@ -229,29 +346,9 @@ module ip_fp_mul niiO = 0; niiOi = 0; niiOl = 0; - niiOO = 0; - nil0i = 0; - nil0l = 0; - nil0O = 0; - nil1i = 0; - nil1l = 0; - nil1O = 0; nili = 0; - nilii = 0; - nilil = 0; - niliO = 0; nill = 0; - nilli = 0; - nilll = 0; - nillO = 0; nilO = 0; - nilOi = 0; - nilOl = 0; - nilOO = 0; - niO0i = 0; - niO1i = 0; - niO1l = 0; - niO1O = 0; niOi = 0; niOl = 0; niOO = 0; @@ -265,30 +362,89 @@ module ip_fp_mul nlil = 0; nliO = 0; nlli = 0; + nllil = 0; nlll = 0; nllO = 0; + nlO0O = 0; nlOi = 0; + nlOii = 0; + nlOil = 0; + nlOiO = 0; nlOl = 0; + nlOli = 0; + nlOll = 0; nlOlO = 0; nlOO = 0; + nlOOi = 0; + nlOOl = 0; + nlOOO = 0; end always @ ( posedge clk or posedge areset) begin if (areset == 1'b1) begin + n00i <= 0; + n00l <= 0; + n01i <= 0; + n01l <= 0; + n01O <= 0; n0ii <= 0; + n0iiO <= 0; n0il <= 0; + n0ili <= 0; + n0ill <= 0; + n0ilO <= 0; n0iO <= 0; + n0iOi <= 0; + n0iOl <= 0; + n0iOO <= 0; + n0l0i <= 0; + n0l0l <= 0; + n0l0O <= 0; + n0l1i <= 0; + n0l1l <= 0; + n0l1O <= 0; n0li <= 0; + n0lii <= 0; + n0lil <= 0; + n0liO <= 0; n0ll <= 0; + n0lli <= 0; + n0lll <= 0; + n0llO <= 0; + n0lOi <= 0; + n0lOl <= 0; + n0lOO <= 0; + n0O0i <= 0; + n0O0l <= 0; + n0O0O <= 0; + n0O1i <= 0; + n0O1l <= 0; + n0O1O <= 0; n0Oi <= 0; + n0Oii <= 0; + n0Oil <= 0; + n0OiO <= 0; n0Ol <= 0; + n0Oli <= 0; + n0Oll <= 0; + n0OlO <= 0; n0OO <= 0; + n0OOi <= 0; + n0OOl <= 0; + n0OOO <= 0; + n11i <= 0; n1i <= 0; n1O <= 0; + n1Oi <= 0; + n1Ol <= 0; + n1OO <= 0; ni00i <= 0; ni00l <= 0; ni00O <= 0; + ni01i <= 0; + ni01l <= 0; + ni01O <= 0; ni0i <= 0; ni0ii <= 0; ni0il <= 0; @@ -301,9 +457,24 @@ module ip_fp_mul ni0Oi <= 0; ni0Ol <= 0; ni0OO <= 0; + ni10i <= 0; + ni10l <= 0; + ni10O <= 0; + ni11i <= 0; + ni11l <= 0; + ni11O <= 0; ni1i <= 0; + ni1ii <= 0; + ni1il <= 0; + ni1iO <= 0; ni1l <= 0; + ni1li <= 0; + ni1ll <= 0; + ni1lO <= 0; ni1O <= 0; + ni1Oi <= 0; + ni1Ol <= 0; + ni1OO <= 0; nii0i <= 0; nii0l <= 0; nii0O <= 0; @@ -321,29 +492,9 @@ module ip_fp_mul niiO <= 0; niiOi <= 0; niiOl <= 0; - niiOO <= 0; - nil0i <= 0; - nil0l <= 0; - nil0O <= 0; - nil1i <= 0; - nil1l <= 0; - nil1O <= 0; nili <= 0; - nilii <= 0; - nilil <= 0; - niliO <= 0; nill <= 0; - nilli <= 0; - nilll <= 0; - nillO <= 0; nilO <= 0; - nilOi <= 0; - nilOl <= 0; - nilOO <= 0; - niO0i <= 0; - niO1i <= 0; - niO1l <= 0; - niO1O <= 0; niOi <= 0; niOl <= 0; niOO <= 0; @@ -357,89 +508,143 @@ module ip_fp_mul nlil <= 0; nliO <= 0; nlli <= 0; + nllil <= 0; nlll <= 0; nllO <= 0; + nlO0O <= 0; nlOi <= 0; + nlOii <= 0; + nlOil <= 0; + nlOiO <= 0; nlOl <= 0; + nlOli <= 0; + nlOll <= 0; nlOlO <= 0; nlOO <= 0; + nlOOi <= 0; + nlOOl <= 0; + nlOOO <= 0; end else if (wire_n1l_ENA == 1'b1) begin + n00i <= wire_n00O_o[8]; + n00l <= wire_n0lO_o[0]; + n01i <= wire_n00O_o[5]; + n01l <= wire_n00O_o[6]; + n01O <= wire_n00O_o[7]; n0ii <= wire_n0lO_o[1]; + n0iiO <= n00Oi; n0il <= wire_n0lO_o[2]; + n0ili <= n0ill; + n0ill <= n0ilO; + n0ilO <= n0iiO; n0iO <= wire_n0lO_o[3]; + n0iOi <= a[10]; + n0iOl <= a[11]; + n0iOO <= a[12]; + n0l0i <= n0l0l; + n0l0l <= n0l1O; + n0l0O <= b[10]; + n0l1i <= a[13]; + n0l1l <= a[14]; + n0l1O <= n00lO; n0li <= wire_n0lO_o[4]; + n0lii <= b[11]; + n0lil <= b[12]; + n0liO <= b[13]; n0ll <= wire_n0lO_o[5]; + n0lli <= b[14]; + n0lll <= n00ll; + n0llO <= n0lOi; + n0lOi <= n0lll; + n0lOl <= n00li; + n0lOO <= n0O1i; + n0O0i <= n0O0l; + n0O0l <= n0O1O; + n0O0O <= n00il; + n0O1i <= n0O1l; + n0O1l <= n0lOl; + n0O1O <= n00iO; n0Oi <= wire_n0i_o[9]; + n0Oii <= n0Oil; + n0Oil <= n0O0O; + n0OiO <= ((n0i0O & n0llO) | (n0i0l & n0Oii)); n0Ol <= wire_n0i_o[10]; + n0Oli <= ((~ n0lOO) & n0O0i); + n0Oll <= ((~ n0ili) & n0l0i); + n0OlO <= (a[15] ^ b[15]); n0OO <= wire_n0i_o[11]; + n0OOi <= n0OOl; + n0OOl <= n0OOO; + n0OOO <= ni11i; + n11i <= wire_n00O_o[1]; n1i <= a[9]; - n1O <= ni1Oi; - ni00i <= ni1ii; - ni00l <= ni00O; - ni00O <= ni00i; + n1O <= n0i1O; + n1Oi <= wire_n00O_o[2]; + n1Ol <= wire_n00O_o[3]; + n1OO <= wire_n00O_o[4]; + ni00i <= (n0i0l & n0i1i); + ni00l <= (n0i0O & n0i0l); + ni00O <= ((~ wire_nllii_o[11]) & (n0i1l & n0i1i)); + ni01i <= ni1ii; + ni01l <= ((~ wire_nlO0i_o[11]) & (n0i1l & n0i1i)); + ni01O <= (n0i0O & n0i1l); ni0i <= wire_n0i_o[15]; - ni0ii <= a[10]; - ni0il <= a[11]; - ni0iO <= a[12]; + ni0ii <= (n0i1i & n0llO); + ni0il <= (n0i1l & n0Oii); + ni0iO <= (n0llO & n0Oii); ni0l <= wire_n0i_o[16]; - ni0li <= a[13]; - ni0ll <= a[14]; - ni0lO <= ni10O; + ni0li <= nii0l; + ni0ll <= nii0O; + ni0lO <= niiii; ni0O <= wire_n0i_o[17]; - ni0Oi <= ni0lO; - ni0Ol <= b[10]; - ni0OO <= b[11]; + ni0Oi <= niiil; + ni0Ol <= niiiO; + ni0OO <= niili; + ni10i <= wire_nlO0l_o[12]; + ni10l <= wire_nlO0l_o[13]; + ni10O <= wire_nlO0l_o[14]; + ni11i <= n0OlO; + ni11l <= nili; + ni11O <= wire_nlO0l_o[11]; ni1i <= wire_n0i_o[12]; + ni1ii <= wire_nlO0l_o[15]; + ni1il <= wire_nlO0l_o[16]; + ni1iO <= wire_nlO0l_o[17]; ni1l <= wire_n0i_o[13]; + ni1li <= wire_nlO0l_o[18]; + ni1ll <= wire_nlO0l_o[19]; + ni1lO <= ni11O; ni1O <= wire_n0i_o[14]; - nii0i <= ni10l; - nii0l <= nii0i; - nii0O <= ni10i; - nii1i <= b[12]; - nii1l <= b[13]; - nii1O <= b[14]; + ni1Oi <= ni10i; + ni1Ol <= ni10l; + ni1OO <= ni10O; + nii0i <= niiOl; + nii0l <= wire_nlO0l_o[1]; + nii0O <= wire_nlO0l_o[2]; + nii1i <= niill; + nii1l <= niilO; + nii1O <= niiOi; niii <= wire_n0i_o[18]; - niiii <= niiil; - niiil <= nii0O; - niiiO <= ni11O; + niiii <= wire_nlO0l_o[3]; + niiil <= wire_nlO0l_o[4]; + niiiO <= wire_nlO0l_o[5]; niil <= wire_n0i_o[19]; - niili <= niiiO; - niill <= ni11l; - niilO <= niill; + niili <= wire_nlO0l_o[6]; + niill <= wire_nlO0l_o[7]; + niilO <= wire_nlO0l_o[8]; niiO <= wire_n0i_o[20]; - niiOi <= (a[15] ^ b[15]); - niiOl <= niiOO; - niiOO <= niiOi; - nil0i <= wire_n1iO_o[14]; - nil0l <= wire_n1iO_o[15]; - nil0O <= wire_n1iO_o[16]; - nil1i <= wire_n1iO_o[11]; - nil1l <= wire_n1iO_o[12]; - nil1O <= wire_n1iO_o[13]; + niiOi <= wire_nlO0l_o[9]; + niiOl <= wire_nlO0l_o[10]; nili <= wire_n0i_o[21]; - nilii <= wire_n1iO_o[17]; - nilil <= wire_n1iO_o[18]; - niliO <= wire_n1iO_o[19]; nill <= b[0]; - nilli <= wire_n1iO_o[1]; - nilll <= wire_n1iO_o[2]; - nillO <= wire_n1iO_o[3]; nilO <= b[1]; - nilOi <= wire_n1iO_o[4]; - nilOl <= wire_n1iO_o[5]; - nilOO <= wire_n1iO_o[6]; - niO0i <= wire_n1iO_o[10]; - niO1i <= wire_n1iO_o[7]; - niO1l <= wire_n1iO_o[8]; - niO1O <= wire_n1iO_o[9]; niOi <= b[2]; niOl <= b[3]; niOO <= b[4]; nl0i <= b[8]; nl0l <= b[9]; - nl0O <= ni1Oi; + nl0O <= n0i1O; nl1i <= b[5]; nl1l <= b[6]; nl1O <= b[7]; @@ -447,30 +652,40 @@ module ip_fp_mul nlil <= a[1]; nliO <= a[2]; nlli <= a[3]; + nllil <= wire_n11l_dataout; nlll <= a[4]; nllO <= a[5]; + nlO0O <= wire_n11O_dataout; nlOi <= a[6]; + nlOii <= wire_n10i_dataout; + nlOil <= wire_n10l_dataout; + nlOiO <= wire_n10O_dataout; nlOl <= a[7]; - nlOlO <= wire_n0lO_o[0]; + nlOli <= wire_n1ii_dataout; + nlOll <= wire_n1il_dataout; + nlOlO <= wire_n1iO_dataout; nlOO <= a[8]; + nlOOi <= wire_n1li_dataout; + nlOOl <= wire_n1ll_dataout; + nlOOO <= wire_n1lO_dataout; end end assign wire_n1l_ENA = en[0]; - assign wire_n00i_dataout = ((~ nili) === 1'b1) ? niii : niil; - assign wire_n00l_dataout = ((~ nili) === 1'b1) ? niil : niiO; - assign wire_n01i_dataout = ((~ nili) === 1'b1) ? ni0i : ni0l; - assign wire_n01l_dataout = ((~ nili) === 1'b1) ? ni0l : ni0O; - assign wire_n01O_dataout = ((~ nili) === 1'b1) ? ni0O : niii; - assign wire_n1li_dataout = ((~ nili) === 1'b1) ? n0Oi : n0Ol; - assign wire_n1ll_dataout = ((~ nili) === 1'b1) ? n0Ol : n0OO; - assign wire_n1lO_dataout = ((~ nili) === 1'b1) ? n0OO : ni1i; - assign wire_n1Oi_dataout = ((~ nili) === 1'b1) ? ni1i : ni1l; - assign wire_n1Ol_dataout = ((~ nili) === 1'b1) ? ni1l : ni1O; - assign wire_n1OO_dataout = ((~ nili) === 1'b1) ? ni1O : ni0i; + assign wire_n10i_dataout = ((~ nili) === 1'b1) ? n0OO : ni1i; + assign wire_n10l_dataout = ((~ nili) === 1'b1) ? ni1i : ni1l; + assign wire_n10O_dataout = ((~ nili) === 1'b1) ? ni1l : ni1O; + assign wire_n11l_dataout = ((~ nili) === 1'b1) ? n0Oi : n0Ol; + assign wire_n11O_dataout = ((~ nili) === 1'b1) ? n0Ol : n0OO; + assign wire_n1ii_dataout = ((~ nili) === 1'b1) ? ni1O : ni0i; + assign wire_n1il_dataout = ((~ nili) === 1'b1) ? ni0i : ni0l; + assign wire_n1iO_dataout = ((~ nili) === 1'b1) ? ni0l : ni0O; + assign wire_n1li_dataout = ((~ nili) === 1'b1) ? ni0O : niii; + assign wire_n1ll_dataout = ((~ nili) === 1'b1) ? niii : niil; + assign wire_n1lO_dataout = ((~ nili) === 1'b1) ? niil : niiO; oper_add n00O ( - .a({{3{1'b0}}, n0ll, n0li, n0iO, n0il, n0ii, nlOlO, 1'b1}), + .a({{3{1'b0}}, n0ll, n0li, n0iO, n0il, n0ii, n00l, 1'b1}), .b({{5{1'b1}}, {4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), @@ -482,8 +697,8 @@ module ip_fp_mul n00O.width_o = 10; oper_add n0lO ( - .a({1'b0, ni0ll, ni0li, ni0iO, ni0il, ni0ii}), - .b({1'b0, nii1O, nii1l, nii1i, ni0OO, ni0Ol}), + .a({1'b0, n0l1l, n0l1i, n0iOO, n0iOl, n0iOi}), + .b({1'b0, n0lli, n0liO, n0lil, n0lii, n0l0O}), .cin(1'b0), .cout(), .o(wire_n0lO_o)); @@ -492,42 +707,42 @@ module ip_fp_mul n0lO.width_a = 6, n0lO.width_b = 6, n0lO.width_o = 6; - oper_add n1il + oper_add nllii ( - .a({{3{niliO}}, nilil, nilii, nil0O, nil0l, nil0i, nil1O, nil1l, nil1i, 1'b1}), - .b({{6{1'b1}}, {5{1'b0}}, 1'b1}), + .a({{3{(~ ni1ll)}}, (~ ni1li), (~ ni1iO), (~ ni1il), (~ ni1ii), (~ ni10O), (~ ni10l), (~ ni10i), (~ ni11O), 1'b1}), + .b({{11{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_n1il_o)); + .o(wire_nllii_o)); defparam - n1il.sgate_representation = 0, - n1il.width_a = 12, - n1il.width_b = 12, - n1il.width_o = 12; - oper_add n1iO + nllii.sgate_representation = 0, + nllii.width_a = 12, + nllii.width_b = 12, + nllii.width_o = 12; + oper_add nlO0i ( - .a({{2{wire_n00O_o[8]}}, wire_n00O_o[8:1], wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout, wire_n1li_dataout}), - .b({{9{1'b0}}, nili, {10{1'b0}}, 1'b1}), + .a({{3{ni1ll}}, ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni10i, ni11O, 1'b1}), + .b({{6{1'b1}}, {5{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_n1iO_o)); + .o(wire_nlO0i_o)); defparam - n1iO.sgate_representation = 0, - n1iO.width_a = 21, - n1iO.width_b = 21, - n1iO.width_o = 21; - oper_add nlOll + nlO0i.sgate_representation = 0, + nlO0i.width_a = 12, + nlO0i.width_b = 12, + nlO0i.width_o = 12; + oper_add nlO0l ( - .a({{3{(~ niliO)}}, (~ nilil), (~ nilii), (~ nil0O), (~ nil0l), (~ nil0i), (~ nil1O), (~ nil1l), (~ nil1i), 1'b1}), - .b({{11{1'b0}}, 1'b1}), + .a({{3{n00i}}, n01O, n01l, n01i, n1OO, n1Ol, n1Oi, n11i, nlOOO, nlOOl, nlOOi, nlOlO, nlOll, nlOli, nlOiO, nlOil, nlOii, nlO0O, nllil}), + .b({{9{1'b0}}, ni11l, {10{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_nlOll_o)); + .o(wire_nlO0l_o)); defparam - nlOll.sgate_representation = 0, - nlOll.width_a = 12, - nlOll.width_b = 12, - nlOll.width_o = 12; + nlO0l.sgate_representation = 0, + nlO0l.width_a = 21, + nlO0l.width_b = 21, + nlO0l.width_o = 21; oper_mult n0i ( .a({n1O, n1i, nlOO, nlOl, nlOi, nllO, nlll, nlli, nliO, nlil, nlii}), @@ -538,159 +753,158 @@ module ip_fp_mul n0i.width_a = 11, n0i.width_b = 11, n0i.width_o = 22; - oper_mux nll0i + oper_mux nl0lO ( - .data({{2{1'b0}}, nillO, 1'b0}), - .o(wire_nll0i_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({1'b1, 1'b0, ni0li, 1'b0}), + .o(wire_nl0lO_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nll0i.width_data = 4, - nll0i.width_sel = 2; - oper_mux nll0l + nl0lO.width_data = 4, + nl0lO.width_sel = 2; + oper_mux nl0Oi ( - .data({{2{1'b0}}, nilOi, 1'b0}), - .o(wire_nll0l_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, ni0ll, 1'b0}), + .o(wire_nl0Oi_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nll0l.width_data = 4, - nll0l.width_sel = 2; - oper_mux nll0O + nl0Oi.width_data = 4, + nl0Oi.width_sel = 2; + oper_mux nl0Ol ( - .data({{2{1'b0}}, nilOl, 1'b0}), - .o(wire_nll0O_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, ni0lO, 1'b0}), + .o(wire_nl0Ol_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nll0O.width_data = 4, - nll0O.width_sel = 2; - oper_mux nll1l + nl0Ol.width_data = 4, + nl0Ol.width_sel = 2; + oper_mux nl0OO ( - .data({1'b1, 1'b0, nilli, 1'b0}), - .o(wire_nll1l_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, ni0Oi, 1'b0}), + .o(wire_nl0OO_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nll1l.width_data = 4, - nll1l.width_sel = 2; - oper_mux nll1O + nl0OO.width_data = 4, + nl0OO.width_sel = 2; + oper_mux nli0i ( - .data({{2{1'b0}}, nilll, 1'b0}), - .o(wire_nll1O_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, nii1l, 1'b0}), + .o(wire_nli0i_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nll1O.width_data = 4, - nll1O.width_sel = 2; - oper_mux nllii + nli0i.width_data = 4, + nli0i.width_sel = 2; + oper_mux nli0l ( - .data({{2{1'b0}}, nilOO, 1'b0}), - .o(wire_nllii_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, nii1O, 1'b0}), + .o(wire_nli0l_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nllii.width_data = 4, - nllii.width_sel = 2; - oper_mux nllil + nli0l.width_data = 4, + nli0l.width_sel = 2; + oper_mux nli0O ( - .data({{2{1'b0}}, niO1i, 1'b0}), - .o(wire_nllil_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, nii0i, 1'b0}), + .o(wire_nli0O_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nllil.width_data = 4, - nllil.width_sel = 2; - oper_mux nlliO + nli0O.width_data = 4, + nli0O.width_sel = 2; + oper_mux nli1i ( - .data({{2{1'b0}}, niO1l, 1'b0}), - .o(wire_nlliO_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, ni0Ol, 1'b0}), + .o(wire_nli1i_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nlliO.width_data = 4, - nlliO.width_sel = 2; - oper_mux nllli + nli1i.width_data = 4, + nli1i.width_sel = 2; + oper_mux nli1l ( - .data({{2{1'b0}}, niO1O, 1'b0}), - .o(wire_nllli_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, ni0OO, 1'b0}), + .o(wire_nli1l_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nllli.width_data = 4, - nllli.width_sel = 2; - oper_mux nllll + nli1l.width_data = 4, + nli1l.width_sel = 2; + oper_mux nli1O ( - .data({{2{1'b0}}, niO0i, 1'b0}), - .o(wire_nllll_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b0}}, nii1i, 1'b0}), + .o(wire_nli1O_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nllll.width_data = 4, - nllll.width_sel = 2; - oper_mux nlllO + nli1O.width_data = 4, + nli1O.width_sel = 2; + oper_mux nliii ( - .data({{2{1'b1}}, nil1i, 1'b0}), - .o(wire_nlllO_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b1}}, ni1lO, 1'b0}), + .o(wire_nliii_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nlllO.width_data = 4, - nlllO.width_sel = 2; - oper_mux nllOi + nliii.width_data = 4, + nliii.width_sel = 2; + oper_mux nliil ( - .data({{2{1'b1}}, nil1l, 1'b0}), - .o(wire_nllOi_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b1}}, ni1Oi, 1'b0}), + .o(wire_nliil_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nllOi.width_data = 4, - nllOi.width_sel = 2; - oper_mux nllOl + nliil.width_data = 4, + nliil.width_sel = 2; + oper_mux nliiO ( - .data({{2{1'b1}}, nil1O, 1'b0}), - .o(wire_nllOl_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b1}}, ni1Ol, 1'b0}), + .o(wire_nliiO_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nllOl.width_data = 4, - nllOl.width_sel = 2; - oper_mux nllOO + nliiO.width_data = 4, + nliiO.width_sel = 2; + oper_mux nlili ( - .data({{2{1'b1}}, nil0i, 1'b0}), - .o(wire_nllOO_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b1}}, ni1OO, 1'b0}), + .o(wire_nlili_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nllOO.width_data = 4, - nllOO.width_sel = 2; - oper_mux nlO1i + nlili.width_data = 4, + nlili.width_sel = 2; + oper_mux nlill ( - .data({{2{1'b1}}, nil0l, 1'b0}), - .o(wire_nlO1i_o), - .sel({wire_nlO1O_o, wire_nlO1l_o})); + .data({{2{1'b1}}, ni01i, 1'b0}), + .o(wire_nlill_o), + .sel({wire_nliOi_o, wire_nlilO_o})); defparam - nlO1i.width_data = 4, - nlO1i.width_sel = 2; - oper_mux nlO1l + nlill.width_data = 4, + nlill.width_sel = 2; + oper_mux nlilO ( .data({{3{1'b0}}, 1'b1}), - .o(wire_nlO1l_o), - .sel({ni1iO, ni1il})); + .o(wire_nlilO_o), + .sel({n00OO, n00Ol})); defparam - nlO1l.width_data = 4, - nlO1l.width_sel = 2; - oper_mux nlO1O + nlilO.width_data = 4, + nlilO.width_sel = 2; + oper_mux nliOi ( .data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}}), - .o(wire_nlO1O_o), - .sel({ni1Ol, ni1iO, ni1il})); + .o(wire_nliOi_o), + .sel({n0i0i, n00OO, n00Ol})); defparam - nlO1O.width_data = 8, - nlO1O.width_sel = 3; + nliOi.width_data = 8, + nliOi.width_sel = 3; assign - ni01i = (ni00l & ni0Oi), - ni10i = ((((((((((~ b[0]) & (~ b[1])) & (~ b[2])) & (~ b[3])) & (~ b[4])) & (~ b[5])) & (~ b[6])) & (~ b[7])) & (~ b[8])) & (~ b[9])), - ni10l = (((((~ nii1O) & (~ nii1l)) & (~ nii1i)) & (~ ni0OO)) & (~ ni0Ol)), - ni10O = ((((ni0ll & ni0li) & ni0iO) & ni0il) & ni0ii), - ni11l = (((((~ ni0ll) & (~ ni0li)) & (~ ni0iO)) & (~ ni0il)) & (~ ni0ii)), - ni11O = ((((nii1O & nii1l) & nii1i) & ni0OO) & ni0Ol), - ni1ii = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])), - ni1il = ((ni1li & (~ wire_nlOll_o[11])) | ((ni1ll & nii0l) | ((ni1lO & niilO) | (nii0l & niilO)))), - ni1iO = (((~ wire_n1il_o[11]) & ni1li) | ((ni01i & ni1lO) | ((ni1OO & ni1ll) | (ni01i & ni1OO)))), - ni1li = (ni1lO & ni1ll), - ni1ll = ((~ ni0Oi) & (~ niilO)), - ni1lO = ((~ nii0l) & (~ niili)), - ni1Oi = 1'b1, - ni1Ol = (((ni01i & nii0l) | (ni1OO & niilO)) | (((~ niiii) & niili) | ((~ ni00l) & ni0Oi))), - ni1OO = (niiii & niili), - q = {((~ ni1Ol) & niiOl), wire_nlO1i_o, wire_nllOO_o, wire_nllOl_o, wire_nllOi_o, wire_nlllO_o, wire_nllll_o, wire_nllli_o, wire_nlliO_o, wire_nllil_o, wire_nllii_o, wire_nll0O_o, wire_nll0l_o, wire_nll0i_o, wire_nll1O_o, wire_nll1l_o}; + n00il = (((((~ n0l1l) & (~ n0l1i)) & (~ n0iOO)) & (~ n0iOl)) & (~ n0iOi)), + n00iO = ((((n0lli & n0liO) & n0lil) & n0lii) & n0l0O), + n00li = ((((((((((~ b[0]) & (~ b[1])) & (~ b[2])) & (~ b[3])) & (~ b[4])) & (~ b[5])) & (~ b[6])) & (~ b[7])) & (~ b[8])) & (~ b[9])), + n00ll = (((((~ n0lli) & (~ n0liO)) & (~ n0lil)) & (~ n0lii)) & (~ n0l0O)), + n00lO = ((((n0l1l & n0l1i) & n0iOO) & n0iOl) & n0iOi), + n00Oi = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])), + n00Ol = (((ni0il | ni0iO) | ni0ii) | ni00O), + n00OO = (((ni00i | ni00l) | ni01O) | ni01l), + n0i0i = ((n0Oli | n0Oll) | n0OiO), + n0i0l = (n0lOO & n0O0i), + n0i0O = (n0ili & n0l0i), + n0i1i = ((~ n0l0i) & (~ n0Oii)), + n0i1l = ((~ n0llO) & (~ n0O0i)), + n0i1O = 1'b1, + q = {((~ n0i0i) & n0OOi), wire_nlill_o, wire_nlili_o, wire_nliiO_o, wire_nliil_o, wire_nliii_o, wire_nli0O_o, wire_nli0l_o, wire_nli0i_o, wire_nli1O_o, wire_nli1l_o, wire_nli1i_o, wire_nl0OO_o, wire_nl0Ol_o, wire_nl0Oi_o, wire_nl0lO_o}; endmodule //ip_fp_mul //synopsys translate_on //VALID FILE diff --git a/ip/ip_fp_mul_sim/mentor/msim_setup.tcl b/ip/ip_fp_mul_sim/mentor/msim_setup.tcl index 14c829b..7cd5cfa 100644 --- a/ip/ip_fp_mul_sim/mentor/msim_setup.tcl +++ b/ip/ip_fp_mul_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:27:56 +# ACDS 20.1 720 linux 2023.10.26.05:48:32 # ---------------------------------------- # Initialize variables diff --git a/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh b/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh index 6bf2ad9..57f942b 100755 --- a/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh +++ b/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.20:27:56 +# ACDS 20.1 720 linux 2023.10.26.05:48:33 # ---------------------------------------- # vcs - auto-generated simulation script @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:27:56 +# ACDS 20.1 720 linux 2023.10.26.05:48:33 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_mul" diff --git a/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh index 8f56686..fb41af0 100755 --- a/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.20:27:56 +# ACDS 20.1 720 linux 2023.10.26.05:48:33 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:27:56 +# ACDS 20.1 720 linux 2023.10.26.05:48:33 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_mul" diff --git a/platform.qsys b/platform.qsys index f0724b0..21cc3e9 100644 --- a/platform.qsys +++ b/platform.qsys @@ -1491,11 +1491,6 @@ <parameter name="baseAddress" value="0x30020000" /> <parameter name="defaultConnection" value="false" /> </connection> - <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="vram.s1"> - <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x38000000" /> - <parameter name="defaultConnection" value="false" /> - </connection> <connection kind="avalon" version="20.1" @@ -1692,7 +1687,6 @@ end="hps_0.f2h_sdram0_clock" /> <connection kind="clock" version="20.1" start="pll_0.outclk1" end="mm_bridge.clk" /> <connection kind="clock" version="20.1" start="pll_0.outclk1" end="smp_0.clock" /> - <connection kind="clock" version="20.1" start="pll_0.outclk1" end="gfx_0.clock" /> <connection kind="clock" version="20.1" @@ -1757,6 +1751,11 @@ kind="clock" version="20.1" start="sys_sdram_pll_0.sys_clk" + end="gfx_0.clock" /> + <connection + kind="clock" + version="20.1" + start="sys_sdram_pll_0.sys_clk" end="pixfifo.clock_stream_in" /> <connection kind="clock" version="20.1" start="video_pll_0.vga_clk" end="vga.clk" /> <connection diff --git a/rtl/gfx/gfx_defs.sv b/rtl/gfx/gfx_defs.sv index 648f9e6..b1f8bb8 100644 --- a/rtl/gfx/gfx_defs.sv +++ b/rtl/gfx/gfx_defs.sv @@ -6,9 +6,9 @@ `define FLOATS_PER_VEC 4 `define VECS_PER_MAT 4 -// Target de 100MHz con float16, rounding aproximado -`define FP_ADD_STAGES 4 // ~325 LUTs -`define FP_MUL_STAGES 3 // ~119 LUTs ~1 bloque DSP +// Target de 200MHz (reloj es 143MHz) con float16, rounding aproximado +`define FP_ADD_STAGES 10 // ~401 LUTs +`define FP_MUL_STAGES 5 // ~144 LUTs ~1 bloque DSP typedef logic[`FLOAT_BITS - 1:0] fp; typedef fp vec2[2]; |