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| author | Alejandro Soto <alejandro@34project.org> | 2022-12-08 19:30:32 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-08 19:30:32 -0600 |
| commit | 2cbccf921bf84665c55cea67b81f31c66dde4249 (patch) | |
| tree | 2f8bc64c61f80f7e264846abaccff2a44807a5bf | |
| parent | 357acc5d82a2b04cf846d69826ec89671e78e759 (diff) | |
Fix decoding of msr with immediate operand
| -rw-r--r-- | rtl/core/decode/isa.sv | 2 | ||||
| -rw-r--r-- | tb/sim/modeswitch.S | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/rtl/core/decode/isa.sv b/rtl/core/decode/isa.sv index 4c9f316..2ad5b40 100644 --- a/rtl/core/decode/isa.sv +++ b/rtl/core/decode/isa.sv @@ -195,7 +195,7 @@ `define INSN_MSR_IMM 28'b0_0_1_1_0_?_1_0_????_1111_????_???????? `define INSN_MSR_REG 28'b0_0_0_1_0_?_1_0_????_1111_0000_0000_???? -`define GROUP_MSR 28'b0_0_?_1_0_?_1_0_????_1111_0000_0000_???? +`define GROUP_MSR `INSN_MSR_IMM, `INSN_MSR_REG `define FIELD_MRS_R [22] `define FIELD_MRS_RD [15:12] diff --git a/tb/sim/modeswitch.S b/tb/sim/modeswitch.S index 52908de..384eb65 100644 --- a/tb/sim/modeswitch.S +++ b/tb/sim/modeswitch.S @@ -1,6 +1,7 @@ .global reset reset: mov r6, lr + msr cpsr_c, #0xd3 mrs r0, cpsr udf mrs r2, cpsr |