Add new toplevel signals

2 files changed, 49 insertions, 20 deletions

diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 50b9cd8..940e46a 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -16,7 +16,17 @@ module conspiracion
 	inout  wire        memory_mem_dqs_n,
 	output wire        memory_mem_odt,
 	output wire        memory_mem_dm,
-	input  wire        memory_oct_rzqin
+	input  wire        memory_oct_rzqin,
+	output wire [12:0] vram_wire_addr,
+	output wire [1:0]  vram_wire_ba,
+	output wire        vram_wire_cas_n,
+	output wire        vram_wire_cke,
+	output wire        vram_wire_cs_n,
+	inout  wire [15:0] vram_wire_dq,
+	output wire [1:0]  vram_wire_dqm,
+	output wire        vram_wire_ras_n,
+	output wire        vram_wire_we_n
+
 );
 
 	//TODO
@@ -25,7 +35,7 @@ module conspiracion
 
 	logic[29:0] addr;
 	logic[31:0] data_rd, data_wr;
-	logic ready, write, start;
+	logic clk_core, ready, write, start;
 
 	arm810 core
 	(
@@ -38,6 +48,9 @@ module conspiracion
 		.bus_start(start)
 	);
 
+	//TODO: pio_0_external_connection_export,
+	//TODO: pll_0_outclk3_clk,
+
 	platform plat
 	(
 		.master_0_core_addr(addr),
@@ -46,6 +59,8 @@ module conspiracion
 		.master_0_core_ready(ready),
 		.master_0_core_write(write),
 		.master_0_core_start(start),
+		.pll_0_outclk3_clk(),
+		.pio_0_external_connection_export(),
 		.*
 	);
 
diff --git a/tb/platform.sv b/tb/platform.sv
index 3d2521b..06c6ad1 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -1,28 +1,42 @@
+
+
+
 module platform (
-		input  wire        clk_clk,               //           clk.clk
+		input  wire        clk_clk,                          //                       clk.clk
 		input  wire [29:0] master_0_core_addr    /*verilator public*/,// master_0_core.addr
 		output wire [31:0] master_0_core_data_rd /*verilator public*/,//              .data_rd
 		input  wire [31:0] master_0_core_data_wr /*verilator public*/,//              .data_wr
 		output wire        master_0_core_ready   /*verilator public*/,//              .ready
 		input  wire        master_0_core_write   /*verilator public*/,//              .write
 		input  wire        master_0_core_start   /*verilator public*/,//              .start
-		output wire [12:0] memory_mem_a,          //        memory.mem_a
-		output wire [2:0]  memory_mem_ba,         //              .mem_ba
-		output wire        memory_mem_ck,         //              .mem_ck
-		output wire        memory_mem_ck_n,       //              .mem_ck_n
-		output wire        memory_mem_cke,        //              .mem_cke
-		output wire        memory_mem_cs_n,       //              .mem_cs_n
-		output wire        memory_mem_ras_n,      //              .mem_ras_n
-		output wire        memory_mem_cas_n,      //              .mem_cas_n
-		output wire        memory_mem_we_n,       //              .mem_we_n
-		output wire        memory_mem_reset_n,    //              .mem_reset_n
-		inout  wire [7:0]  memory_mem_dq,         //              .mem_dq
-		inout  wire        memory_mem_dqs,        //              .mem_dqs
-		inout  wire        memory_mem_dqs_n,      //              .mem_dqs_n
-		output wire        memory_mem_odt,        //              .mem_odt
-		output wire        memory_mem_dm,         //              .mem_dm
-		input  wire        memory_oct_rzqin,      //              .oct_rzqin
-		input  wire        reset_reset_n          //         reset.reset_n
+		output wire [12:0] memory_mem_a,                     //                    memory.mem_a
+		output wire [2:0]  memory_mem_ba,                    //                          .mem_ba
+		output wire        memory_mem_ck,                    //                          .mem_ck
+		output wire        memory_mem_ck_n,                  //                          .mem_ck_n
+		output wire        memory_mem_cke,                   //                          .mem_cke
+		output wire        memory_mem_cs_n,                  //                          .mem_cs_n
+		output wire        memory_mem_ras_n,                 //                          .mem_ras_n
+		output wire        memory_mem_cas_n,                 //                          .mem_cas_n
+		output wire        memory_mem_we_n,                  //                          .mem_we_n
+		output wire        memory_mem_reset_n,               //                          .mem_reset_n
+		inout  wire [7:0]  memory_mem_dq,                    //                          .mem_dq
+		inout  wire        memory_mem_dqs,                   //                          .mem_dqs
+		inout  wire        memory_mem_dqs_n,                 //                          .mem_dqs_n
+		output wire        memory_mem_odt,                   //                          .mem_odt
+		output wire        memory_mem_dm,                    //                          .mem_dm
+		input  wire        memory_oct_rzqin,                 //                          .oct_rzqin
+		output wire [7:0]  pio_0_external_connection_export, // pio_0_external_connection.export
+		output wire        pll_0_outclk3_clk,                //             pll_0_outclk3.clk
+		input  wire        reset_reset_n,                    //                     reset.reset_n
+		output wire [12:0] vram_wire_addr,                   //                 vram_wire.addr
+		output wire [1:0]  vram_wire_ba,                     //                          .ba
+		output wire        vram_wire_cas_n,                  //                          .cas_n
+		output wire        vram_wire_cke,                    //                          .cke
+		output wire        vram_wire_cs_n,                   //                          .cs_n
+		inout  wire [15:0] vram_wire_dq,                     //                          .dq
+		output wire [1:0]  vram_wire_dqm,                    //                          .dqm
+		output wire        vram_wire_ras_n,                  //                          .ras_n
+		output wire        vram_wire_we_n                    //                          .we_n
 	);
 
 	logic[31:0] avl_address /*verilator public*/;