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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-16 00:14:47 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-16 00:29:28 -0600 |
| commit | 743b5ca25567199b95018127606c0ebaa56ad24c (patch) | |
| tree | 311e5fc62519e3213180c7f8d120bd1c0461096b | |
| parent | 86903ec40acd3014861d856660a27f6a131d8ca3 (diff) | |
Add sim test: subword
| -rw-r--r-- | tb/sim/subword.S | 16 | ||||
| -rw-r--r-- | tb/sim/subword.py | 8 |
2 files changed, 24 insertions, 0 deletions
diff --git a/tb/sim/subword.S b/tb/sim/subword.S new file mode 100644 index 0000000..82604ae --- /dev/null +++ b/tb/sim/subword.S @@ -0,0 +1,16 @@ +.global reset + +reset: + ldr r0, =0x01234567 + push {r0} + ldr r0, =0x89ab + ldrb r1, [sp, #2] + strh r0, [sp, #2] + mov r2, #0xcd + strb r2, [sp] + ldr r0, [sp] + ldrsb r2, [sp] + ldrb r3, [sp] + ldrsb r4, [sp, #1]! + ldrsh r5, [sp, #1] + mov pc, lr diff --git a/tb/sim/subword.py b/tb/sim/subword.py new file mode 100644 index 0000000..4292d6d --- /dev/null +++ b/tb/sim/subword.py @@ -0,0 +1,8 @@ +def final(): + assert_reg(r0, 0x89ab45cd) + assert_reg(r1, 0x23) + assert_reg(r2, 0xffffffcd) + assert_reg(r3, 0xcd) + assert_reg(r4, 0x00000045) + assert_reg(r5, 0xffff89ab) + assert_reg(sp_svc, 0x2000_0000 - 3) |