Implement initial state randomization in sim

6 files changed, 45 insertions, 9 deletions

diff --git a/Makefile b/Makefile
index b48dac1..66e9ff7 100644
--- a/Makefile
+++ b/Makefile
@@ -63,4 +63,7 @@ $(OBJ_DIR)/%.mk: \
   $$(shell find $(TB_DIR)/top/$$(dir $$*) -type f -name '*.cpp' 2>/dev/null)
 
 	mkdir -p $(dir $@)
-	$(VERILATOR) -O3 --cc --exe --trace -y $(RTL_DIR) --Mdir $(dir $@) --top $(word 1,$(subst /, ,$*)) $(patsubst tb/%,../tb/%,$^)
+	$(VERILATOR) \
+		-O3 --cc --exe --trace -y $(RTL_DIR) --Mdir $(dir $@) \
+		--top $(word 1,$(subst /, ,$*)) $(patsubst tb/%,../tb/%,$^) \
+		--x-assign unique --x-initial unique
diff --git a/conspiracion.qsf b/conspiracion.qsf
index ee6ccf8..92d47c6 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -109,7 +109,7 @@ set_global_assignment -name ECO_REGENERATE_REPORT ON
 
 set_location_assignment PIN_AF14 -to clk_clk
 
-set_location_assignment PIN_AB12 -to debug
+set_location_assignment PIN_AB12 -to reset_reset_n
 
 set_location_assignment PIN_V16 -to pio_leds[0]
 set_location_assignment PIN_W16 -to pio_leds[1]
@@ -344,4 +344,4 @@ set_global_assignment -name SIP_FILE ip/dsp_mul.sip
 
 
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/tb/avalon.impl.hpp b/tb/avalon.impl.hpp
index 6864c6d..f701e73 100644
--- a/tb/avalon.impl.hpp
+++ b/tb/avalon.impl.hpp
@@ -24,6 +24,17 @@ namespace taller::avalon
 	template<class Platform>
 	void interconnect<Platform>::tick(bool clk)
 	{
+		if(!plat.reset_reset_n) [[unlikely]]
+		{
+			active = nullptr;
+			avl_read = false;
+			avl_write = false;
+			avl_address = 0;
+			avl_writedata = 0;
+			avl_byteenable = 0;
+			return;
+		}
+
 		if(active)
 		{
 			assert(avl_address == plat.avl_address);
diff --git a/tb/platform.sv b/tb/platform.sv
index a2820fa..a43af19 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -30,7 +30,7 @@ module platform
 	input  wire        memory_oct_rzqin,                 //                          .oct_rzqin
 	output wire [7:0]  pio_0_external_connection_export, // pio_0_external_connection.export
 	output wire        pll_0_outclk3_clk,                //             pll_0_outclk3.clk
-	input  wire        reset_reset_n,                    //                     reset.reset_n
+	input  wire        reset_reset_n /*verilator public*/,//                     reset.reset_n
 	output wire [12:0] vram_wire_addr,                   //                 vram_wire.addr
 	output wire [1:0]  vram_wire_ba,                     //                          .ba
 	output wire        vram_wire_cas_n,                  //                          .cas_n
diff --git a/tb/sim/sim.py b/tb/sim/sim.py
index cc1f205..4e0bdf1 100755
--- a/tb/sim/sim.py
+++ b/tb/sim/sim.py
@@ -1,11 +1,13 @@
 #!/usr/bin/env python3
 
-import importlib.util, os, pathlib, subprocess, sys
+import importlib.util, os, pathlib, random, subprocess, sys
 
 module_path, verilated, image = sys.argv[1:]
 test_name = pathlib.Path(module_path).stem
 module = None
 
+seed = os.getenv('SIM_SEED', str(random.randint(0, 0x7fff_ffff)))
+
 all_regs = [
     ('r0', 'r0'),
     ('r1', 'r1'),
@@ -123,7 +125,14 @@ COLOR_YELLOW = '\033[33;1m'
 COLOR_BLUE   = '\033[34;1m'
 
 def exit(*, success):
-    status, color = ('passed', COLOR_GREEN) if success else ('failed', COLOR_RED)
+    global seed
+
+    if not success:
+        while_running()
+        if exec_args:
+            print('cmdline:', subprocess.list2cmdline(exec_args), file=sys.stderr)
+
+    status, color = ('passed', COLOR_GREEN) if success else (f'failed (seed: {seed})', COLOR_RED)
     print( \
         f'{color}Test \'{COLOR_YELLOW}{test_name}{COLOR_RESET}{color}\' ' +
         f'{status}{COLOR_RESET}', file=sys.stderr)
@@ -164,9 +173,6 @@ def test_assert(condition, message):
         while_running()
         print(f'{COLOR_RED}{message()}{COLOR_RESET}', file=sys.stderr)
 
-        if exec_args:
-            print('cmdline:', subprocess.list2cmdline(exec_args), file=sys.stderr)
-
         if regs:
             dump_regs()
 
@@ -258,6 +264,8 @@ for r, value in init_regs.items():
 init_regs = None
 exec_args.append(image)
 
+exec_args.extend([f'+verilator+seed+{seed}', '+verilator+rand+reset+2'])
+
 output = subprocess.run(exec_args, stdout=subprocess.PIPE, text=True)
 if output.returncode != 0:
     exit(success=False)
diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp
index c671e77..b73bd4b 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion.cpp
@@ -116,6 +116,16 @@ int main(int argc, char **argv)
 
 	Verilated::commandArgs(argc, argv);
 
+	for(char **arg = argv; *arg; ++arg)
+	{
+		if(**arg == '+')
+		{
+			*arg = NULL;
+			argc = arg - argv;
+			break;
+		}
+	}
+
 	args::ArgumentParser parser("Simulador proyecto final CE3201");
 
 	args::ValueFlagList<reg_init> init_regs
@@ -220,6 +230,10 @@ int main(int argc, char **argv)
 		tick();
 	};
 
+	top.reset_reset_n = 0;
+	cycle();
+	top.reset_reset_n = 1;
+
 	for(unsigned i = 0; i < *cycles; ++i)
 	{
 		cycle();