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authorAlejandro Soto <alejandro@34project.org>2022-11-06 11:45:08 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-06 11:45:08 -0600
commitff5f2a94c06ce3af9cc04033220dcd0f6c8826e3 (patch)
tree449d1ebf4c8574bff55f356f6a9732d869f84a30
parent543f9de75d19eb34c386ad25662beb8dd2aed5c4 (diff)
Add dsp_mul IP variation
Diffstat (limited to '')
-rw-r--r--.gitignore1
-rw-r--r--conspiracion.qsf4
-rw-r--r--ip/dsp_mul.cmp14
-rw-r--r--ip/dsp_mul.ppf18
-rw-r--r--ip/dsp_mul.qip273
-rw-r--r--ip/dsp_mul.sip6
-rw-r--r--ip/dsp_mul.spd6
-rw-r--r--ip/dsp_mul.v181
-rw-r--r--ip/dsp_mul/dsp_mul_0002.v338
-rw-r--r--ip/dsp_mul_sim.f1
-rw-r--r--ip/dsp_mul_sim/aldec/rivierapro_setup.tcl278
-rw-r--r--ip/dsp_mul_sim/cadence/cds.lib19
-rw-r--r--ip/dsp_mul_sim/cadence/hdl.var2
-rwxr-xr-xip/dsp_mul_sim/cadence/ncsim_setup.sh195
-rw-r--r--ip/dsp_mul_sim/dsp_mul.v338
-rw-r--r--ip/dsp_mul_sim/mentor/msim_setup.tcl272
-rwxr-xr-xip/dsp_mul_sim/synopsys/vcs/vcs_setup.sh152
-rw-r--r--ip/dsp_mul_sim/synopsys/vcsmx/synopsys_sim.setup12
-rwxr-xr-xip/dsp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh195
19 files changed, 2304 insertions, 1 deletions
diff --git a/.gitignore b/.gitignore
index 04fbdeb..c204d2d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -41,3 +41,4 @@ platform.sopcinfo
hps_isw_handoff/
*~
*.vcd
+qmegawiz_errors_log.txt
diff --git a/conspiracion.qsf b/conspiracion.qsf
index 7cc2838..2585fd3 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -264,4 +264,6 @@ set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name QIP_FILE ip/dsp_mul.qip
+set_global_assignment -name SIP_FILE ip/dsp_mul.sip \ No newline at end of file
diff --git a/ip/dsp_mul.cmp b/ip/dsp_mul.cmp
new file mode 100644
index 0000000..e14f012
--- /dev/null
+++ b/ip/dsp_mul.cmp
@@ -0,0 +1,14 @@
+ component dsp_mul is
+ port (
+ result : out std_logic_vector(63 downto 0); -- result
+ dataa_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- dataa_0
+ datab_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- datab_0
+ signa : in std_logic := 'X'; -- signa
+ signb : in std_logic := 'X'; -- signb
+ clock0 : in std_logic := 'X'; -- clock0
+ ena0 : in std_logic := 'X'; -- ena0
+ aclr0 : in std_logic := 'X'; -- aclr0
+ chainin : in std_logic_vector(63 downto 0) := (others => 'X') -- chainin
+ );
+ end component dsp_mul;
+
diff --git a/ip/dsp_mul.ppf b/ip/dsp_mul.ppf
new file mode 100644
index 0000000..2d04f68
--- /dev/null
+++ b/ip/dsp_mul.ppf
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan
+ variation_name="dsp_mul"
+ megafunction_name="ALTERA_MULT_ADD"
+ intended_family="Cyclone V"
+ specifies="all_ports">
+ <global>
+ <pin name="result[63..0]" direction="output" scope="external" />
+ <pin name="dataa_0[31..0]" direction="input" scope="external" />
+ <pin name="datab_0[31..0]" direction="input" scope="external" />
+ <pin name="signa" direction="input" scope="external" />
+ <pin name="signb" direction="input" scope="external" />
+ <pin name="clock0" direction="input" scope="external" />
+ <pin name="ena0" direction="input" scope="external" />
+ <pin name="aclr0" direction="input" scope="external" />
+ <pin name="chainin[63..0]" direction="input" scope="external" />
+ </global>
+</pinplan>
diff --git a/ip/dsp_mul.qip b/ip/dsp_mul.qip
new file mode 100644
index 0000000..f61b2fe
--- /dev/null
+++ b/ip/dsp_mul.qip
@@ -0,0 +1,273 @@
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_TOOL_NAME "altera_mult_add"
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "dsp_mul" -name MISC_FILE [file join $::quartus(qip_path) "dsp_mul.cmp"]
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_COMPONENT_NAME "ZHNwX211bA=="
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_COMPONENT_DISPLAY_NAME "TXVsdGlwbHkgQWRkZXIgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "dsp_mul" -library "dsp_mul" -name IP_COMPONENT_DESCRIPTION "VGhlIEFMVEVSQV9NVUxUX0FERCBtZWdhZnVuY3Rpb24gYWxsb3dzIHlvdSB0byBpbXBsZW1lbnQgYSBtdWx0aXBsaWVyLWFkZGVy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_NAME "ZHNwX211bF8wMDAy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_DISPLAY_NAME "TXVsdGlwbHkgQWRkZXIgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_DESCRIPTION "VGhlIEFMVEVSQV9NVUxUX0FERCBtZWdhZnVuY3Rpb24gYWxsb3dzIHlvdSB0byBpbXBsZW1lbnQgYSBtdWx0aXBsaWVyLWFkZGVy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX211bHRpcGxpZXJz::MQ==::V2hhdCBpcyB0aGUgbnVtYmVyIG9mIG11bHRpcGxpZXJzPw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "d2lkdGhfYQ==::MzI=::SG93IHdpZGUgc2hvdWxkIHRoZSBBIGlucHV0IGJ1c2VzIGJlPw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "d2lkdGhfYg==::MzI=::SG93IHdpZGUgc2hvdWxkIHRoZSBCIGlucHV0IGJ1c2VzIGJlPw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "d2lkdGhfcmVzdWx0::NjQ=::SG93IHdpZGUgc2hvdWxkIHRoZSAncmVzdWx0JyBvdXRwdXQgYnVzIGJlPw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2Fzc29jaWF0ZWRfY2xvY2tfZW5hYmxl::dHJ1ZQ==::Q3JlYXRlIGFuIGFzc29jaWF0ZWQgY2xvY2sgZW5hYmxlIGZvciBlYWNoIGNsb2Nr"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9yZWdpc3Rlcg==::dHJ1ZQ==::UmVnaXN0ZXIgb3V0cHV0IG9mIHRoZSBhZGRlciB1bml0"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "b3V0cHV0X3JlZ2lzdGVy::Q0xPQ0sw::b3V0cHV0X3JlZ2lzdGVy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9yZWdpc3Rlcl9jbG9jaw==::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9yZWdpc3Rlcl9hY2xy::QUNMUjA=::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2FjbHI=::QUNMUjA=::b3V0cHV0X2FjbHI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9yZWdpc3Rlcl9zY2xy::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "b3V0cHV0X3NjbHI=::Tk9ORQ==::b3V0cHV0X3NjbHI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcjFfZGlyZWN0aW9u::QURE::bXVsdGlwbGllcjFfZGlyZWN0aW9u"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cG9ydF9hZGRuc3ViMQ==::UE9SVF9VTlVTRUQ=::cG9ydF9hZGRuc3ViMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX3JlZ2lzdGVyMQ==::VU5SRUdJU1RFUkVE::YWRkbnN1Yl9tdWx0aXBsaWVyX3JlZ2lzdGVyMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FkZG5zdWJfbXVsdGlwbGllcl9yZWdpc3RlcjFfY2xvY2s=::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FkZG5zdWJfbXVsdGlwbGllcl9hY2xyMQ==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX2FjbHIx::Tk9ORQ==::YWRkbnN1Yl9tdWx0aXBsaWVyX2FjbHIx"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FkZG5zdWJfbXVsdGlwbGllcl9zY2xyMQ==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX3NjbHIx::Tk9ORQ==::YWRkbnN1Yl9tdWx0aXBsaWVyX3NjbHIx"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcjNfZGlyZWN0aW9u::QURE::bXVsdGlwbGllcjNfZGlyZWN0aW9u"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cG9ydF9hZGRuc3ViMw==::UE9SVF9VTlVTRUQ=::cG9ydF9hZGRuc3ViMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX3JlZ2lzdGVyMw==::VU5SRUdJU1RFUkVE::YWRkbnN1Yl9tdWx0aXBsaWVyX3JlZ2lzdGVyMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FkZG5zdWJfbXVsdGlwbGllcl9yZWdpc3RlcjNfY2xvY2s=::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FkZG5zdWJfbXVsdGlwbGllcl9hY2xyMw==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX2FjbHIz::Tk9ORQ==::YWRkbnN1Yl9tdWx0aXBsaWVyX2FjbHIz"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FkZG5zdWJfbXVsdGlwbGllcl9zY2xyMw==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX3NjbHIz::Tk9ORQ==::YWRkbnN1Yl9tdWx0aXBsaWVyX3NjbHIz"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9zdWJuYWRk::ZmFsc2U=::RW5hYmxlICd1c2Vfc3VibmFkZCc="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "dXNlX3N1Ym5hZGQ=::Tk8=::dXNlX3N1Ym5hZGQ="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlcHJlc2VudGF0aW9uX2E=::VkFSSUFCTEU=::V2hhdCBpcyB0aGUgcmVwcmVzZW50YXRpb24gZm9ybWF0IGZvciBNdWx0aXBsaWVycyBBIGlucHV0cz8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cmVwcmVzZW50YXRpb25fYQ==::VU5TSUdORUQ=::cmVwcmVzZW50YXRpb25fYQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZ2lzdGVyX3NpZ25h::dHJ1ZQ==::UmVnaXN0ZXIgJ3NpZ25hJyBpbnB1dA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cG9ydF9zaWduYQ==::UE9SVF9VU0VE::cG9ydF9zaWduYQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX3JlZ2lzdGVyX2E=::Q0xPQ0sw::c2lnbmVkX3JlZ2lzdGVyX2E="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZ2lzdGVyX3NpZ25hX2Nsb2Nr::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZ2lzdGVyX3NpZ25hX2FjbHI=::QUNMUjA=::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX2FjbHJfYQ==::QUNMUjA=::c2lnbmVkX2FjbHJfYQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZ2lzdGVyX3NpZ25hX3NjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX3NjbHJfYQ==::Tk9ORQ==::c2lnbmVkX3NjbHJfYQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlcHJlc2VudGF0aW9uX2I=::VkFSSUFCTEU=::V2hhdCBpcyB0aGUgcmVwcmVzZW50YXRpb24gZm9ybWF0IGZvciBNdWx0aXBsaWVycyBCIGlucHV0cz8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cG9ydF9zaWduYg==::UE9SVF9VU0VE::cG9ydF9zaWduYg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cmVwcmVzZW50YXRpb25fYg==::VU5TSUdORUQ=::cmVwcmVzZW50YXRpb25fYg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZ2lzdGVyX3NpZ25i::dHJ1ZQ==::UmVnaXN0ZXIgJ3NpZ25iJyBpbnB1dA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX3JlZ2lzdGVyX2I=::Q0xPQ0sw::c2lnbmVkX3JlZ2lzdGVyX2I="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZ2lzdGVyX3NpZ25iX2Nsb2Nr::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZ2lzdGVyX3NpZ25iX2FjbHI=::QUNMUjA=::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX2FjbHJfYg==::QUNMUjA=::c2lnbmVkX2FjbHJfYg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZ2lzdGVyX3NpZ25iX3NjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX3NjbHJfYg==::Tk9ORQ==::c2lnbmVkX3NjbHJfYg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X3JlZ2lzdGVyX2E=::dHJ1ZQ==::UmVnaXN0ZXIgaW5wdXQgQSBvZiB0aGUgbXVsdGlwbGllcg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X3JlZ2lzdGVyX2FfY2xvY2s=::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X3JlZ2lzdGVyX2FfYWNscg==::QUNMUjA=::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X3JlZ2lzdGVyX2Ffc2Nscg==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYTA=::Q0xPQ0sw::aW5wdXRfcmVnaXN0ZXJfYTA="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYTE=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYTE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYTI=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYTI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYTM=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYTM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9hMA==::QUNMUjA=::aW5wdXRfYWNscl9hMA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9hMQ==::Tk9ORQ==::aW5wdXRfYWNscl9hMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9hMg==::Tk9ORQ==::aW5wdXRfYWNscl9hMg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9hMw==::Tk9ORQ==::aW5wdXRfYWNscl9hMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9hMA==::Tk9ORQ==::aW5wdXRfc2Nscl9hMA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9hMQ==::Tk9ORQ==::aW5wdXRfc2Nscl9hMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9hMg==::Tk9ORQ==::aW5wdXRfc2Nscl9hMg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9hMw==::Tk9ORQ==::aW5wdXRfc2Nscl9hMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X3JlZ2lzdGVyX2I=::dHJ1ZQ==::UmVnaXN0ZXIgaW5wdXQgQiBvZiB0aGUgbXVsdGlwbGllcg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X3JlZ2lzdGVyX2JfY2xvY2s=::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X3JlZ2lzdGVyX2JfYWNscg==::QUNMUjA=::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X3JlZ2lzdGVyX2Jfc2Nscg==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYjA=::Q0xPQ0sw::aW5wdXRfcmVnaXN0ZXJfYjA="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYjE=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYjE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYjI=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYjI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYjM=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYjM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9iMA==::QUNMUjA=::aW5wdXRfYWNscl9iMA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9iMQ==::Tk9ORQ==::aW5wdXRfYWNscl9iMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9iMg==::Tk9ORQ==::aW5wdXRfYWNscl9iMg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9iMw==::Tk9ORQ==::aW5wdXRfYWNscl9iMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9iMA==::Tk9ORQ==::aW5wdXRfc2Nscl9iMA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9iMQ==::Tk9ORQ==::aW5wdXRfc2Nscl9iMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9iMg==::Tk9ORQ==::aW5wdXRfc2Nscl9iMg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9iMw==::Tk9ORQ==::aW5wdXRfc2Nscl9iMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3NjYW5vdXRhX3JlZ2lzdGVyX2Nsb2Nr::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3NjYW5vdXRhX3JlZ2lzdGVyX2FjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3NjYW5vdXRhX3JlZ2lzdGVyX3NjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2Nhbm91dGFfcmVnaXN0ZXI=::VU5SRUdJU1RFUkVE::c2Nhbm91dGFfcmVnaXN0ZXI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2Nhbm91dGFfYWNscg==::Tk9ORQ==::c2Nhbm91dGFfYWNscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2Nhbm91dGFfc2Nscg==::Tk9ORQ==::c2Nhbm91dGFfc2Nscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc291cmNlX2Ew::REFUQUE=::aW5wdXRfc291cmNlX2Ew"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc291cmNlX2Ex::REFUQUE=::aW5wdXRfc291cmNlX2Ex"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc291cmNlX2Ey::REFUQUE=::aW5wdXRfc291cmNlX2Ey"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc291cmNlX2Ez::REFUQUE=::aW5wdXRfc291cmNlX2Ez"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc291cmNlX2Iw::REFUQUI=::aW5wdXRfc291cmNlX2Iw"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc291cmNlX2Ix::REFUQUI=::aW5wdXRfc291cmNlX2Ix"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc291cmNlX2Iy::REFUQUI=::aW5wdXRfc291cmNlX2Iy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc291cmNlX2Iz::REFUQUI=::aW5wdXRfc291cmNlX2Iz"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGxpZXJfcmVnaXN0ZXJfY2xvY2s=::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGxpZXJfcmVnaXN0ZXJfYWNscg==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGxpZXJfcmVnaXN0ZXJfc2Nscg==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9yZWdpc3RlcjA=::VU5SRUdJU1RFUkVE::bXVsdGlwbGllcl9yZWdpc3RlcjA="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9yZWdpc3RlcjE=::VU5SRUdJU1RFUkVE::bXVsdGlwbGllcl9yZWdpc3RlcjE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9yZWdpc3RlcjI=::VU5SRUdJU1RFUkVE::bXVsdGlwbGllcl9yZWdpc3RlcjI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9yZWdpc3RlcjM=::VU5SRUdJU1RFUkVE::bXVsdGlwbGllcl9yZWdpc3RlcjM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9hY2xyMA==::Tk9ORQ==::bXVsdGlwbGllcl9hY2xyMA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9hY2xyMQ==::Tk9ORQ==::bXVsdGlwbGllcl9hY2xyMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9hY2xyMg==::Tk9ORQ==::bXVsdGlwbGllcl9hY2xyMg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9hY2xyMw==::Tk9ORQ==::bXVsdGlwbGllcl9hY2xyMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9zY2xyMA==::Tk9ORQ==::bXVsdGlwbGllcl9zY2xyMA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9zY2xyMQ==::Tk9ORQ==::bXVsdGlwbGllcl9zY2xyMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9zY2xyMg==::Tk9ORQ==::bXVsdGlwbGllcl9zY2xyMg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllcl9zY2xyMw==::Tk9ORQ==::bXVsdGlwbGllcl9zY2xyMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cHJlYWRkZXJfbW9kZQ==::U0lNUExF::U2VsZWN0IHByZWFkZGVyIG1vZGU="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cHJlYWRkZXJfZGlyZWN0aW9uXzA=::QURE::cHJlYWRkZXJfZGlyZWN0aW9uXzA="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cHJlYWRkZXJfZGlyZWN0aW9uXzE=::QURE::cHJlYWRkZXJfZGlyZWN0aW9uXzE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cHJlYWRkZXJfZGlyZWN0aW9uXzI=::QURE::cHJlYWRkZXJfZGlyZWN0aW9uXzI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cHJlYWRkZXJfZGlyZWN0aW9uXzM=::QURE::cHJlYWRkZXJfZGlyZWN0aW9uXzM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2RhdGFjX2lucHV0X3JlZ2lzdGVyX2Nsb2Nr::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2RhdGFjX2lucHV0X3JlZ2lzdGVyX2FjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2RhdGFjX2lucHV0X3JlZ2lzdGVyX3NjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYzA=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYzA="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYzE=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYzE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYzI=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYzI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfcmVnaXN0ZXJfYzM=::VU5SRUdJU1RFUkVE::aW5wdXRfcmVnaXN0ZXJfYzM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9jMA==::Tk9ORQ==::aW5wdXRfYWNscl9jMA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9jMQ==::Tk9ORQ==::aW5wdXRfYWNscl9jMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9jMg==::Tk9ORQ==::aW5wdXRfYWNscl9jMg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYWNscl9jMw==::Tk9ORQ==::aW5wdXRfYWNscl9jMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9jMA==::Tk9ORQ==::aW5wdXRfc2Nscl9jMA=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9jMQ==::Tk9ORQ==::aW5wdXRfc2Nscl9jMQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9jMg==::Tk9ORQ==::aW5wdXRfc2Nscl9jMg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfc2Nscl9jMw==::Tk9ORQ==::aW5wdXRfc2Nscl9jMw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2NvZWZfcmVnaXN0ZXJfY2xvY2s=::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2NvZWZfcmVnaXN0ZXJfYWNscg==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2NvZWZfcmVnaXN0ZXJfc2Nscg==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDBfcmVnaXN0ZXI=::VU5SRUdJU1RFUkVE::Y29lZnNlbDBfcmVnaXN0ZXI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDFfcmVnaXN0ZXI=::VU5SRUdJU1RFUkVE::Y29lZnNlbDFfcmVnaXN0ZXI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDJfcmVnaXN0ZXI=::VU5SRUdJU1RFUkVE::Y29lZnNlbDJfcmVnaXN0ZXI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDNfcmVnaXN0ZXI=::VU5SRUdJU1RFUkVE::Y29lZnNlbDNfcmVnaXN0ZXI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDBfYWNscg==::Tk9ORQ==::Y29lZnNlbDBfYWNscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDFfYWNscg==::Tk9ORQ==::Y29lZnNlbDFfYWNscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDJfYWNscg==::Tk9ORQ==::Y29lZnNlbDJfYWNscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDNfYWNscg==::Tk9ORQ==::Y29lZnNlbDNfYWNscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDBfc2Nscg==::Tk9ORQ==::Y29lZnNlbDBfc2Nscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDFfc2Nscg==::Tk9ORQ==::Y29lZnNlbDFfc2Nscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDJfc2Nscg==::Tk9ORQ==::Y29lZnNlbDJfc2Nscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDNfc2Nscg==::Tk9ORQ==::Y29lZnNlbDNfc2Nscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWNjdW11bGF0b3I=::Tk8=::RW5hYmxlIGFjY3VtdWxhdG9yPw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "dXNlX3Nsb2FkX2FjY3VtX3BvcnQ=::Tk8=::dXNlX3Nsb2FkX2FjY3VtX3BvcnQ="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FjY3VtX3Nsb2FkX3JlZ2lzdGVy::ZmFsc2U=::UmVnaXN0ZXIgaW5wdXQgb2YgYWNjdW1fc2xvYWQ="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FjY3VtX3Nsb2FkX3JlZ2lzdGVyX2Nsb2Nr::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FjY3VtX3Nsb2FkX3JlZ2lzdGVyX2FjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2FjY3VtX3Nsb2FkX3JlZ2lzdGVyX3NjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWNjdW1fc2xvYWRfcmVnaXN0ZXI=::VU5SRUdJU1RFUkVE::YWNjdW1fc2xvYWRfcmVnaXN0ZXI="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWNjdW1fc2xvYWRfYWNscg==::Tk9ORQ==::YWNjdW1fc2xvYWRfYWNscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWNjdW1fc2xvYWRfc2Nscg==::Tk9ORQ==::YWNjdW1fc2xvYWRfc2Nscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "ZG91YmxlX2FjY3Vt::Tk8=::ZG91YmxlX2FjY3Vt"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "d2lkdGhfY2hhaW5pbg==::NjQ=::d2lkdGhfY2hhaW5pbg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y2hhaW5vdXRfYWRkZXI=::WUVT::RW5hYmxlIGNoYWlub3V0IGFkZGVy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y2hhaW5vdXRfYWRkZXJfZGlyZWN0aW9u::QURE::V2hhdCBpcyB0aGUgY2hhaW5vdXQgYWRkZXIgb3BlcmF0aW9uIHR5cGU/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cG9ydF9uZWdhdGU=::UE9SVF9VTlVTRUQ=::RW5hYmxlICduZWdhdGUnIGlucHV0IGZvciBjaGFpbm91dCBhZGRlcj8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bmVnYXRlX3JlZ2lzdGVy::VU5SRUdJU1RFUkVE::UmVnaXN0ZXIgJ25lZ2F0ZScgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bmVnYXRlX2FjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bmVnYXRlX3NjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3N5c3RvbGljX2RlbGF5X2Nsb2Nr::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3N5c3RvbGljX2RlbGF5X2FjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3N5c3RvbGljX2RlbGF5X3NjbHI=::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c3lzdG9saWNfZGVsYXkx::VU5SRUdJU1RFUkVE::c3lzdG9saWNfZGVsYXkx"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c3lzdG9saWNfYWNscjE=::Tk9ORQ==::c3lzdG9saWNfYWNscjE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c3lzdG9saWNfc2NscjE=::Tk9ORQ==::c3lzdG9saWNfc2NscjE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c3lzdG9saWNfZGVsYXkz::VU5SRUdJU1RFUkVE::c3lzdG9saWNfZGVsYXkz"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c3lzdG9saWNfYWNscjM=::Tk9ORQ==::c3lzdG9saWNfYWNscjM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c3lzdG9saWNfc2NscjM=::Tk9ORQ==::c3lzdG9saWNfc2NscjM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX3BpcGVsaW5pbmc=::MA==::RG8geW91IHdhbnQgdG8gYWRkIHBpcGVsaW5lIHJlZ2lzdGVyIHRvIHRoZSBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X2xhdGVuY3lfY2xvY2s=::Q0xPQ0sw::V2hhdCBpcyB0aGUgc291cmNlIGZvciBjbG9jayBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X2xhdGVuY3lfYWNscg==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBhc3luY2hyb25vdXMgY2xlYXIgaW5wdXQ/"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Z3VpX2lucHV0X2xhdGVuY3lfc2Nscg==::Tk9ORQ==::V2hhdCBpcyB0aGUgc291cmNlIGZvciBzeW5jaHJvbm91cyBjbGVhciBpbnB1dD8="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTBfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYTBfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTFfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYTFfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTJfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYTJfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTNfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYTNfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTBfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYTBfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTFfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYTFfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTJfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYTJfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTNfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYTNfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTBfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYTBfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTFfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYTFfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTJfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYTJfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYTNfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYTNfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjBfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYjBfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjFfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYjFfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjJfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYjJfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjNfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYjNfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjBfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYjBfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjFfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYjFfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjJfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYjJfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjNfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYjNfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjBfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYjBfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjFfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYjFfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjJfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYjJfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYjNfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYjNfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzBfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYzBfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzFfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYzFfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzJfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYzJfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzNfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::aW5wdXRfYzNfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzBfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYzBfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzFfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYzFfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzJfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYzJfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzNfbGF0ZW5jeV9hY2xy::Tk9ORQ==::aW5wdXRfYzNfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzBfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYzBfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzFfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYzFfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzJfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYzJfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "aW5wdXRfYzNfbGF0ZW5jeV9zY2xy::Tk9ORQ==::aW5wdXRfYzNfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDBfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::Y29lZnNlbDBfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDFfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::Y29lZnNlbDFfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDJfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::Y29lZnNlbDJfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDNfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::Y29lZnNlbDNfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDBfbGF0ZW5jeV9hY2xy::Tk9ORQ==::Y29lZnNlbDBfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDFfbGF0ZW5jeV9hY2xy::Tk9ORQ==::Y29lZnNlbDFfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDJfbGF0ZW5jeV9hY2xy::Tk9ORQ==::Y29lZnNlbDJfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDNfbGF0ZW5jeV9hY2xy::Tk9ORQ==::Y29lZnNlbDNfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDBfbGF0ZW5jeV9zY2xy::Tk9ORQ==::Y29lZnNlbDBfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDFfbGF0ZW5jeV9zY2xy::Tk9ORQ==::Y29lZnNlbDFfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDJfbGF0ZW5jeV9zY2xy::Tk9ORQ==::Y29lZnNlbDJfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "Y29lZnNlbDNfbGF0ZW5jeV9zY2xy::Tk9ORQ==::Y29lZnNlbDNfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX2xhdGVuY3lfY2xvY2tfYQ==::VU5SRUdJU1RFUkVE::c2lnbmVkX2xhdGVuY3lfY2xvY2tfYQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX2xhdGVuY3lfYWNscl9h::Tk9ORQ==::c2lnbmVkX2xhdGVuY3lfYWNscl9h"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX2xhdGVuY3lfc2Nscl9h::Tk9ORQ==::c2lnbmVkX2xhdGVuY3lfc2Nscl9h"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX2xhdGVuY3lfY2xvY2tfYg==::VU5SRUdJU1RFUkVE::c2lnbmVkX2xhdGVuY3lfY2xvY2tfYg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX2xhdGVuY3lfYWNscl9i::Tk9ORQ==::c2lnbmVkX2xhdGVuY3lfYWNscl9i"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2lnbmVkX2xhdGVuY3lfc2Nscl9i::Tk9ORQ==::c2lnbmVkX2xhdGVuY3lfc2Nscl9i"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfY2xvY2sx::VU5SRUdJU1RFUkVE::YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfY2xvY2sx"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfYWNscjE=::Tk9ORQ==::YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfYWNscjE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfc2NscjE=::Tk9ORQ==::YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfc2NscjE="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfY2xvY2sz::VU5SRUdJU1RFUkVE::YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfY2xvY2sz"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfYWNscjM=::Tk9ORQ==::YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfYWNscjM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfc2NscjM=::Tk9ORQ==::YWRkbnN1Yl9tdWx0aXBsaWVyX2xhdGVuY3lfc2NscjM="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWNjdW1fc2xvYWRfbGF0ZW5jeV9jbG9jaw==::VU5SRUdJU1RFUkVE::YWNjdW1fc2xvYWRfbGF0ZW5jeV9jbG9jaw=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWNjdW1fc2xvYWRfbGF0ZW5jeV9hY2xy::Tk9ORQ==::YWNjdW1fc2xvYWRfbGF0ZW5jeV9hY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "YWNjdW1fc2xvYWRfbGF0ZW5jeV9zY2xy::Tk9ORQ==::YWNjdW1fc2xvYWRfbGF0ZW5jeV9zY2xy"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bmVnYXRlX2xhdGVuY3lfY2xvY2s=::VU5SRUdJU1RFUkVE::bmVnYXRlX2xhdGVuY3lfY2xvY2s="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bmVnYXRlX2xhdGVuY3lfYWNscg==::Tk9ORQ==::bmVnYXRlX2xhdGVuY3lfYWNscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "bmVnYXRlX2xhdGVuY3lfc2Nscg==::Tk9ORQ==::bmVnYXRlX2xhdGVuY3lfc2Nscg=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ=="
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_COMPONENT_PARAMETER "cmVnX2F1dG92ZWNfc2lt::ZmFsc2U=::cmVnX2F1dG92ZWNfc2lt"
+
+set_global_assignment -library "dsp_mul" -name VERILOG_FILE [file join $::quartus(qip_path) "dsp_mul.v"]
+set_global_assignment -library "dsp_mul" -name VERILOG_FILE [file join $::quartus(qip_path) "dsp_mul/dsp_mul_0002.v"]
+
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_TOOL_NAME "altera_mult_add"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "dsp_mul_0002" -library "dsp_mul" -name IP_TOOL_ENV "mwpim"
diff --git a/ip/dsp_mul.sip b/ip/dsp_mul.sip
new file mode 100644
index 0000000..5698742
--- /dev/null
+++ b/ip/dsp_mul.sip
@@ -0,0 +1,6 @@
+set_global_assignment -entity "dsp_mul" -library "lib_dsp_mul" -name IP_TOOL_NAME "altera_mult_add"
+set_global_assignment -entity "dsp_mul" -library "lib_dsp_mul" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "dsp_mul" -library "lib_dsp_mul" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_dsp_mul" -name SPD_FILE [file join $::quartus(sip_path) "dsp_mul.spd"]
+
+set_global_assignment -library "lib_dsp_mul" -name MISC_FILE [file join $::quartus(sip_path) "dsp_mul_sim/dsp_mul.v"]
diff --git a/ip/dsp_mul.spd b/ip/dsp_mul.spd
new file mode 100644
index 0000000..59c658d
--- /dev/null
+++ b/ip/dsp_mul.spd
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file path="dsp_mul_sim/dsp_mul.v" type="VERILOG" />
+ <topLevel name="dsp_mul" />
+ <deviceFamily name="cyclonev" />
+</simPackage>
diff --git a/ip/dsp_mul.v b/ip/dsp_mul.v
new file mode 100644
index 0000000..2f8434c
--- /dev/null
+++ b/ip/dsp_mul.v
@@ -0,0 +1,181 @@
+// megafunction wizard: %Multiply Adder Intel FPGA IP v20.1%
+// GENERATION: XML
+// dsp_mul.v
+
+// Generated using ACDS version 20.1 720
+
+`timescale 1 ps / 1 ps
+module dsp_mul (
+ output wire [63:0] result, // result.result
+ input wire [31:0] dataa_0, // dataa_0.dataa_0
+ input wire [31:0] datab_0, // datab_0.datab_0
+ input wire signa, // signa.signa
+ input wire signb, // signb.signb
+ input wire clock0, // clock0.clock0
+ input wire ena0, // ena0.ena0
+ input wire aclr0, // aclr0.aclr0
+ input wire [63:0] chainin // chainin.chainin
+ );
+
+ dsp_mul_0002 dsp_mul_inst (
+ .result (result), // result.result
+ .dataa_0 (dataa_0), // dataa_0.dataa_0
+ .datab_0 (datab_0), // datab_0.datab_0
+ .signa (signa), // signa.signa
+ .signb (signb), // signb.signb
+ .clock0 (clock0), // clock0.clock0
+ .ena0 (ena0), // ena0.ena0
+ .aclr0 (aclr0), // aclr0.aclr0
+ .chainin (chainin) // chainin.chainin
+ );
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+// Generated by Altera MegaWizard Launcher Utility version 1.0
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+// Copyright (C) 1991-2022 Altera Corporation
+// Any megafunction design, and related net list (encrypted or decrypted),
+// support information, device programming or simulation file, and any other
+// associated documentation or information provided by Altera or a partner
+// under Altera's Megafunction Partnership Program may be used only to
+// program PLD devices (but not masked PLD devices) from Altera. Any other
+// use of such megafunction design, net list, support information, device
+// programming or simulation file, or any other related documentation or
+// information is prohibited for any other purpose, including, but not
+// limited to modification, reverse engineering, de-compiling, or use with
+// any other silicon devices, unless such use is explicitly licensed under
+// a separate agreement with Altera or a megafunction partner. Title to
+// the intellectual property, including patents, copyrights, trademarks,
+// trade secrets, or maskworks, embodied in any such megafunction design,
+// net list, support information, device programming or simulation file, or
+// any other related documentation or information provided by Altera or a
+// megafunction partner, remains with Altera, the megafunction partner, or
+// their respective licensors. No other licenses, including any licenses
+// needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_mult_add" version="20.1" >
+// Retrieval info: <generic name="number_of_multipliers" value="1" />
+// Retrieval info: <generic name="width_a" value="32" />
+// Retrieval info: <generic name="width_b" value="32" />
+// Retrieval info: <generic name="width_result" value="64" />
+// Retrieval info: <generic name="gui_4th_asynchronous_clear" value="false" />
+// Retrieval info: <generic name="gui_associated_clock_enable" value="true" />
+// Retrieval info: <generic name="gui_output_register" value="true" />
+// Retrieval info: <generic name="gui_output_register_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_output_register_aclr" value="ACLR0" />
+// Retrieval info: <generic name="gui_output_register_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_multiplier1_direction" value="ADD" />
+// Retrieval info: <generic name="gui_addnsub_multiplier_register1" value="false" />
+// Retrieval info: <generic name="gui_addnsub_multiplier_register1_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_addnsub_multiplier_aclr1" value="NONE" />
+// Retrieval info: <generic name="gui_addnsub_multiplier_sclr1" value="NONE" />
+// Retrieval info: <generic name="gui_multiplier3_direction" value="ADD" />
+// Retrieval info: <generic name="gui_addnsub_multiplier_register3" value="false" />
+// Retrieval info: <generic name="gui_addnsub_multiplier_register3_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_addnsub_multiplier_aclr3" value="NONE" />
+// Retrieval info: <generic name="gui_addnsub_multiplier_sclr3" value="NONE" />
+// Retrieval info: <generic name="gui_use_subnadd" value="false" />
+// Retrieval info: <generic name="gui_representation_a" value="VARIABLE" />
+// Retrieval info: <generic name="gui_register_signa" value="true" />
+// Retrieval info: <generic name="gui_register_signa_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_register_signa_aclr" value="ACLR0" />
+// Retrieval info: <generic name="gui_register_signa_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_representation_b" value="VARIABLE" />
+// Retrieval info: <generic name="gui_register_signb" value="true" />
+// Retrieval info: <generic name="gui_register_signb_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_register_signb_aclr" value="ACLR0" />
+// Retrieval info: <generic name="gui_register_signb_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_input_register_a" value="true" />
+// Retrieval info: <generic name="gui_input_register_a_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_input_register_a_aclr" value="ACLR0" />
+// Retrieval info: <generic name="gui_input_register_a_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_input_register_b" value="true" />
+// Retrieval info: <generic name="gui_input_register_b_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_input_register_b_aclr" value="ACLR0" />
+// Retrieval info: <generic name="gui_input_register_b_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_multiplier_a_input" value="Multiplier input" />
+// Retrieval info: <generic name="gui_scanouta_register" value="false" />
+// Retrieval info: <generic name="gui_scanouta_register_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_scanouta_register_aclr" value="NONE" />
+// Retrieval info: <generic name="gui_scanouta_register_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_multiplier_b_input" value="Multiplier input" />
+// Retrieval info: <generic name="gui_multiplier_register" value="false" />
+// Retrieval info: <generic name="gui_multiplier_register_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_multiplier_register_aclr" value="NONE" />
+// Retrieval info: <generic name="gui_multiplier_register_sclr" value="NONE" />
+// Retrieval info: <generic name="preadder_mode" value="SIMPLE" />
+// Retrieval info: <generic name="gui_preadder_direction" value="ADD" />
+// Retrieval info: <generic name="width_c" value="16" />
+// Retrieval info: <generic name="gui_datac_input_register" value="false" />
+// Retrieval info: <generic name="gui_datac_input_register_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_datac_input_register_aclr" value="NONE" />
+// Retrieval info: <generic name="gui_datac_input_register_sclr" value="NONE" />
+// Retrieval info: <generic name="width_coef" value="18" />
+// Retrieval info: <generic name="gui_coef_register" value="false" />
+// Retrieval info: <generic name="gui_coef_register_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_coef_register_aclr" value="NONE" />
+// Retrieval info: <generic name="gui_coef_register_sclr" value="NONE" />
+// Retrieval info: <generic name="coef0_0" value="0" />
+// Retrieval info: <generic name="coef0_1" value="0" />
+// Retrieval info: <generic name="coef0_2" value="0" />
+// Retrieval info: <generic name="coef0_3" value="0" />
+// Retrieval info: <generic name="coef0_4" value="0" />
+// Retrieval info: <generic name="coef0_5" value="0" />
+// Retrieval info: <generic name="coef0_6" value="0" />
+// Retrieval info: <generic name="coef0_7" value="0" />
+// Retrieval info: <generic name="coef1_0" value="0" />
+// Retrieval info: <generic name="coef1_1" value="0" />
+// Retrieval info: <generic name="coef1_2" value="0" />
+// Retrieval info: <generic name="coef1_3" value="0" />
+// Retrieval info: <generic name="coef1_4" value="0" />
+// Retrieval info: <generic name="coef1_5" value="0" />
+// Retrieval info: <generic name="coef1_6" value="0" />
+// Retrieval info: <generic name="coef1_7" value="0" />
+// Retrieval info: <generic name="coef2_0" value="0" />
+// Retrieval info: <generic name="coef2_1" value="0" />
+// Retrieval info: <generic name="coef2_2" value="0" />
+// Retrieval info: <generic name="coef2_3" value="0" />
+// Retrieval info: <generic name="coef2_4" value="0" />
+// Retrieval info: <generic name="coef2_5" value="0" />
+// Retrieval info: <generic name="coef2_6" value="0" />
+// Retrieval info: <generic name="coef2_7" value="0" />
+// Retrieval info: <generic name="coef3_0" value="0" />
+// Retrieval info: <generic name="coef3_1" value="0" />
+// Retrieval info: <generic name="coef3_2" value="0" />
+// Retrieval info: <generic name="coef3_3" value="0" />
+// Retrieval info: <generic name="coef3_4" value="0" />
+// Retrieval info: <generic name="coef3_5" value="0" />
+// Retrieval info: <generic name="coef3_6" value="0" />
+// Retrieval info: <generic name="coef3_7" value="0" />
+// Retrieval info: <generic name="accumulator" value="NO" />
+// Retrieval info: <generic name="accum_direction" value="ADD" />
+// Retrieval info: <generic name="gui_ena_preload_const" value="false" />
+// Retrieval info: <generic name="gui_accumulate_port_select" value="0" />
+// Retrieval info: <generic name="loadconst_value" value="64" />
+// Retrieval info: <generic name="gui_accum_sload_register_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_accum_sload_register_aclr" value="NONE" />
+// Retrieval info: <generic name="gui_accum_sload_register_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_double_accum" value="false" />
+// Retrieval info: <generic name="chainout_adder" value="YES" />
+// Retrieval info: <generic name="chainout_adder_direction" value="ADD" />
+// Retrieval info: <generic name="port_negate" value="PORT_UNUSED" />
+// Retrieval info: <generic name="negate_register" value="UNREGISTERED" />
+// Retrieval info: <generic name="negate_aclr" value="NONE" />
+// Retrieval info: <generic name="negate_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_systolic_delay" value="false" />
+// Retrieval info: <generic name="gui_systolic_delay_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_systolic_delay_aclr" value="NONE" />
+// Retrieval info: <generic name="gui_systolic_delay_sclr" value="NONE" />
+// Retrieval info: <generic name="gui_pipelining" value="0" />
+// Retrieval info: <generic name="latency" value="0" />
+// Retrieval info: <generic name="gui_input_latency_clock" value="CLOCK0" />
+// Retrieval info: <generic name="gui_input_latency_aclr" value="NONE" />
+// Retrieval info: <generic name="gui_input_latency_sclr" value="NONE" />
+// Retrieval info: <generic name="selected_device_family" value="Cyclone V" />
+// Retrieval info: <generic name="reg_autovec_sim" value="false" />
+// Retrieval info: </instance>
+// IPFS_FILES : dsp_mul.vo
+// RELATED_FILES: dsp_mul.v, dsp_mul_0002.v
diff --git a/ip/dsp_mul/dsp_mul_0002.v b/ip/dsp_mul/dsp_mul_0002.v
new file mode 100644
index 0000000..d2cda4c
--- /dev/null
+++ b/ip/dsp_mul/dsp_mul_0002.v
@@ -0,0 +1,338 @@
+// (C) 2001-2020 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module dsp_mul_0002 (
+ aclr0,
+ chainin,
+ clock0,
+ dataa_0,
+ datab_0,
+ ena0,
+ signa,
+ signb,
+ result);
+
+ input aclr0;
+ input [63:0] chainin;
+ input clock0;
+ input [31:0] dataa_0;
+ input [31:0] datab_0;
+ input ena0;
+ input signa;
+ input signb;
+ output [63:0] result;
+
+ wire [63:0] sub_wire0;
+ wire [63:0] result = sub_wire0[63:0];
+
+ wire [31:0] wire_dataa;
+ assign wire_dataa[31:0] = dataa_0;
+
+ wire [31:0] wire_datab;
+ assign wire_datab[31:0] = datab_0;
+
+ altera_mult_add altera_mult_add_component (
+ .aclr0 (aclr0),
+ .chainin (chainin),
+ .clock0 (clock0),
+ .ena0 (ena0),
+ .signa (signa),
+ .signb (signb),
+ .dataa (wire_dataa),
+ .datab (wire_datab),
+ .result (sub_wire0),
+ .accum_sload (1'b0),
+ .aclr1 (1'b0),
+ .aclr2 (1'b0),
+ .aclr3 (1'b0),
+ .addnsub1 (1'b1),
+ .addnsub1_round (1'b0),
+ .addnsub3 (1'b1),
+ .addnsub3_round (1'b0),
+ .chainout_round (1'b0),
+ .chainout_sat_overflow (),
+ .chainout_saturate (1'b0),
+ .clock1 (1'b1),
+ .clock2 (1'b1),
+ .clock3 (1'b1),
+ .coefsel0 ({3{1'b0}}),
+ .coefsel1 ({3{1'b0}}),
+ .coefsel2 ({3{1'b0}}),
+ .coefsel3 ({3{1'b0}}),
+ .datac ({16{1'b0}}),
+ .ena1 (1'b1),
+ .ena2 (1'b1),
+ .ena3 (1'b1),
+ .mult01_round (1'b0),
+ .mult01_saturation (1'b0),
+ .mult0_is_saturated (),
+ .mult1_is_saturated (),
+ .mult23_round (1'b0),
+ .mult23_saturation (1'b0),
+ .mult2_is_saturated (),
+ .mult3_is_saturated (),
+ .negate (1'b0),
+ .output_round (1'b0),
+ .output_saturate (1'b0),
+ .overflow (),
+ .rotate (1'b0),
+ .scanina ({32{1'b0}}),
+ .scaninb ({32{1'b0}}),
+ .scanouta (),
+ .scanoutb (),
+ .sclr0 (1'b0),
+ .sclr1 (1'b0),
+ .sclr2 (1'b0),
+ .sclr3 (1'b0),
+ .shift_right (1'b0),
+ .sload_accum (1'b0),
+ .sourcea ({1{1'b0}}),
+ .sourceb ({1{1'b0}}),
+ .zero_chainout (1'b0),
+ .zero_loopback (1'b0));
+ defparam
+ altera_mult_add_component.number_of_multipliers = 1,
+ altera_mult_add_component.width_a = 32,
+ altera_mult_add_component.width_b = 32,
+ altera_mult_add_component.width_result = 64,
+ altera_mult_add_component.output_register = "CLOCK0",
+ altera_mult_add_component.output_aclr = "ACLR0",
+ altera_mult_add_component.output_sclr = "NONE",
+ altera_mult_add_component.multiplier1_direction = "ADD",
+ altera_mult_add_component.port_addnsub1 = "PORT_UNUSED",
+ altera_mult_add_component.addnsub_multiplier_register1 = "UNREGISTERED",
+ altera_mult_add_component.addnsub_multiplier_aclr1 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_sclr1 = "NONE",
+ altera_mult_add_component.multiplier3_direction = "ADD",
+ altera_mult_add_component.port_addnsub3 = "PORT_UNUSED",
+ altera_mult_add_component.addnsub_multiplier_register3 = "UNREGISTERED",
+ altera_mult_add_component.addnsub_multiplier_aclr3 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_sclr3 = "NONE",
+ altera_mult_add_component.use_subnadd = "NO",
+ altera_mult_add_component.representation_a = "UNSIGNED",
+ altera_mult_add_component.port_signa = "PORT_USED",
+ altera_mult_add_component.signed_register_a = "CLOCK0",
+ altera_mult_add_component.signed_aclr_a = "ACLR0",
+ altera_mult_add_component.signed_sclr_a = "NONE",
+ altera_mult_add_component.port_signb = "PORT_USED",
+ altera_mult_add_component.representation_b = "UNSIGNED",
+ altera_mult_add_component.signed_register_b = "CLOCK0",
+ altera_mult_add_component.signed_aclr_b = "ACLR0",
+ altera_mult_add_component.signed_sclr_b = "NONE",
+ altera_mult_add_component.input_register_a0 = "CLOCK0",
+ altera_mult_add_component.input_register_a1 = "UNREGISTERED",
+ altera_mult_add_component.input_register_a2 = "UNREGISTERED",
+ altera_mult_add_component.input_register_a3 = "UNREGISTERED",
+ altera_mult_add_component.input_aclr_a0 = "ACLR0",
+ altera_mult_add_component.input_aclr_a1 = "NONE",
+ altera_mult_add_component.input_aclr_a2 = "NONE",
+ altera_mult_add_component.input_aclr_a3 = "NONE",
+ altera_mult_add_component.input_sclr_a0 = "NONE",
+ altera_mult_add_component.input_sclr_a1 = "NONE",
+ altera_mult_add_component.input_sclr_a2 = "NONE",
+ altera_mult_add_component.input_sclr_a3 = "NONE",
+ altera_mult_add_component.input_register_b0 = "CLOCK0",
+ altera_mult_add_component.input_register_b1 = "UNREGISTERED",
+ altera_mult_add_component.input_register_b2 = "UNREGISTERED",
+ altera_mult_add_component.input_register_b3 = "UNREGISTERED",
+ altera_mult_add_component.input_aclr_b0 = "ACLR0",
+ altera_mult_add_component.input_aclr_b1 = "NONE",
+ altera_mult_add_component.input_aclr_b2 = "NONE",
+ altera_mult_add_component.input_aclr_b3 = "NONE",
+ altera_mult_add_component.input_sclr_b0 = "NONE",
+ altera_mult_add_component.input_sclr_b1 = "NONE",
+ altera_mult_add_component.input_sclr_b2 = "NONE",
+ altera_mult_add_component.input_sclr_b3 = "NONE",
+ altera_mult_add_component.scanouta_register = "UNREGISTERED",
+ altera_mult_add_component.scanouta_aclr = "NONE",
+ altera_mult_add_component.scanouta_sclr = "NONE",
+ altera_mult_add_component.input_source_a0 = "DATAA",
+ altera_mult_add_component.input_source_a1 = "DATAA",
+ altera_mult_add_component.input_source_a2 = "DATAA",
+ altera_mult_add_component.input_source_a3 = "DATAA",
+ altera_mult_add_component.input_source_b0 = "DATAB",
+ altera_mult_add_component.input_source_b1 = "DATAB",
+ altera_mult_add_component.input_source_b2 = "DATAB",
+ altera_mult_add_component.input_source_b3 = "DATAB",
+ altera_mult_add_component.multiplier_register0 = "UNREGISTERED",
+ altera_mult_add_component.multiplier_register1 = "UNREGISTERED",
+ altera_mult_add_component.multiplier_register2 = "UNREGISTERED",
+ altera_mult_add_component.multiplier_register3 = "UNREGISTERED",
+ altera_mult_add_component.multiplier_aclr0 = "NONE",
+ altera_mult_add_component.multiplier_aclr1 = "NONE",
+ altera_mult_add_component.multiplier_aclr2 = "NONE",
+ altera_mult_add_component.multiplier_aclr3 = "NONE",
+ altera_mult_add_component.multiplier_sclr0 = "NONE",
+ altera_mult_add_component.multiplier_sclr1 = "NONE",
+ altera_mult_add_component.multiplier_sclr2 = "NONE",
+ altera_mult_add_component.multiplier_sclr3 = "NONE",
+ altera_mult_add_component.preadder_mode = "SIMPLE",
+ altera_mult_add_component.preadder_direction_0 = "ADD",
+ altera_mult_add_component.preadder_direction_1 = "ADD",
+ altera_mult_add_component.preadder_direction_2 = "ADD",
+ altera_mult_add_component.preadder_direction_3 = "ADD",
+ altera_mult_add_component.width_c = 16,
+ altera_mult_add_component.input_register_c0 = "UNREGISTERED",
+ altera_mult_add_component.input_register_c1 = "UNREGISTERED",
+ altera_mult_add_component.input_register_c2 = "UNREGISTERED",
+ altera_mult_add_component.input_register_c3 = "UNREGISTERED",
+ altera_mult_add_component.input_aclr_c0 = "NONE",
+ altera_mult_add_component.input_aclr_c1 = "NONE",
+ altera_mult_add_component.input_aclr_c2 = "NONE",
+ altera_mult_add_component.input_aclr_c3 = "NONE",
+ altera_mult_add_component.input_sclr_c0 = "NONE",
+ altera_mult_add_component.input_sclr_c1 = "NONE",
+ altera_mult_add_component.input_sclr_c2 = "NONE",
+ altera_mult_add_component.input_sclr_c3 = "NONE",
+ altera_mult_add_component.width_coef = 18,
+ altera_mult_add_component.coefsel0_register = "UNREGISTERED",
+ altera_mult_add_component.coefsel1_register = "UNREGISTERED",
+ altera_mult_add_component.coefsel2_register = "UNREGISTERED",
+ altera_mult_add_component.coefsel3_register = "UNREGISTERED",
+ altera_mult_add_component.coefsel0_aclr = "NONE",
+ altera_mult_add_component.coefsel1_aclr = "NONE",
+ altera_mult_add_component.coefsel2_aclr = "NONE",
+ altera_mult_add_component.coefsel3_aclr = "NONE",
+ altera_mult_add_component.coefsel0_sclr = "NONE",
+ altera_mult_add_component.coefsel1_sclr = "NONE",
+ altera_mult_add_component.coefsel2_sclr = "NONE",
+ altera_mult_add_component.coefsel3_sclr = "NONE",
+ altera_mult_add_component.coef0_0 = 0,
+ altera_mult_add_component.coef0_1 = 0,
+ altera_mult_add_component.coef0_2 = 0,
+ altera_mult_add_component.coef0_3 = 0,
+ altera_mult_add_component.coef0_4 = 0,
+ altera_mult_add_component.coef0_5 = 0,
+ altera_mult_add_component.coef0_6 = 0,
+ altera_mult_add_component.coef0_7 = 0,
+ altera_mult_add_component.coef1_0 = 0,
+ altera_mult_add_component.coef1_1 = 0,
+ altera_mult_add_component.coef1_2 = 0,
+ altera_mult_add_component.coef1_3 = 0,
+ altera_mult_add_component.coef1_4 = 0,
+ altera_mult_add_component.coef1_5 = 0,
+ altera_mult_add_component.coef1_6 = 0,
+ altera_mult_add_component.coef1_7 = 0,
+ altera_mult_add_component.coef2_0 = 0,
+ altera_mult_add_component.coef2_1 = 0,
+ altera_mult_add_component.coef2_2 = 0,
+ altera_mult_add_component.coef2_3 = 0,
+ altera_mult_add_component.coef2_4 = 0,
+ altera_mult_add_component.coef2_5 = 0,
+ altera_mult_add_component.coef2_6 = 0,
+ altera_mult_add_component.coef2_7 = 0,
+ altera_mult_add_component.coef3_0 = 0,
+ altera_mult_add_component.coef3_1 = 0,
+ altera_mult_add_component.coef3_2 = 0,
+ altera_mult_add_component.coef3_3 = 0,
+ altera_mult_add_component.coef3_4 = 0,
+ altera_mult_add_component.coef3_5 = 0,
+ altera_mult_add_component.coef3_6 = 0,
+ altera_mult_add_component.coef3_7 = 0,
+ altera_mult_add_component.accumulator = "NO",
+ altera_mult_add_component.accum_direction = "ADD",
+ altera_mult_add_component.use_sload_accum_port = "NO",
+ altera_mult_add_component.loadconst_value = 64,
+ altera_mult_add_component.accum_sload_register = "UNREGISTERED",
+ altera_mult_add_component.accum_sload_aclr = "NONE",
+ altera_mult_add_component.accum_sload_sclr = "NONE",
+ altera_mult_add_component.double_accum = "NO",
+ altera_mult_add_component.width_chainin = 64,
+ altera_mult_add_component.chainout_adder = "YES",
+ altera_mult_add_component.chainout_adder_direction = "ADD",
+ altera_mult_add_component.port_negate = "PORT_UNUSED",
+ altera_mult_add_component.negate_register = "UNREGISTERED",
+ altera_mult_add_component.negate_aclr = "NONE",
+ altera_mult_add_component.negate_sclr = "NONE",
+ altera_mult_add_component.systolic_delay1 = "UNREGISTERED",
+ altera_mult_add_component.systolic_aclr1 = "NONE",
+ altera_mult_add_component.systolic_sclr1 = "NONE",
+ altera_mult_add_component.systolic_delay3 = "UNREGISTERED",
+ altera_mult_add_component.systolic_aclr3 = "NONE",
+ altera_mult_add_component.systolic_sclr3 = "NONE",
+ altera_mult_add_component.latency = 0,
+ altera_mult_add_component.input_a0_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_a1_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_a2_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_a3_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_a0_latency_aclr = "NONE",
+ altera_mult_add_component.input_a1_latency_aclr = "NONE",
+ altera_mult_add_component.input_a2_latency_aclr = "NONE",
+ altera_mult_add_component.input_a3_latency_aclr = "NONE",
+ altera_mult_add_component.input_a0_latency_sclr = "NONE",
+ altera_mult_add_component.input_a1_latency_sclr = "NONE",
+ altera_mult_add_component.input_a2_latency_sclr = "NONE",
+ altera_mult_add_component.input_a3_latency_sclr = "NONE",
+ altera_mult_add_component.input_b0_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_b1_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_b2_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_b3_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_b0_latency_aclr = "NONE",
+ altera_mult_add_component.input_b1_latency_aclr = "NONE",
+ altera_mult_add_component.input_b2_latency_aclr = "NONE",
+ altera_mult_add_component.input_b3_latency_aclr = "NONE",
+ altera_mult_add_component.input_b0_latency_sclr = "NONE",
+ altera_mult_add_component.input_b1_latency_sclr = "NONE",
+ altera_mult_add_component.input_b2_latency_sclr = "NONE",
+ altera_mult_add_component.input_b3_latency_sclr = "NONE",
+ altera_mult_add_component.input_c0_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_c1_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_c2_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_c3_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_c0_latency_aclr = "NONE",
+ altera_mult_add_component.input_c1_latency_aclr = "NONE",
+ altera_mult_add_component.input_c2_latency_aclr = "NONE",
+ altera_mult_add_component.input_c3_latency_aclr = "NONE",
+ altera_mult_add_component.input_c0_latency_sclr = "NONE",
+ altera_mult_add_component.input_c1_latency_sclr = "NONE",
+ altera_mult_add_component.input_c2_latency_sclr = "NONE",
+ altera_mult_add_component.input_c3_latency_sclr = "NONE",
+ altera_mult_add_component.coefsel0_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.coefsel1_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.coefsel2_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.coefsel3_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.coefsel0_latency_aclr = "NONE",
+ altera_mult_add_component.coefsel1_latency_aclr = "NONE",
+ altera_mult_add_component.coefsel2_latency_aclr = "NONE",
+ altera_mult_add_component.coefsel3_latency_aclr = "NONE",
+ altera_mult_add_component.coefsel0_latency_sclr = "NONE",
+ altera_mult_add_component.coefsel1_latency_sclr = "NONE",
+ altera_mult_add_component.coefsel2_latency_sclr = "NONE",
+ altera_mult_add_component.coefsel3_latency_sclr = "NONE",
+ altera_mult_add_component.signed_latency_clock_a = "UNREGISTERED",
+ altera_mult_add_component.signed_latency_aclr_a = "NONE",
+ altera_mult_add_component.signed_latency_sclr_a = "NONE",
+ altera_mult_add_component.signed_latency_clock_b = "UNREGISTERED",
+ altera_mult_add_component.signed_latency_aclr_b = "NONE",
+ altera_mult_add_component.signed_latency_sclr_b = "NONE",
+ altera_mult_add_component.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
+ altera_mult_add_component.addnsub_multiplier_latency_aclr1 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_latency_sclr1 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
+ altera_mult_add_component.addnsub_multiplier_latency_aclr3 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_latency_sclr3 = "NONE",
+ altera_mult_add_component.accum_sload_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.accum_sload_latency_aclr = "NONE",
+ altera_mult_add_component.accum_sload_latency_sclr = "NONE",
+ altera_mult_add_component.negate_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.negate_latency_aclr = "NONE",
+ altera_mult_add_component.negate_latency_sclr = "NONE",
+ altera_mult_add_component.selected_device_family = "Cyclone V";
+
+
+endmodule
+
+
diff --git a/ip/dsp_mul_sim.f b/ip/dsp_mul_sim.f
new file mode 100644
index 0000000..9063310
--- /dev/null
+++ b/ip/dsp_mul_sim.f
@@ -0,0 +1 @@
+dsp_mul_sim/dsp_mul.v
diff --git a/ip/dsp_mul_sim/aldec/rivierapro_setup.tcl b/ip/dsp_mul_sim/aldec/rivierapro_setup.tcl
new file mode 100644
index 0000000..8936f01
--- /dev/null
+++ b/ip/dsp_mul_sim/aldec/rivierapro_setup.tcl
@@ -0,0 +1,278 @@
+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2022.11.06.17:40:06
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# dsp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If dsp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "dsp_mul"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] {
+ set QUARTUS_INSTALL_DIR "/nix/store/w7fwf5djgj7x4jp14b81i51c84kg010y-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
+ set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
+ set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
+ set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] {
+ set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+ set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+ scripterconf -tcl
+ createdesign "$TOP_LEVEL_NAME" "."
+ opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+ echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries
+ensure_lib ./libraries/work
+vmap work ./libraries/work
+ensure_lib ./libraries/altera_ver
+vmap altera_ver ./libraries/altera_ver
+ensure_lib ./libraries/lpm_ver
+vmap lpm_ver ./libraries/lpm_ver
+ensure_lib ./libraries/sgate_ver
+vmap sgate_ver ./libraries/sgate_ver
+ensure_lib ./libraries/altera_mf_ver
+vmap altera_mf_ver ./libraries/altera_mf_ver
+ensure_lib ./libraries/altera_lnsim_ver
+vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
+ensure_lib ./libraries/cyclonev_ver
+vmap cyclonev_ver ./libraries/cyclonev_ver
+ensure_lib ./libraries/cyclonev_hssi_ver
+vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
+ensure_lib ./libraries/cyclonev_pcie_hip_ver
+vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dsp_mul.v"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "file_copy -- Copy ROM/RAM files to simulation directory"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo " For most designs, this should be overridden"
+ echo " to enable the elab/elab_debug aliases."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
+ echo
+ echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
+ echo
+ echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
+ echo
+ echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
diff --git a/ip/dsp_mul_sim/cadence/cds.lib b/ip/dsp_mul_sim/cadence/cds.lib
new file mode 100644
index 0000000..b2eae0a
--- /dev/null
+++ b/ip/dsp_mul_sim/cadence/cds.lib
@@ -0,0 +1,19 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./libraries/work/
+DEFINE altera_ver ./libraries/altera_ver/
+DEFINE lpm_ver ./libraries/lpm_ver/
+DEFINE sgate_ver ./libraries/sgate_ver/
+DEFINE altera_mf_ver ./libraries/altera_mf_ver/
+DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/
+DEFINE cyclonev_ver ./libraries/cyclonev_ver/
+DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
+DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
diff --git a/ip/dsp_mul_sim/cadence/hdl.var b/ip/dsp_mul_sim/cadence/hdl.var
new file mode 100644
index 0000000..c1b7814
--- /dev/null
+++ b/ip/dsp_mul_sim/cadence/hdl.var
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
diff --git a/ip/dsp_mul_sim/cadence/ncsim_setup.sh b/ip/dsp_mul_sim/cadence/ncsim_setup.sh
new file mode 100755
index 0000000..77f7887
--- /dev/null
+++ b/ip/dsp_mul_sim/cadence/ncsim_setup.sh
@@ -0,0 +1,195 @@
+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2022.11.06.17:40:06
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# dsp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If dsp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2022.11.06.17:40:06
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="dsp_mul"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/nix/store/w7fwf5djgj7x4jp14b81i51c84kg010y-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dsp_mul.v"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ export GENERIC_PARAM_COMPAT_CHECK=1
+ ncelab -access +w+r+c -namemap_mixgen $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi
diff --git a/ip/dsp_mul_sim/dsp_mul.v b/ip/dsp_mul_sim/dsp_mul.v
new file mode 100644
index 0000000..cf2fa4d
--- /dev/null
+++ b/ip/dsp_mul_sim/dsp_mul.v
@@ -0,0 +1,338 @@
+// (C) 2001-2020 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module dsp_mul (
+ aclr0,
+ chainin,
+ clock0,
+ dataa_0,
+ datab_0,
+ ena0,
+ signa,
+ signb,
+ result);
+
+ input aclr0;
+ input [63:0] chainin;
+ input clock0;
+ input [31:0] dataa_0;
+ input [31:0] datab_0;
+ input ena0;
+ input signa;
+ input signb;
+ output [63:0] result;
+
+ wire [63:0] sub_wire0;
+ wire [63:0] result = sub_wire0[63:0];
+
+ wire [31:0] wire_dataa;
+ assign wire_dataa[31:0] = dataa_0;
+
+ wire [31:0] wire_datab;
+ assign wire_datab[31:0] = datab_0;
+
+ altera_mult_add altera_mult_add_component (
+ .aclr0 (aclr0),
+ .chainin (chainin),
+ .clock0 (clock0),
+ .ena0 (ena0),
+ .signa (signa),
+ .signb (signb),
+ .dataa (wire_dataa),
+ .datab (wire_datab),
+ .result (sub_wire0),
+ .accum_sload (1'b0),
+ .aclr1 (1'b0),
+ .aclr2 (1'b0),
+ .aclr3 (1'b0),
+ .addnsub1 (1'b1),
+ .addnsub1_round (1'b0),
+ .addnsub3 (1'b1),
+ .addnsub3_round (1'b0),
+ .chainout_round (1'b0),
+ .chainout_sat_overflow (),
+ .chainout_saturate (1'b0),
+ .clock1 (1'b1),
+ .clock2 (1'b1),
+ .clock3 (1'b1),
+ .coefsel0 ({3{1'b0}}),
+ .coefsel1 ({3{1'b0}}),
+ .coefsel2 ({3{1'b0}}),
+ .coefsel3 ({3{1'b0}}),
+ .datac ({16{1'b0}}),
+ .ena1 (1'b1),
+ .ena2 (1'b1),
+ .ena3 (1'b1),
+ .mult01_round (1'b0),
+ .mult01_saturation (1'b0),
+ .mult0_is_saturated (),
+ .mult1_is_saturated (),
+ .mult23_round (1'b0),
+ .mult23_saturation (1'b0),
+ .mult2_is_saturated (),
+ .mult3_is_saturated (),
+ .negate (1'b0),
+ .output_round (1'b0),
+ .output_saturate (1'b0),
+ .overflow (),
+ .rotate (1'b0),
+ .scanina ({32{1'b0}}),
+ .scaninb ({32{1'b0}}),
+ .scanouta (),
+ .scanoutb (),
+ .sclr0 (1'b0),
+ .sclr1 (1'b0),
+ .sclr2 (1'b0),
+ .sclr3 (1'b0),
+ .shift_right (1'b0),
+ .sload_accum (1'b0),
+ .sourcea ({1{1'b0}}),
+ .sourceb ({1{1'b0}}),
+ .zero_chainout (1'b0),
+ .zero_loopback (1'b0));
+ defparam
+ altera_mult_add_component.number_of_multipliers = 1,
+ altera_mult_add_component.width_a = 32,
+ altera_mult_add_component.width_b = 32,
+ altera_mult_add_component.width_result = 64,
+ altera_mult_add_component.output_register = "CLOCK0",
+ altera_mult_add_component.output_aclr = "ACLR0",
+ altera_mult_add_component.output_sclr = "NONE",
+ altera_mult_add_component.multiplier1_direction = "ADD",
+ altera_mult_add_component.port_addnsub1 = "PORT_UNUSED",
+ altera_mult_add_component.addnsub_multiplier_register1 = "UNREGISTERED",
+ altera_mult_add_component.addnsub_multiplier_aclr1 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_sclr1 = "NONE",
+ altera_mult_add_component.multiplier3_direction = "ADD",
+ altera_mult_add_component.port_addnsub3 = "PORT_UNUSED",
+ altera_mult_add_component.addnsub_multiplier_register3 = "UNREGISTERED",
+ altera_mult_add_component.addnsub_multiplier_aclr3 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_sclr3 = "NONE",
+ altera_mult_add_component.use_subnadd = "NO",
+ altera_mult_add_component.representation_a = "UNSIGNED",
+ altera_mult_add_component.port_signa = "PORT_USED",
+ altera_mult_add_component.signed_register_a = "CLOCK0",
+ altera_mult_add_component.signed_aclr_a = "ACLR0",
+ altera_mult_add_component.signed_sclr_a = "NONE",
+ altera_mult_add_component.port_signb = "PORT_USED",
+ altera_mult_add_component.representation_b = "UNSIGNED",
+ altera_mult_add_component.signed_register_b = "CLOCK0",
+ altera_mult_add_component.signed_aclr_b = "ACLR0",
+ altera_mult_add_component.signed_sclr_b = "NONE",
+ altera_mult_add_component.input_register_a0 = "CLOCK0",
+ altera_mult_add_component.input_register_a1 = "UNREGISTERED",
+ altera_mult_add_component.input_register_a2 = "UNREGISTERED",
+ altera_mult_add_component.input_register_a3 = "UNREGISTERED",
+ altera_mult_add_component.input_aclr_a0 = "ACLR0",
+ altera_mult_add_component.input_aclr_a1 = "NONE",
+ altera_mult_add_component.input_aclr_a2 = "NONE",
+ altera_mult_add_component.input_aclr_a3 = "NONE",
+ altera_mult_add_component.input_sclr_a0 = "NONE",
+ altera_mult_add_component.input_sclr_a1 = "NONE",
+ altera_mult_add_component.input_sclr_a2 = "NONE",
+ altera_mult_add_component.input_sclr_a3 = "NONE",
+ altera_mult_add_component.input_register_b0 = "CLOCK0",
+ altera_mult_add_component.input_register_b1 = "UNREGISTERED",
+ altera_mult_add_component.input_register_b2 = "UNREGISTERED",
+ altera_mult_add_component.input_register_b3 = "UNREGISTERED",
+ altera_mult_add_component.input_aclr_b0 = "ACLR0",
+ altera_mult_add_component.input_aclr_b1 = "NONE",
+ altera_mult_add_component.input_aclr_b2 = "NONE",
+ altera_mult_add_component.input_aclr_b3 = "NONE",
+ altera_mult_add_component.input_sclr_b0 = "NONE",
+ altera_mult_add_component.input_sclr_b1 = "NONE",
+ altera_mult_add_component.input_sclr_b2 = "NONE",
+ altera_mult_add_component.input_sclr_b3 = "NONE",
+ altera_mult_add_component.scanouta_register = "UNREGISTERED",
+ altera_mult_add_component.scanouta_aclr = "NONE",
+ altera_mult_add_component.scanouta_sclr = "NONE",
+ altera_mult_add_component.input_source_a0 = "DATAA",
+ altera_mult_add_component.input_source_a1 = "DATAA",
+ altera_mult_add_component.input_source_a2 = "DATAA",
+ altera_mult_add_component.input_source_a3 = "DATAA",
+ altera_mult_add_component.input_source_b0 = "DATAB",
+ altera_mult_add_component.input_source_b1 = "DATAB",
+ altera_mult_add_component.input_source_b2 = "DATAB",
+ altera_mult_add_component.input_source_b3 = "DATAB",
+ altera_mult_add_component.multiplier_register0 = "UNREGISTERED",
+ altera_mult_add_component.multiplier_register1 = "UNREGISTERED",
+ altera_mult_add_component.multiplier_register2 = "UNREGISTERED",
+ altera_mult_add_component.multiplier_register3 = "UNREGISTERED",
+ altera_mult_add_component.multiplier_aclr0 = "NONE",
+ altera_mult_add_component.multiplier_aclr1 = "NONE",
+ altera_mult_add_component.multiplier_aclr2 = "NONE",
+ altera_mult_add_component.multiplier_aclr3 = "NONE",
+ altera_mult_add_component.multiplier_sclr0 = "NONE",
+ altera_mult_add_component.multiplier_sclr1 = "NONE",
+ altera_mult_add_component.multiplier_sclr2 = "NONE",
+ altera_mult_add_component.multiplier_sclr3 = "NONE",
+ altera_mult_add_component.preadder_mode = "SIMPLE",
+ altera_mult_add_component.preadder_direction_0 = "ADD",
+ altera_mult_add_component.preadder_direction_1 = "ADD",
+ altera_mult_add_component.preadder_direction_2 = "ADD",
+ altera_mult_add_component.preadder_direction_3 = "ADD",
+ altera_mult_add_component.width_c = 16,
+ altera_mult_add_component.input_register_c0 = "UNREGISTERED",
+ altera_mult_add_component.input_register_c1 = "UNREGISTERED",
+ altera_mult_add_component.input_register_c2 = "UNREGISTERED",
+ altera_mult_add_component.input_register_c3 = "UNREGISTERED",
+ altera_mult_add_component.input_aclr_c0 = "NONE",
+ altera_mult_add_component.input_aclr_c1 = "NONE",
+ altera_mult_add_component.input_aclr_c2 = "NONE",
+ altera_mult_add_component.input_aclr_c3 = "NONE",
+ altera_mult_add_component.input_sclr_c0 = "NONE",
+ altera_mult_add_component.input_sclr_c1 = "NONE",
+ altera_mult_add_component.input_sclr_c2 = "NONE",
+ altera_mult_add_component.input_sclr_c3 = "NONE",
+ altera_mult_add_component.width_coef = 18,
+ altera_mult_add_component.coefsel0_register = "UNREGISTERED",
+ altera_mult_add_component.coefsel1_register = "UNREGISTERED",
+ altera_mult_add_component.coefsel2_register = "UNREGISTERED",
+ altera_mult_add_component.coefsel3_register = "UNREGISTERED",
+ altera_mult_add_component.coefsel0_aclr = "NONE",
+ altera_mult_add_component.coefsel1_aclr = "NONE",
+ altera_mult_add_component.coefsel2_aclr = "NONE",
+ altera_mult_add_component.coefsel3_aclr = "NONE",
+ altera_mult_add_component.coefsel0_sclr = "NONE",
+ altera_mult_add_component.coefsel1_sclr = "NONE",
+ altera_mult_add_component.coefsel2_sclr = "NONE",
+ altera_mult_add_component.coefsel3_sclr = "NONE",
+ altera_mult_add_component.coef0_0 = 0,
+ altera_mult_add_component.coef0_1 = 0,
+ altera_mult_add_component.coef0_2 = 0,
+ altera_mult_add_component.coef0_3 = 0,
+ altera_mult_add_component.coef0_4 = 0,
+ altera_mult_add_component.coef0_5 = 0,
+ altera_mult_add_component.coef0_6 = 0,
+ altera_mult_add_component.coef0_7 = 0,
+ altera_mult_add_component.coef1_0 = 0,
+ altera_mult_add_component.coef1_1 = 0,
+ altera_mult_add_component.coef1_2 = 0,
+ altera_mult_add_component.coef1_3 = 0,
+ altera_mult_add_component.coef1_4 = 0,
+ altera_mult_add_component.coef1_5 = 0,
+ altera_mult_add_component.coef1_6 = 0,
+ altera_mult_add_component.coef1_7 = 0,
+ altera_mult_add_component.coef2_0 = 0,
+ altera_mult_add_component.coef2_1 = 0,
+ altera_mult_add_component.coef2_2 = 0,
+ altera_mult_add_component.coef2_3 = 0,
+ altera_mult_add_component.coef2_4 = 0,
+ altera_mult_add_component.coef2_5 = 0,
+ altera_mult_add_component.coef2_6 = 0,
+ altera_mult_add_component.coef2_7 = 0,
+ altera_mult_add_component.coef3_0 = 0,
+ altera_mult_add_component.coef3_1 = 0,
+ altera_mult_add_component.coef3_2 = 0,
+ altera_mult_add_component.coef3_3 = 0,
+ altera_mult_add_component.coef3_4 = 0,
+ altera_mult_add_component.coef3_5 = 0,
+ altera_mult_add_component.coef3_6 = 0,
+ altera_mult_add_component.coef3_7 = 0,
+ altera_mult_add_component.accumulator = "NO",
+ altera_mult_add_component.accum_direction = "ADD",
+ altera_mult_add_component.use_sload_accum_port = "NO",
+ altera_mult_add_component.loadconst_value = 64,
+ altera_mult_add_component.accum_sload_register = "UNREGISTERED",
+ altera_mult_add_component.accum_sload_aclr = "NONE",
+ altera_mult_add_component.accum_sload_sclr = "NONE",
+ altera_mult_add_component.double_accum = "NO",
+ altera_mult_add_component.width_chainin = 64,
+ altera_mult_add_component.chainout_adder = "YES",
+ altera_mult_add_component.chainout_adder_direction = "ADD",
+ altera_mult_add_component.port_negate = "PORT_UNUSED",
+ altera_mult_add_component.negate_register = "UNREGISTERED",
+ altera_mult_add_component.negate_aclr = "NONE",
+ altera_mult_add_component.negate_sclr = "NONE",
+ altera_mult_add_component.systolic_delay1 = "UNREGISTERED",
+ altera_mult_add_component.systolic_aclr1 = "NONE",
+ altera_mult_add_component.systolic_sclr1 = "NONE",
+ altera_mult_add_component.systolic_delay3 = "UNREGISTERED",
+ altera_mult_add_component.systolic_aclr3 = "NONE",
+ altera_mult_add_component.systolic_sclr3 = "NONE",
+ altera_mult_add_component.latency = 0,
+ altera_mult_add_component.input_a0_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_a1_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_a2_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_a3_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_a0_latency_aclr = "NONE",
+ altera_mult_add_component.input_a1_latency_aclr = "NONE",
+ altera_mult_add_component.input_a2_latency_aclr = "NONE",
+ altera_mult_add_component.input_a3_latency_aclr = "NONE",
+ altera_mult_add_component.input_a0_latency_sclr = "NONE",
+ altera_mult_add_component.input_a1_latency_sclr = "NONE",
+ altera_mult_add_component.input_a2_latency_sclr = "NONE",
+ altera_mult_add_component.input_a3_latency_sclr = "NONE",
+ altera_mult_add_component.input_b0_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_b1_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_b2_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_b3_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_b0_latency_aclr = "NONE",
+ altera_mult_add_component.input_b1_latency_aclr = "NONE",
+ altera_mult_add_component.input_b2_latency_aclr = "NONE",
+ altera_mult_add_component.input_b3_latency_aclr = "NONE",
+ altera_mult_add_component.input_b0_latency_sclr = "NONE",
+ altera_mult_add_component.input_b1_latency_sclr = "NONE",
+ altera_mult_add_component.input_b2_latency_sclr = "NONE",
+ altera_mult_add_component.input_b3_latency_sclr = "NONE",
+ altera_mult_add_component.input_c0_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_c1_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_c2_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_c3_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.input_c0_latency_aclr = "NONE",
+ altera_mult_add_component.input_c1_latency_aclr = "NONE",
+ altera_mult_add_component.input_c2_latency_aclr = "NONE",
+ altera_mult_add_component.input_c3_latency_aclr = "NONE",
+ altera_mult_add_component.input_c0_latency_sclr = "NONE",
+ altera_mult_add_component.input_c1_latency_sclr = "NONE",
+ altera_mult_add_component.input_c2_latency_sclr = "NONE",
+ altera_mult_add_component.input_c3_latency_sclr = "NONE",
+ altera_mult_add_component.coefsel0_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.coefsel1_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.coefsel2_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.coefsel3_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.coefsel0_latency_aclr = "NONE",
+ altera_mult_add_component.coefsel1_latency_aclr = "NONE",
+ altera_mult_add_component.coefsel2_latency_aclr = "NONE",
+ altera_mult_add_component.coefsel3_latency_aclr = "NONE",
+ altera_mult_add_component.coefsel0_latency_sclr = "NONE",
+ altera_mult_add_component.coefsel1_latency_sclr = "NONE",
+ altera_mult_add_component.coefsel2_latency_sclr = "NONE",
+ altera_mult_add_component.coefsel3_latency_sclr = "NONE",
+ altera_mult_add_component.signed_latency_clock_a = "UNREGISTERED",
+ altera_mult_add_component.signed_latency_aclr_a = "NONE",
+ altera_mult_add_component.signed_latency_sclr_a = "NONE",
+ altera_mult_add_component.signed_latency_clock_b = "UNREGISTERED",
+ altera_mult_add_component.signed_latency_aclr_b = "NONE",
+ altera_mult_add_component.signed_latency_sclr_b = "NONE",
+ altera_mult_add_component.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
+ altera_mult_add_component.addnsub_multiplier_latency_aclr1 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_latency_sclr1 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
+ altera_mult_add_component.addnsub_multiplier_latency_aclr3 = "NONE",
+ altera_mult_add_component.addnsub_multiplier_latency_sclr3 = "NONE",
+ altera_mult_add_component.accum_sload_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.accum_sload_latency_aclr = "NONE",
+ altera_mult_add_component.accum_sload_latency_sclr = "NONE",
+ altera_mult_add_component.negate_latency_clock = "UNREGISTERED",
+ altera_mult_add_component.negate_latency_aclr = "NONE",
+ altera_mult_add_component.negate_latency_sclr = "NONE",
+ altera_mult_add_component.selected_device_family = "Cyclone V";
+
+
+endmodule
+
+
diff --git a/ip/dsp_mul_sim/mentor/msim_setup.tcl b/ip/dsp_mul_sim/mentor/msim_setup.tcl
new file mode 100644
index 0000000..d13c11e
--- /dev/null
+++ b/ip/dsp_mul_sim/mentor/msim_setup.tcl
@@ -0,0 +1,272 @@
+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# dsp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If dsp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2022.11.06.17:40:06
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "dsp_mul"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] {
+ set QUARTUS_INSTALL_DIR "/nix/store/w7fwf5djgj7x4jp14b81i51c84kg010y-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
+ set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
+ set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
+ set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] {
+ set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+ echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries/
+ensure_lib ./libraries/work/
+vmap work ./libraries/work/
+vmap work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+ ensure_lib ./libraries/altera_ver/
+ vmap altera_ver ./libraries/altera_ver/
+ ensure_lib ./libraries/lpm_ver/
+ vmap lpm_ver ./libraries/lpm_ver/
+ ensure_lib ./libraries/sgate_ver/
+ vmap sgate_ver ./libraries/sgate_ver/
+ ensure_lib ./libraries/altera_mf_ver/
+ vmap altera_mf_ver ./libraries/altera_mf_ver/
+ ensure_lib ./libraries/altera_lnsim_ver/
+ vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
+ ensure_lib ./libraries/cyclonev_ver/
+ vmap cyclonev_ver ./libraries/cyclonev_ver/
+ ensure_lib ./libraries/cyclonev_hssi_ver/
+ vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
+ ensure_lib ./libraries/cyclonev_pcie_hip_ver/
+ vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
+}
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+ }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dsp_mul.v"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -voptargs=+acc option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -voptargs=+acc
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "file_copy -- Copy ROM/RAM files to simulation directory"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo " For most designs, this should be overridden"
+ echo " to enable the elab/elab_debug aliases."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
+ echo
+ echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
+ echo
+ echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
+ echo
+ echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
diff --git a/ip/dsp_mul_sim/synopsys/vcs/vcs_setup.sh b/ip/dsp_mul_sim/synopsys/vcs/vcs_setup.sh
new file mode 100755
index 0000000..4bfbc7a
--- /dev/null
+++ b/ip/dsp_mul_sim/synopsys/vcs/vcs_setup.sh
@@ -0,0 +1,152 @@
+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2022.11.06.17:40:06
+
+# ----------------------------------------
+# vcs - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# dsp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, follow the guidelines below.
+#
+# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
+# below into a new file, e.g. named "vcs_sim.sh".
+#
+# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
+# a separate file, e.g. named "filelist.f".
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
+# # set the top-level simulation or testbench module/entity name.
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# # Source the Quartus-generated IP simulation script and do the following:
+# # - Compile the Quartus EDA simulation library and IP simulation files.
+# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
+# # - Compile the design and top-level simulation module/entity using
+# # information specified in "filelist.f".
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# # - Run the simulation.
+# #
+# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
+# TOP_LEVEL_NAME=<simulation top> \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# ----------------------------------------
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the Quartus-generated IP simulation script)
+# #
+# +systemverilogext+.sv
+# <design and testbench files, compile-time options, elaboration options>
+# #
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If dsp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2022.11.06.17:40:06
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="dsp_mul"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/nix/store/w7fwf5djgj7x4jp14b81i51c84kg010y-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
+ $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
+ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
+ $QSYS_SIMDIR/dsp_mul.v \
+ -top $TOP_LEVEL_NAME
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi
diff --git a/ip/dsp_mul_sim/synopsys/vcsmx/synopsys_sim.setup b/ip/dsp_mul_sim/synopsys/vcsmx/synopsys_sim.setup
new file mode 100644
index 0000000..0ee2069
--- /dev/null
+++ b/ip/dsp_mul_sim/synopsys/vcsmx/synopsys_sim.setup
@@ -0,0 +1,12 @@
+
+WORK > DEFAULT
+DEFAULT: ./libraries/work/
+work: ./libraries/work/
+altera_ver: ./libraries/altera_ver/
+lpm_ver: ./libraries/lpm_ver/
+sgate_ver: ./libraries/sgate_ver/
+altera_mf_ver: ./libraries/altera_mf_ver/
+altera_lnsim_ver: ./libraries/altera_lnsim_ver/
+cyclonev_ver: ./libraries/cyclonev_ver/
+cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/
+cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
diff --git a/ip/dsp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/dsp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh
new file mode 100755
index 0000000..60d0552
--- /dev/null
+++ b/ip/dsp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh
@@ -0,0 +1,195 @@
+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2022.11.06.17:40:06
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# dsp_mul
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If dsp_mul is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2022.11.06.17:40:06
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="dsp_mul"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/nix/store/w7fwf5djgj7x4jp14b81i51c84kg010y-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+ :
+else
+ :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dsp_mul.v"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 10:16:30 +0000