rtl/gfx: rename modules

16 files changed, 43 insertions, 43 deletions

diff --git a/gfx_hw.tcl b/gfx_hw.tcl
index 3ba4029..3122b4f 100644
--- a/gfx_hw.tcl
+++ b/gfx_hw.tcl
@@ -40,20 +40,20 @@ set_fileset_property QUARTUS_SYNTH TOP_LEVEL gfx
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file gfx.sv SYSTEM_VERILOG PATH rtl/gfx/gfx.sv TOP_LEVEL_FILE
-add_fileset_file fp_add.sv SYSTEM_VERILOG PATH rtl/gfx/fp_add.sv
-add_fileset_file fp_inv.sv SYSTEM_VERILOG PATH rtl/gfx/fp_inv.sv
-add_fileset_file fp_mul.sv SYSTEM_VERILOG PATH rtl/gfx/fp_mul.sv
+add_fileset_file gfx_fp_add.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fp_add.sv
+add_fileset_file gfx_fp_inv.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fp_inv.sv
+add_fileset_file gfx_fp_mul.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fp_mul.sv
 add_fileset_file gfx_cmd.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_cmd.sv
 add_fileset_file gfx_defs.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_defs.sv
-add_fileset_file horizontal_fold.sv SYSTEM_VERILOG PATH rtl/gfx/horizontal_fold.sv
-add_fileset_file mat_mat_mul.sv SYSTEM_VERILOG PATH rtl/gfx/mat_mat_mul.sv
-add_fileset_file mat_vec_mul.sv SYSTEM_VERILOG PATH rtl/gfx/mat_vec_mul.sv
-add_fileset_file pipeline_flow.sv SYSTEM_VERILOG PATH rtl/gfx/pipeline_flow.sv
-add_fileset_file fold_flow.sv SYSTEM_VERILOG PATH rtl/gfx/fold_flow.sv
-add_fileset_file skid_flow.sv SYSTEM_VERILOG PATH rtl/gfx/skid_flow.sv
-add_fileset_file skid_buf.sv SYSTEM_VERILOG PATH rtl/gfx/skid_buf.sv
-add_fileset_file vec_dot.sv SYSTEM_VERILOG PATH rtl/gfx/vec_dot.sv
-add_fileset_file transpose.sv SYSTEM_VERILOG PATH rtl/gfx/transpose.sv
+add_fileset_file gfx_fold.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fold.sv
+add_fileset_file gfx_mat_mat.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_mat_mat.sv
+add_fileset_file gfx_mat_vec.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_mat_vec.sv
+add_fileset_file gfx_pipeline_flow.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_pipeline_flow.sv
+add_fileset_file gfx_fold_flow.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fold_flow.sv
+add_fileset_file gfx_skid_flow.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_skid_flow.sv
+add_fileset_file gfx_skid_buf.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_skid_buf.sv
+add_fileset_file gfx_dot.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_dot.sv
+add_fileset_file gfx_transpose.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_transpose.sv
 add_fileset_file gfx_scanout.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_scanout.sv
 add_fileset_file gfx_masks.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_masks.sv
 add_fileset_file gfx_mask_sram.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_mask_sram.sv
diff --git a/rtl/gfx/vec_dot.sv b/rtl/gfx/gfx_dot.sv
index a386e6d..9c21c23 100644
--- a/rtl/gfx/vec_dot.sv
+++ b/rtl/gfx/gfx_dot.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module vec_dot
+module gfx_dot
 (
 	input  logic clk,
 
@@ -17,7 +17,7 @@ module vec_dot
 
 	vec4 products_fold, products_mul;
 
-	horizontal_fold fold
+	gfx_fold fold
 	(
 		.vec(products_fold),
 		.stall(stall_fold),
@@ -27,7 +27,7 @@ module vec_dot
 	genvar i;
 	generate
 		for (i = 0; i < `FLOATS_PER_VEC; ++i) begin: entries
-			fp_mul entry_i
+			gfx_fp_mul entry_i
 			(
 				.a(a[i]),
 				.b(b[i]),
@@ -36,7 +36,7 @@ module vec_dot
 				.*
 			);
 
-			skid_buf #(.WIDTH($bits(fp))) skid_i
+			gfx_skid_buf #(.WIDTH($bits(fp))) skid_i
 			(
 				.in(products_mul[i]),
 				.out(products_fold[i]),
diff --git a/rtl/gfx/horizontal_fold.sv b/rtl/gfx/gfx_fold.sv
index f244b55..616d868 100644
--- a/rtl/gfx/horizontal_fold.sv
+++ b/rtl/gfx/gfx_fold.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module horizontal_fold
+module gfx_fold
 (
 	input  logic  clk,
 
@@ -17,7 +17,7 @@ module horizontal_fold
 
 	assign feedback_vec = queued[`FP_ADD_STAGES - 1];
 
-	fp_add add
+	gfx_fp_add add
 	(
 		.a(feedback ? q_add : vec[0]),
 		.b(feedback ? feedback_vec[feedback_last] : vec[1]),
@@ -25,7 +25,7 @@ module horizontal_fold
 		.*
 	);
 
-	skid_buf #(.WIDTH($bits(q))) skid
+	gfx_skid_buf #(.WIDTH($bits(q))) skid
 	(
 		.in(q_add),
 		.out(q),
diff --git a/rtl/gfx/fold_flow.sv b/rtl/gfx/gfx_fold_flow.sv
index 2221976..8f23b8f 100644
--- a/rtl/gfx/fold_flow.sv
+++ b/rtl/gfx/gfx_fold_flow.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module fold_flow
+module gfx_fold_flow
 (
 	input  logic  clk,
 	              rst_n,
@@ -25,7 +25,7 @@ module fold_flow
 
 	assign last_round = rounds[`FP_ADD_STAGES - 1];
 
-	skid_flow skid
+	gfx_skid_flow skid
 	(
 		.in_valid(last_round == `INDEX4_MAX),
 		.in_ready(skid_ready),
diff --git a/rtl/gfx/fp_add.sv b/rtl/gfx/gfx_fp_add.sv
index b49a8aa..6ba7b1c 100644
--- a/rtl/gfx/fp_add.sv
+++ b/rtl/gfx/gfx_fp_add.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module fp_add
+module gfx_fp_add
 (
 	input  logic clk,
 
diff --git a/rtl/gfx/fp_inv.sv b/rtl/gfx/gfx_fp_inv.sv
index d2bebdc..41b3ad5 100644
--- a/rtl/gfx/fp_inv.sv
+++ b/rtl/gfx/gfx_fp_inv.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module fp_inv
+module gfx_fp_inv
 (
 	input  logic clk,
 
diff --git a/rtl/gfx/fp_mul.sv b/rtl/gfx/gfx_fp_mul.sv
index fda4de2..eb7d7d7 100644
--- a/rtl/gfx/fp_mul.sv
+++ b/rtl/gfx/gfx_fp_mul.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module fp_mul
+module gfx_fp_mul
 (
 	input  logic clk,
 
diff --git a/rtl/gfx/mat_mat_mul.sv b/rtl/gfx/gfx_mat_mat.sv
index 85ff7d6..d03a648 100644
--- a/rtl/gfx/mat_mat_mul.sv
+++ b/rtl/gfx/gfx_mat_mat.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module mat_mat_mul
+module gfx_mat_mat
 (
 	input  logic clk,
 	             rst_n,
@@ -26,13 +26,13 @@ module mat_mat_mul
 	assign mul_in_valid = in_valid || in_index != `INDEX4_MIN;
 	assign mul_out_ready = out_ready || out_index != `INDEX4_MAX;
 
-	transpose transpose_b
+	gfx_transpose transpose_b
 	(
 		.in(b),
 		.out(b_transpose)
 	);
 
-	mat_vec_mul mul
+	gfx_mat_vec mul
 	(
 		.a(in_index == `INDEX4_MIN ? a : a_hold),
 		.x(mul_b[in_index]),
@@ -44,7 +44,7 @@ module mat_mat_mul
 		.*
 	);
 
-	transpose transpose_q
+	gfx_transpose transpose_q
 	(
 		.in(q_transpose),
 		.out(q)
diff --git a/rtl/gfx/mat_vec_mul.sv b/rtl/gfx/gfx_mat_vec.sv
index 9f5dcae..4be4976 100644
--- a/rtl/gfx/mat_vec_mul.sv
+++ b/rtl/gfx/gfx_mat_vec.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module mat_vec_mul
+module gfx_mat_vec
 (
 	input  logic clk,
 	             rst_n,
@@ -17,7 +17,7 @@ module mat_vec_mul
 
 	logic stall_mul, stall_fold, mul_ready, mul_valid, feedback, feedback_last;
 
-	pipeline_flow #(.STAGES(`FP_MUL_STAGES)) mul
+	gfx_pipeline_flow #(.STAGES(`FP_MUL_STAGES)) mul
 	(
 		.stall(stall_mul),
 		.out_ready(mul_ready),
@@ -25,7 +25,7 @@ module mat_vec_mul
 		.*
 	);
 
-	fold_flow fold
+	gfx_fold_flow fold
 	(
 		.stall(stall_fold),
 		.in_ready(mul_ready),
@@ -36,7 +36,7 @@ module mat_vec_mul
 	genvar i;
 	generate
 		for (i = 0; i < `VECS_PER_MAT; ++i) begin: dots
-			vec_dot dot_i
+			gfx_dot dot_i
 			(
 				.a(a[i]),
 				.b(x),
diff --git a/rtl/gfx/gfx_perspective.sv b/rtl/gfx/gfx_perspective.sv
index 3cc38b2..6af1724 100644
--- a/rtl/gfx/gfx_perspective.sv
+++ b/rtl/gfx/gfx_perspective.sv
@@ -19,7 +19,7 @@ module gfx_perspective
 	assign w_inv = w_inv_pipes[`FP_MUL_STAGES - 1];
 	assign selected_w_inv = in_start ? next_w_inv : vertex_w_inv;
 
-	fp_inv inv
+	gfx_fp_inv inv
 	(
 		.a(clip_attr.w),
 		.q(next_w_inv),
@@ -29,7 +29,7 @@ module gfx_perspective
 	genvar i;
 	generate
 		for (i = 0; i < `FLOATS_PER_VEC; ++i) begin: divs
-			fp_mul div
+			gfx_fp_mul div
 			(
 				.a(in_pipes[`FP_INV_STAGES - 1][i]),
 				.b(selected_w_inv),
diff --git a/rtl/gfx/gfx_perspective_flow.sv b/rtl/gfx/gfx_perspective_flow.sv
index ecacc65..e94f584 100644
--- a/rtl/gfx/gfx_perspective_flow.sv
+++ b/rtl/gfx/gfx_perspective_flow.sv
@@ -25,7 +25,7 @@ module gfx_perspective_flow
 	assign in_start = start_pipes[`FP_INV_STAGES - 1];
 	assign out_start = start_pipes[STAGES - 1];
 
-	pipeline_flow #(.STAGES(STAGES)) flow
+	gfx_pipeline_flow #(.STAGES(STAGES)) flow
 	(
 		.*
 	);
diff --git a/rtl/gfx/pipeline_flow.sv b/rtl/gfx/gfx_pipeline_flow.sv
index 64b5714..9b3f22a 100644
--- a/rtl/gfx/pipeline_flow.sv
+++ b/rtl/gfx/gfx_pipeline_flow.sv
@@ -1,4 +1,4 @@
-module pipeline_flow
+module gfx_pipeline_flow
 #(parameter STAGES=0)
 (
 	input  logic clk,
@@ -14,7 +14,7 @@ module pipeline_flow
 
 	logic[STAGES - 1:0] valid;
 
-	skid_flow skid
+	gfx_skid_flow skid
 	(
 		.in_valid(valid[STAGES - 1]),
 		.*
diff --git a/rtl/gfx/gfx_scanout.sv b/rtl/gfx/gfx_scanout.sv
index c549782..18b700d 100644
--- a/rtl/gfx/gfx_scanout.sv
+++ b/rtl/gfx/gfx_scanout.sv
@@ -73,7 +73,7 @@ module gfx_scanout
 	genvar i;
 	generate
 		for (i = 0; i < `GFX_SCAN_STAGES; ++i) begin: stages
-			pipeline_flow #(.STAGES(1)) fb_flow
+			gfx_pipeline_flow #(.STAGES(1)) fb_flow
 			(
 				.stall(fb_stalls[i]),
 				.in_ready(fb_ready[i]),
@@ -83,7 +83,7 @@ module gfx_scanout
 				.*
 			);
 
-			pipeline_flow #(.STAGES(1)) src_flow
+			gfx_pipeline_flow #(.STAGES(1)) src_flow
 			(
 				.stall(src_stalls[i]),
 				.in_ready(src_ready[i]),
diff --git a/rtl/gfx/skid_buf.sv b/rtl/gfx/gfx_skid_buf.sv
index 6e7ffbb..fae5717 100644
--- a/rtl/gfx/skid_buf.sv
+++ b/rtl/gfx/gfx_skid_buf.sv
@@ -1,4 +1,4 @@
-module skid_buf
+module gfx_skid_buf
 #(parameter WIDTH=0)
 (
 	input  logic              clk,
diff --git a/rtl/gfx/skid_flow.sv b/rtl/gfx/gfx_skid_flow.sv
index 2b521e5..c5e3b4a 100644
--- a/rtl/gfx/skid_flow.sv
+++ b/rtl/gfx/gfx_skid_flow.sv
@@ -1,4 +1,4 @@
-module skid_flow
+module gfx_skid_flow
 (
 	input  logic clk,
 	             rst_n,
@@ -17,7 +17,7 @@ module skid_flow
 	assign in_ready = was_ready || !was_valid;
 	assign out_valid = in_valid || stall;
 
-	always @(posedge clk or negedge rst_n)
+	always_ff @(posedge clk or negedge rst_n)
 		if (!rst_n) begin
 			was_ready <= 0;
 			was_valid <= 0;
diff --git a/rtl/gfx/transpose.sv b/rtl/gfx/gfx_transpose.sv
index 1df68d5..03ecf2d 100644
--- a/rtl/gfx/transpose.sv
+++ b/rtl/gfx/gfx_transpose.sv
@@ -1,6 +1,6 @@
 `include "gfx/gfx_defs.sv"
 
-module transpose
+module gfx_transpose
 (
 	input  mat4 in,
 	output mat4 out