Add sim test: control_flow

2 files changed, 62 insertions, 0 deletions

diff --git a/tb/sim/control_flow.c b/tb/sim/control_flow.c
new file mode 100644
index 0000000..3bcf643
--- /dev/null
+++ b/tb/sim/control_flow.c
@@ -0,0 +1,56 @@
+int __attribute__((noinline)) sgn(int x)
+{
+	return x > 0 ? 1 : x < 0 ? -1 : 0;
+}
+
+int reset(int a, int b)
+{
+	int c;
+	do
+	{
+		c = sgn(a) + sgn(b);
+		if(!c)
+		{
+			goto l1;
+		}
+
+		switch(c)
+		{
+			case -1:
+				a = b;
+				__attribute__((fallthrough));
+
+			case 0:
+				b = a;
+				break;
+
+			case 1:
+				goto l2;
+
+			default:
+				a = (a >> 7) ^ ((unsigned)a << 10);
+				b = b + (b << 12 | (unsigned)b >> 17);
+				continue;
+		}
+
+		if(sgn(b) <= 0)
+		{
+			a = ~b;
+		}
+
+		if(sgn(a) > 0)
+		{
+			b = 1 - a;
+		}
+	} while(a > b);
+
+	c = a + b;
+	return c;
+
+l1:
+	a = (b << 16 | (unsigned)a >> 16) ^ c;
+
+l2:
+	a = a << 2 | (unsigned)a >> 30;
+	return a;
+}
diff --git a/tb/sim/control_flow.py b/tb/sim/control_flow.py
new file mode 100644
index 0000000..21aaac0
--- /dev/null
+++ b/tb/sim/control_flow.py
@@ -0,0 +1,6 @@
+def init():
+    init_reg(r0, 0xdeadc0de);
+    init_reg(r1, 0xbaaaaaad);
+
+def final():
+    assert_reg(r0, 0xae13ab83)