Add toplevel module for core tests

3 files changed, 67 insertions, 3 deletions

diff --git a/conspiracion.qsf b/conspiracion.qsf
index 850a26a..4242e25 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -56,8 +56,6 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv
-set_global_assignment -name QIP_FILE platform/synthesis/platform.qip
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_oct_rzqin -tag __hps_sdram_p0
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[0] -tag __hps_sdram_p0
 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0
@@ -213,5 +211,15 @@ set_location_assignment PIN_Y21 -to done
 
 set_location_assignment PIN_AF14 -to clk_clk
 
+set_global_assignment -name SEARCH_PATH rtl
+
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/uarch.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv
+set_global_assignment -name QSYS_FILE platform.qsys
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv
+set_global_assignment -name QIP_FILE platform/synthesis/platform.qip
 set_global_assignment -name SDC_FILE conspiracion.sdc
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv
index b994d8b..3d0eb88 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/fetch/prefetch.sv
@@ -47,7 +47,7 @@ module core_prefetch
 
 	genvar i;
 	generate
-		for(i = 0; i < SIZE - 1; ++i) begin
+		for(i = 0; i < SIZE - 1; ++i) begin: prefetch_slots
 			always_ff @(posedge clk)
 				if(flush)
 					prefetch[i] <= `NOP;
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
new file mode 100644
index 0000000..79e8bb8
--- /dev/null
+++ b/rtl/top/conspiracion.sv
@@ -0,0 +1,56 @@
+module conspiracion
+(
+	input  wire        clk_clk,
+	output wire [12:0] memory_mem_a,
+	output wire [2:0]  memory_mem_ba,
+	output wire        memory_mem_ck,
+	output wire        memory_mem_ck_n,
+	output wire        memory_mem_cke,
+	output wire        memory_mem_cs_n,
+	output wire        memory_mem_ras_n,
+	output wire        memory_mem_cas_n,
+	output wire        memory_mem_we_n,
+	output wire        memory_mem_reset_n,
+	inout  wire [7:0]  memory_mem_dq,
+	inout  wire        memory_mem_dqs,
+	inout  wire        memory_mem_dqs_n,
+	output wire        memory_mem_odt,
+	output wire        memory_mem_dm,
+	input  wire        memory_oct_rzqin,
+
+	input logic dir, clr, mov, add, io,
+	output logic[7:0] out,
+	output logic done
+);
+
+	//TODO
+	wire reset_reset_n;
+	assign reset_reset_n = 1'b1;
+
+	logic[29:0] addr;
+	logic[31:0] data_rd, data_wr;
+	logic ready, write, start;
+
+	arm810 core
+	(
+		.clk(clk_clk),
+		.bus_addr(addr),
+		.bus_data_rd(data_rd),
+		.bus_data_wr(data_wr),
+		.bus_ready(ready),
+		.bus_write(write),
+		.bus_start(start)
+	);
+
+	platform plat
+	(
+		.master_0_core_addr(addr),
+		.master_0_core_data_rd(data_rd),
+		.master_0_core_data_wr(data_wr),
+		.master_0_core_ready(ready),
+		.master_0_core_write(write),
+		.master_0_core_start(start),
+		.*
+	);
+
+endmodule