diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-10-01 08:21:27 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-01 09:58:49 -0600 |
| commit | 7b329b833ec3f63b0195369e76b86cca1e5e3ad6 (patch) | |
| tree | 99b906a05bd41dca6f635adf7e4ae7da6640e3c2 | |
| parent | 58dd2e9725b7ba05238f12a4432a83740eff7511 (diff) | |
nix: patch binutils to disable instruction support check GNU as
Diffstat (limited to '')
| -rw-r--r-- | nix/flake.nix | 15 | ||||
| -rw-r--r-- | nix/gas-config-tc-arm-disable-instruction-support-check.patch | 33 |
2 files changed, 48 insertions, 0 deletions
diff --git a/nix/flake.nix b/nix/flake.nix index 99ccbdc..25eac80 100644 --- a/nix/flake.nix +++ b/nix/flake.nix @@ -32,6 +32,21 @@ baseConfig = "taller_defconfig"; }; }; + + # Tomó mucho conseguir esta expresión: horas de leer nixpkgs, prueba y error + crossOverlays = [ + (final: prev: { + stdenv = prev.stdenvAdapters.overrideCC prev.stdenv (prev.stdenv.cc.override { + bintools = prev.stdenv.cc.bintools.override { + bintools = prev.stdenv.cc.bintools.bintools.overrideAttrs (prev: { + patches = prev.patches ++ [ + ./gas-config-tc-arm-disable-instruction-support-check.patch + ]; + }); + }; + }); + }) + ]; }; in { diff --git a/nix/gas-config-tc-arm-disable-instruction-support-check.patch b/nix/gas-config-tc-arm-disable-instruction-support-check.patch new file mode 100644 index 0000000..ded93ac --- /dev/null +++ b/nix/gas-config-tc-arm-disable-instruction-support-check.patch @@ -0,0 +1,33 @@ +From c756563bacfad1f88e9b3ed5d63f5208a0637e57 Mon Sep 17 00:00:00 2001 +From: Alejandro Soto <alejandro@34project.org> +Date: Sun, 1 Oct 2023 08:16:52 -0600 +Subject: [PATCH] gas/config/tc-arm: disable instruction support check in ARM + mode + +--- + gas/config/tc-arm.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c +index a5687ba0..ea727195 100644 +--- a/gas/config/tc-arm.c ++++ b/gas/config/tc-arm.c +@@ -23710,6 +23710,7 @@ md_assemble (char *str) + /* bx is allowed on v5 cores, and sometimes on v4 cores. */ + is_bx = (opcode->aencode == do_bx); + ++#if 0 + /* Check that this instruction is supported for this CPU. */ + if (!(is_bx && fix_v4bx) + && !(opcode->avariant && +@@ -23718,6 +23719,7 @@ md_assemble (char *str) + as_bad (_("selected processor does not support `%s' in ARM mode"), str); + return; + } ++#endif + if (inst.size_req) + { + as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); +-- +2.40.1 + |