Define ALU control signal set

4 files changed, 37 insertions, 20 deletions

diff --git a/rtl/core/alu/alu.sv b/rtl/core/alu/alu.sv
index ade0340..914b40e 100644
--- a/rtl/core/alu/alu.sv
+++ b/rtl/core/alu/alu.sv
@@ -3,7 +3,7 @@
 module core_alu
 #(parameter W=16)
 (
-	input  alu_op         op,
+	input  alu_control    ctrl,
 	input  logic[W - 1:0] a,
 	                      b,
 	input  logic          c_in,
@@ -51,7 +51,7 @@ module core_alu
 	);
 
 	always_comb begin
-		unique case(op)
+		unique case(ctrl.op)
 			`ALU_ADD, `ALU_ADC, `ALU_CMN, `ALU_CMP, `ALU_SUB, `ALU_SBC:
 				swap = 0;
 
@@ -62,7 +62,7 @@ module core_alu
 				swap = 1'bx;
 		endcase
 
-		unique case(op)
+		unique case(ctrl.op)
 			`ALU_ADD, `ALU_CMN, `ALU_ADC:
 				sub = 0;
 
@@ -73,7 +73,7 @@ module core_alu
 				sub = 1'bx;
 		endcase
 
-		unique case(op)
+		unique case(ctrl.op)
 			`ALU_ADD, `ALU_CMN, `ALU_CMP, `ALU_SUB, `ALU_RSB:
 				c_in_add = 0;
 
@@ -87,7 +87,7 @@ module core_alu
 				c_in_add = {W{1'bx}};
 		endcase
 
-		unique case(op)
+		unique case(ctrl.op)
 			`ALU_AND, `ALU_TST:
 				and_not = 0;
 
@@ -98,7 +98,7 @@ module core_alu
 				and_not = 1'bx;
 		endcase
 
-		unique case(op)
+		unique case(ctrl.op)
 			`ALU_SUB, `ALU_RSB, `ALU_ADD, `ALU_ADC, `ALU_SBC, `ALU_RSC, `ALU_CMP, `ALU_CMN:
 				q = q_add;
 
@@ -118,7 +118,7 @@ module core_alu
 				q = neg_b;
 		endcase
 
-		unique case(op)
+		unique case(ctrl.op)
 			`ALU_AND, `ALU_EOR, `ALU_TST, `ALU_TEQ, `ALU_ORR, `ALU_MOV, `ALU_BIC, `ALU_MVN: begin
 				c = c_shifter;
 				v = 1'bx;
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 5dc8172..d9939fd 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -49,11 +49,12 @@ module arm810
 	logic explicit_branch, writeback, update_flags;
 	ptr branch_target;
 	psr_mode reg_mode;
-	alu_op data_op;
+	alu_control alu_ctrl;
 
 	core_cycles cycles
 	(
 		.branch(explicit_branch),
+		.alu(alu_ctrl),
 		.*
 	);
 
@@ -84,7 +85,7 @@ module arm810
 
 	core_alu #(.W(32)) alu
 	(
-		.op(data_op),
+		.ctrl(alu_ctrl),
 		.a(rd_value_a),
 		.b(rd_value_b),
 		.c_in(flags.c),
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
index ff4eb34..84bbd32 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/cycles.sv
@@ -11,16 +11,16 @@ module core_cycles
 	input  alu_decode dec_alu,
 	input  ptr        fetch_insn_pc,
 
-	output logic      stall,
-	                  branch,
-	                  writeback,
-	                  update_flags,
-	output reg_num    rd,
-	output ptr        branch_target,
-	                  pc,
-	                  pc_visible,
-	output psr_mode   reg_mode,
-	output alu_op     data_op
+	output logic       stall,
+	                   branch,
+	                   writeback,
+	                   update_flags,
+	output reg_num     rd,
+	output ptr         branch_target,
+	                   pc,
+	                   pc_visible,
+	output psr_mode    reg_mode,
+	output alu_control alu
 );
 
 	enum
@@ -48,9 +48,15 @@ module core_cycles
 				branch_target <= pc_visible + dec_branch_offset;
 			end
 
+			alu.op <= dec_alu.op;
+			alu.shl <= dec_alu.shl;
+			alu.shr <= dec_alu.shr;
+			alu.ror <= dec_alu.ror;
+			alu.put_carry <= dec_alu.put_carry;
+			alu.sign_extend <= dec_alu.sign_extend;
+
 			pc <= fetch_insn_pc;
 			rd <= dec_alu.rd;
-			data_op <= dec_alu.op;
 			update_flags <= dec_update_flags;
 		end
 	end
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv
index c4dd961..c382cba 100644
--- a/rtl/core/uarch.sv
+++ b/rtl/core/uarch.sv
@@ -74,4 +74,14 @@ typedef struct packed
 	logic[5:0] shift_imm;
 } alu_decode;
 
+typedef struct packed
+{
+	alu_op op;
+	logic  shl,
+	       shr,
+	       ror,
+	       put_carry,
+	       sign_extend;
+} alu_control;
+
 `endif