platform: add gfx

2 files changed, 147 insertions, 0 deletions

diff --git a/gfx_hw.tcl b/gfx_hw.tcl
new file mode 100644
index 0000000..f337d95
--- /dev/null
+++ b/gfx_hw.tcl
@@ -0,0 +1,127 @@
+# TCL File Generated by Component Editor 20.1
+# Sat Oct 21 08:29:20 GMT 2023
+# DO NOT MODIFY
+
+
+# 
+# gfx "3D graphics accelerator" v1.0
+#  2023.10.21.08:29:20
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module gfx
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME gfx
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME "3D graphics accelerator"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL gfx
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file gfx.sv SYSTEM_VERILOG PATH rtl/gfx/gfx.sv TOP_LEVEL_FILE
+add_fileset_file fp_add.sv SYSTEM_VERILOG PATH rtl/gfx/fp_add.sv
+add_fileset_file fp_mul.sv SYSTEM_VERILOG PATH rtl/gfx/fp_mul.sv
+add_fileset_file gfx_defs.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_defs.sv
+add_fileset_file horizontal_fold.sv SYSTEM_VERILOG PATH rtl/gfx/horizontal_fold.sv
+add_fileset_file mat_mat_mul.sv SYSTEM_VERILOG PATH rtl/gfx/mat_mat_mul.sv
+add_fileset_file mat_vec_mul.sv SYSTEM_VERILOG PATH rtl/gfx/mat_vec_mul.sv
+add_fileset_file pipelined_flow.sv SYSTEM_VERILOG PATH rtl/gfx/pipelined_flow.sv
+add_fileset_file vec_dot.sv SYSTEM_VERILOG PATH rtl/gfx/vec_dot.sv
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point cmd
+# 
+add_interface cmd avalon end
+set_interface_property cmd addressUnits WORDS
+set_interface_property cmd associatedClock clock
+set_interface_property cmd associatedReset reset_sink
+set_interface_property cmd bitsPerSymbol 8
+set_interface_property cmd burstOnBurstBoundariesOnly false
+set_interface_property cmd burstcountUnits WORDS
+set_interface_property cmd explicitAddressSpan 0
+set_interface_property cmd holdTime 0
+set_interface_property cmd linewrapBursts false
+set_interface_property cmd maximumPendingReadTransactions 0
+set_interface_property cmd maximumPendingWriteTransactions 0
+set_interface_property cmd readLatency 0
+set_interface_property cmd readWaitTime 1
+set_interface_property cmd setupTime 0
+set_interface_property cmd timingUnits Cycles
+set_interface_property cmd writeWaitTime 0
+set_interface_property cmd ENABLED true
+set_interface_property cmd EXPORT_OF ""
+set_interface_property cmd PORT_NAME_MAP ""
+set_interface_property cmd CMSIS_SVD_VARIABLES ""
+set_interface_property cmd SVD_ADDRESS_GROUP ""
+
+add_interface_port cmd cmd_address address Input 5
+add_interface_port cmd cmd_read read Input 1
+add_interface_port cmd cmd_write write Input 1
+add_interface_port cmd cmd_writedata writedata Input 32
+add_interface_port cmd cmd_readdata readdata Output 32
+set_interface_assignment cmd embeddedsw.configuration.isFlash 0
+set_interface_assignment cmd embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment cmd embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment cmd embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink rst_n reset_n Input 1
+
diff --git a/platform.qsys b/platform.qsys
index 0e829c7..ebcff33 100644
--- a/platform.qsys
+++ b/platform.qsys
@@ -97,6 +97,14 @@
          type = "int";
       }
    }
+   element gfx_0
+   {
+      datum _sortIndex
+      {
+         value = "29";
+         type = "int";
+      }
+   }
    element hps_0
    {
       datum _sortIndex
@@ -426,6 +434,7 @@
  <module name="cpu_3" kind="core" version="1.0" enabled="1">
   <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" />
  </module>
+ <module name="gfx_0" kind="gfx" version="1.0" enabled="1" />
  <module name="hps_0" kind="altera_hps" version="20.1" enabled="1">
   <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
   <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
@@ -1424,6 +1433,11 @@
   <parameter name="baseAddress" value="0x30140000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="gfx_0.cmd">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x3c000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="cache_0.dbg">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x30100000" />
@@ -1665,6 +1679,7 @@
    end="hps_0.f2h_sdram0_clock" />
  <connection kind="clock" version="20.1" start="pll_0.outclk1" end="mm_bridge.clk" />
  <connection kind="clock" version="20.1" start="pll_0.outclk1" end="smp_0.clock" />
+ <connection kind="clock" version="20.1" start="pll_0.outclk1" end="gfx_0.clock" />
  <connection
    kind="clock"
    version="20.1"
@@ -1889,6 +1904,11 @@
  <connection
    kind="reset"
    version="20.1"
+   start="clk_0.clk_reset"
+   end="gfx_0.reset_sink" />
+ <connection
+   kind="reset"
+   version="20.1"
    start="sys_sdram_pll_0.reset_source"
    end="vram.reset" />
  <connection