rtl/gfx: add debug registers

1 files changed, 52 insertions, 3 deletions

diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv
index 0d16552..bae65e3 100644
--- a/rtl/gfx/gfx.sv
+++ b/rtl/gfx/gfx.sv
@@ -24,13 +24,32 @@ module gfx
 	mat4 a, b, q, hold_q;
 	logic start, done;
 
-	assign mem_address = 26'b0;
 	assign mem_read = 1;
 	assign mem_write = 0;
 
 	assign readdata = hold_q[cmd_address[3:2]][cmd_address[1:0]];
 	assign writedata = cmd_writedata[`FLOAT_BITS - 1:0];
-	assign cmd_readdata = {{($bits(cmd_readdata) - `FLOAT_BITS){1'b0}}, readdata};
+
+	always_comb begin
+		if (!cmd_address[5])
+			cmd_readdata = {{($bits(cmd_readdata) - `FLOAT_BITS){1'b0}}, readdata};
+		else if (cmd_address[4])
+			cmd_readdata = cmd_address[0] ? cnt_done : cnt_start;
+		else
+			unique case (cmd_address[1:0])
+				2'b00:
+					cmd_readdata = snp_trans[31:0];
+
+				2'b01:
+					cmd_readdata = snp_trans[63:32];
+
+				2'b10:
+					cmd_readdata = snp_cycles[31:0];
+
+				2'b11:
+					cmd_readdata = snp_cycles[63:32];
+			endcase
+	end
 
 	mat_mat_mul mul
 	(
@@ -41,12 +60,20 @@ module gfx
 		.*
 	);
 
+	logic[63:0] cnt_cycles, cnt_trans, snp_cycles, snp_trans;
+	logic[24:0] cnt_addr;
+	logic[31:0] cnt_done, cnt_start;
+	assign mem_address = {cnt_addr, 1'b0};
+
 	always_ff @(posedge clk) begin
 		if (cmd_write) begin
 			if (cmd_address[4])
 				b[cmd_address[3:2]][cmd_address[1:0]] <= writedata;
 			else
 				a[cmd_address[3:2]][cmd_address[1:0]] <= writedata;
+
+			snp_trans <= cnt_trans;
+			snp_cycles <= cnt_cycles;
 		end
 
 		if (done)
@@ -54,6 +81,28 @@ module gfx
 	end
 
 	always_ff @(posedge clk or negedge rst_n)
-		start <= !rst_n ? 0 : (cmd_write && cmd_address == 5'b11111);
+		if (!rst_n) begin
+			start <= 0;
+			cnt_addr <= 0;
+			cnt_trans <= 0;
+			cnt_cycles <= 0;
+			cnt_done <= 0;
+			cnt_start <= 0;
+		end else begin
+			start <= cmd_write;
+			cnt_cycles <= cnt_cycles + 1;
+
+			if (start)
+				cnt_start <= cnt_start + 1;
+
+			if (done)
+				cnt_done <= cnt_done + 1;
+
+			if (!mem_waitrequest)
+				cnt_addr <= cnt_addr + 1;
+
+			if (mem_readdatavalid)
+				cnt_trans <= cnt_trans + 1;
+		end
 
 endmodule