Implemente byte-enable signal in stores

9 files changed, 86 insertions, 63 deletions

diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl
index 2cb7f85..a83c642 100644
--- a/conspiracion_bus_master_hw.tcl
+++ b/conspiracion_bus_master_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 20.1
-# Sat Nov 12 23:28:38 GMT 2022
+# Wed Nov 16 05:30:25 GMT 2022
 # DO NOT MODIFY
 
 
 # 
 # conspiracion_bus_master "Toplevel bus master" v1.0
-#  2022.11.12.23:28:37
+#  2022.11.16.05:30:25
 # 
 # 
 
@@ -102,6 +102,7 @@ add_interface_port core start start Input 1
 add_interface_port core irq irq Output 1
 add_interface_port core cpu_clk cpu_clk Output 1
 add_interface_port core cpu_rst_n cpu_rst_n Output 1
+add_interface_port core data_be data_be Input 4
 
 
 # 
diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
index 7775e42..0c6af55 100644
--- a/rtl/bus_master.sv
+++ b/rtl/bus_master.sv
@@ -9,6 +9,7 @@ module bus_master
 	output logic       ready,
 	output logic[31:0] data_rd,
 	input  logic[31:0] data_wr,
+	input  logic[3:0]  data_be,
 	output logic       cpu_clk,
 	                   cpu_rst_n,
 	                   irq,
@@ -34,7 +35,6 @@ module bus_master
 	assign cpu_rst_n = rst_n;
 
 	assign data_rd = avl_readdata;
-	assign avl_byteenable = 4'b1111; //TODO
 
 	always_comb
 		unique case(state)
@@ -56,12 +56,14 @@ module bus_master
 			avl_write <= 0;
 			avl_address <= 0;
 			avl_writedata <= 0;
+			avl_byteenable <= 0;
 		end else if((state == IDLE || !avl_waitrequest) && start) begin
 			state <= WAIT;
 			avl_read <= ~write;
 			avl_write <= write;
 			avl_address <= {addr, 2'b00};
 			avl_writedata <= data_wr;
+			avl_byteenable <= write ? data_be : 4'b1111;
 		end else if(state == WAIT && !avl_waitrequest) begin
 			state <= IDLE;
 			avl_read <= 0;
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index ce29821..89f84ec 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -2,18 +2,19 @@
 
 module arm810
 (
-	input  logic clk,
-	             rst_n,
-	             irq,
-	             halt,
-
-	output ptr   bus_addr,
-	output logic bus_start,
-	             bus_write,
-	input  logic bus_ready,
-	input  word  bus_data_rd,
-	output word  bus_data_wr,
-	output logic halted
+	input  logic      clk,
+	                  rst_n,
+	                  irq,
+	                  halt,
+
+	output ptr        bus_addr,
+	output logic      bus_start,
+	                  bus_write,
+	input  logic      bus_ready,
+	input  word       bus_data_rd,
+	output word       bus_data_wr,
+	output logic[3:0] bus_data_be,
+	output logic      halted
 );
 
 	ptr fetch_insn_pc, fetch_head, insn_addr;
@@ -72,6 +73,7 @@ module arm810
 		.mem_ready(data_ready),
 		.mem_data_rd(data_data_rd),
 		.mem_data_wr(data_data_wr),
+		.mem_data_be(data_data_be),
 		.*
 	);
 
@@ -160,8 +162,9 @@ module arm810
 	);
 
 	ptr data_addr;
-	logic data_start, data_write, data_ready, insn_ready;
 	word data_data_rd, data_data_wr, insn_data_rd;
+	logic data_start, data_write, data_ready, insn_ready;
+	logic[3:0] data_data_be;
 
 	core_mmu mmu
 	(
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index adfe9f7..4bff86e 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -47,6 +47,7 @@ module core_control
 	output logic[7:0]      shifter_shift,
 	output ptr             mem_addr,
 	output word            mem_data_wr,
+	output logic[3:0]      mem_data_be,
 	output logic           mem_start,
 	                       mem_write,
 	output word            mul_a,
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index 02f7b4a..dd5155a 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -18,6 +18,7 @@ module core_control_ldst
 	                   alu_b,
 
 	output ptr         mem_addr,
+	output logic[3:0]  mem_data_be,
 	output word        mem_data_wr,
 	                   mem_offset,
 	output logic       mem_start,
@@ -57,7 +58,7 @@ module core_control_ldst
 		.read(ldst_read),
 		.shift(ldst_shift),
 		.fault(), //TODO: alignment check
-		.byteenable(), //TODO
+		.byteenable(mem_data_be),
 		.*
 	);
 
diff --git a/rtl/core/mmu/arbiter.sv b/rtl/core/mmu/arbiter.sv
index 3740539..5a75ddf 100644
--- a/rtl/core/mmu/arbiter.sv
+++ b/rtl/core/mmu/arbiter.sv
@@ -1,25 +1,27 @@
 module core_mmu_arbiter
 (
-	input  logic clk,
-	             rst_n,
-
-	input  logic bus_ready,
-	input  word  bus_data_rd,
-	             data_data_wr,
-	input  ptr   insn_addr,
-	             data_addr,
-	input  logic insn_start,
-	             data_start,
-	             data_write,
-
-	output word  bus_data_wr,
-	output ptr   bus_addr,
-	output logic bus_start,
-	             bus_write,
-	             insn_ready,
-	             data_ready,
-	output word  insn_data_rd,
-	             data_data_rd
+	input  logic      clk,
+	                  rst_n,
+
+	input  logic      bus_ready,
+	input  word       bus_data_rd,
+	                  data_data_wr,
+	input  ptr        insn_addr,
+	                  data_addr,
+	input  logic      insn_start,
+	                  data_start,
+	                  data_write,
+	input  logic[3:0] data_data_be,
+
+	output word       bus_data_wr,
+	output logic[3:0] bus_data_be,
+	output ptr        bus_addr,
+	output logic      bus_start,
+	                  bus_write,
+	                  insn_ready,
+	                  data_ready,
+	output word       insn_data_rd,
+	                  data_data_rd
 );
 
 	enum int unsigned
@@ -31,6 +33,7 @@ module core_mmu_arbiter
 	ptr hold_addr;
 	word hold_data_wr;
 	logic active, hold_start, hold_write, hold_issue, hold_free, transition;
+	logic[3:0] hold_data_be;
 
 	assign insn_data_rd = bus_data_rd;
 	assign data_data_rd = bus_data_rd;
@@ -56,19 +59,20 @@ module core_mmu_arbiter
 			DATA: data_ready = bus_ready;
 		endcase
 
+		bus_data_wr = data_data_wr;
 		unique case(next_master)
 			INSN: begin
 				bus_addr = insn_addr;
 				bus_write = 0;
 				bus_start = insn_start;
-				bus_data_wr = {32{1'bx}};
+				bus_data_be = 4'b1111;
 			end
 
 			DATA: begin
 				bus_addr = data_addr;
 				bus_write = data_write;
 				bus_start = data_start;
-				bus_data_wr = data_data_wr;
+				bus_data_be = data_data_be;
 			end
 		endcase
 
@@ -77,6 +81,7 @@ module core_mmu_arbiter
 			bus_write = hold_write;
 			bus_start = 1;
 			bus_data_wr = hold_data_wr;
+			bus_data_be = hold_data_be;
 		end
 	end
 
@@ -89,6 +94,7 @@ module core_mmu_arbiter
 			hold_start <= 0;
 			hold_write <= 0;
 			hold_data_wr <= 0;
+			hold_data_be <= 0;
 		end else begin
 			master <= next_master;
 			active <= bus_start || (active && !bus_ready);
@@ -100,12 +106,14 @@ module core_mmu_arbiter
 						hold_start <= data_start;
 						hold_write <= data_write;
 						hold_data_wr <= data_data_wr;
+						hold_data_be <= data_data_be;
 					end
 
 					DATA: begin
 						hold_addr <= insn_addr;
 						hold_start <= insn_start;
 						hold_write <= 0;
+						hold_data_be <= 4'b1111;
 					end
 				endcase
 		end
diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv
index a4be70e..a909537 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/mmu/mmu.sv
@@ -1,25 +1,27 @@
 module core_mmu
 (
-	input  logic clk,
-	             rst_n,
+	input  logic      clk,
+	                  rst_n,
 
-	input  logic bus_ready,
-	input  word  bus_data_rd,
-	             data_data_wr,
-	input  ptr   insn_addr,
-	             data_addr,
-	input  logic insn_start,
-	             data_start,
-	             data_write,
+	input  logic      bus_ready,
+	input  word       bus_data_rd,
+	                  data_data_wr,
+	input  ptr        insn_addr,
+	                  data_addr,
+	input  logic      insn_start,
+	                  data_start,
+	                  data_write,
+	input  logic[3:0] data_data_be,
 
-	output word  bus_data_wr,
-	output ptr   bus_addr,
-	output logic bus_start,
-	             bus_write,
-	             insn_ready,
-	             data_ready,
-	output word  insn_data_rd,
-	             data_data_rd
+	output word       bus_data_wr,
+	output logic[3:0] bus_data_be,
+	output ptr        bus_addr,
+	output logic      bus_start,
+	                  bus_write,
+	                  insn_ready,
+	                  data_ready,
+	output word       insn_data_rd,
+	                  data_data_rd
 );
 
 	//TODO
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 450af54..62e71b3 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -40,6 +40,7 @@ module conspiracion
 	output wire [7:0]  vga_dac_b
 );
 
+	logic[3:0] data_be;
 	logic[29:0] addr;
 	logic[31:0] data_rd, data_wr;
 	logic reset_reset_n, cpu_clk, cpu_rst_n, cpu_halt, cpu_halted,
@@ -73,6 +74,7 @@ module conspiracion
 		.bus_addr(addr),
 		.bus_data_rd(data_rd),
 		.bus_data_wr(data_wr),
+		.bus_data_be(data_be),
 		.bus_ready(ready),
 		.bus_write(write),
 		.bus_start(start),
@@ -86,6 +88,7 @@ module conspiracion
 		.master_0_core_addr(addr),
 		.master_0_core_data_rd(data_rd),
 		.master_0_core_data_wr(data_wr),
+		.master_0_core_data_be(data_be),
 		.master_0_core_ready(ready),
 		.master_0_core_write(write),
 		.master_0_core_start(start),
diff --git a/tb/platform.sv b/tb/platform.sv
index 5fcb9f2..1e708cc 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -1,12 +1,13 @@
 module platform
 (
 	input  wire        clk_clk,                          //                       clk.clk
-	input  wire [29:0] master_0_core_addr    /*verilator public*/,// master_0_core.addr
-	output wire [31:0] master_0_core_data_rd /*verilator public*/,//              .data_rd
-	input  wire [31:0] master_0_core_data_wr /*verilator public*/,//              .data_wr
-	output wire        master_0_core_ready   /*verilator public*/,//              .ready
-	input  wire        master_0_core_write   /*verilator public*/,//              .write
-	input  wire        master_0_core_start   /*verilator public*/,//              .start
+	input  wire [29:0] master_0_core_addr,               // master_0_core.addr
+	output wire [31:0] master_0_core_data_rd,            //              .data_rd
+	input  wire [31:0] master_0_core_data_wr,            //              .data_wr
+	input  wire [3:0]  master_0_core_data_be,            //              .data_be
+	output wire        master_0_core_ready,              //              .ready
+	input  wire        master_0_core_write,              //              .write
+	input  wire        master_0_core_start,              //              .start
 	output wire        master_0_core_irq,                //                          .irq
 	output wire        master_0_core_cpu_clk,            //                          .cpu_clk
 	output wire        master_0_core_cpu_rst_n,
@@ -68,6 +69,7 @@ module platform
 		.ready(master_0_core_ready),
 		.data_rd(master_0_core_data_rd),
 		.data_wr(master_0_core_data_wr),
+		.data_be(master_0_core_data_be),
 		.cpu_clk(master_0_core_cpu_clk),
 		.cpu_rst_n(master_0_core_cpu_rst_n),
 		.irq(master_0_core_irq),