Implement branch history (simulation only)

3 files changed, 37 insertions, 1 deletions

diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index 23ecdcf..5bd03e1 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -4,7 +4,9 @@ module core_control_issue
 (
 	input  logic       clk,
 	                   rst_n,
-	                   halt,
+
+	input  logic       halt,
+	                   irq,
 
 	input  insn_decode dec,
 	input  ptr         insn_pc,
@@ -27,6 +29,13 @@ module core_control_issue
 
 	logic valid;
 
+`ifdef VERILATOR
+	word bh0 /*verilator public*/,
+	     bh1 /*verilator public*/,
+	     bh2 /*verilator public*/,
+	     bh3 /*verilator public*/;
+`endif
+
 	assign valid = !next_bubble && !halt;
 	assign issue = next_cycle.issue && dec.ctrl.execute && valid;
 	assign next_pc_visible = insn_pc + 2;
@@ -37,6 +46,13 @@ module core_control_issue
 			undefined <= 0;
 			pc_visible <= 2;
 			prefetch_abort <= 0;
+
+`ifdef VERILATOR
+			bh0 <= 0;
+			bh1 <= 0;
+			bh2 <= 0;
+			bh3 <= 0;
+`endif
 		end else if(next_cycle.issue) begin
 			if(valid) begin
 				undefined <= dec.ctrl.undefined;
@@ -50,6 +66,15 @@ module core_control_issue
 
 			pc <= insn_pc;
 			pc_visible <= next_pc_visible;
+
+`ifdef VERILATOR
+			if(insn_pc != pc && insn_pc != pc + 1) begin
+				bh0 <= {pc, 2'b00};
+				bh1 <= bh0;
+				bh2 <= bh1;
+				bh3 <= bh2;
+			end
+`endif
 		end
 
 endmodule
diff --git a/sim/sim.py b/sim/sim.py
index 03d45c7..b45ca7e 100755
--- a/sim/sim.py
+++ b/sim/sim.py
@@ -73,12 +73,18 @@ all_regs = [
     ('far', 'far'),
     ('fsr', 'fsr'),
     ('dacr', 'dacr'),
+    ('bh0', 'bh0'),
+    ('bh1', 'bh1'),
+    ('bh2', 'bh2'),
+    ('bh3', 'bh3'),
     ]
 
 regs = {}
 read_reg = lambda r: regs.setdefault(r, 0)
 
+do_output = None
 output_buffer = None
+
 def out(*args, **kwargs):
     global output_buffer
 
diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp
index 5af439f..e1095f2 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion.cpp
@@ -19,6 +19,7 @@
 #include "Vconspiracion_platform.h"
 #include "Vconspiracion_vga_domain.h"
 #include "Vconspiracion_core_control.h"
+#include "Vconspiracion_core_control_issue.h"
 #include "Vconspiracion_core_cp15_domain.h"
 #include "Vconspiracion_core_cp15_far.h"
 #include "Vconspiracion_core_cp15_fsr.h"
@@ -466,6 +467,10 @@ int main(int argc, char **argv)
 		std::fprintf(ctrl, "%08x far\n", core.cp15->far_->read);
 		std::fprintf(ctrl, "%08x fsr\n", core.cp15->fsr->read);
 		std::fprintf(ctrl, "%08x dacr\n", core.cp15->domain->mmu_dac);
+		std::fprintf(ctrl, "%08x bh0\n", core.control->ctrl_issue->bh0);
+		std::fprintf(ctrl, "%08x bh1\n", core.control->ctrl_issue->bh1);
+		std::fprintf(ctrl, "%08x bh2\n", core.control->ctrl_issue->bh2);
+		std::fprintf(ctrl, "%08x bh3\n", core.control->ctrl_issue->bh3);
 		std::fputs("=== end-regs ===\n", ctrl);
 	};