rtl/gfx: implement fp16 on verilator

4 files changed, 72 insertions, 3 deletions

diff --git a/Makefile b/Makefile
index c6fa11d..01e4c15 100644
--- a/Makefile
+++ b/Makefile
@@ -21,11 +21,11 @@ CROSS_CFLAGS  := -O3 -Wall -Wextra -Werror
 CROSS_LDFLAGS :=
 
 ifeq ($(shell which $(VERILATOR)),)
-  $(error verilator not found)
+	$(error verilator not found)
 endif
 
 ifeq ($(shell which $(COCOTB_CONFIG)),)
-  $(error cocotb not found)
+	$(error cocotb not found)
 endif
 
 ifdef FASTER_IS_BETTER
@@ -200,7 +200,7 @@ $(OBJ_DIR)/%.mk: \
 
 	mkdir -p $(dir $@)
 	$(VERILATOR) $(VFLAGS) \
-		--Mdir $(dir $@) --top $(word 1,$(subst /, ,$*)) \
+		--Mdir $(dir $@) --top $(word 1,$(subst /, ,$*)) -FI $(ROOT)/$(TB_DIR)/verilator.hpp \
 		$(filter %.sv %.cpp,$(patsubst tb/%,../tb/%,$^)) \
 		$(if $(filter $(TOP),$(word 1,$(subst /, ,$*))),, \
 			--vpi --public-flat-rw -LDFLAGS "$(COCOTB_LDFLAGS) $(LIBPYTHON)" \
diff --git a/rtl/gfx/fp_add.sv b/rtl/gfx/fp_add.sv
index fad4768..e8e0c5f 100644
--- a/rtl/gfx/fp_add.sv
+++ b/rtl/gfx/fp_add.sv
@@ -18,6 +18,23 @@ module fp_add
 		.areset(0),
 		.*
 	);
+`else
+	fp a_pipeline[`FP_ADD_STAGES - 1], b_pipeline[`FP_ADD_STAGES - 1];
+
+	integer i;
+
+	always @(posedge clk)
+		if (!stall) begin
+			a_pipeline[0] <= a;
+			b_pipeline[0] <= b;
+
+			for (i = 1; i < `FP_ADD_STAGES - 1; ++i) begin
+				a_pipeline[i] <= a_pipeline[i - 1];
+				b_pipeline[i] <= b_pipeline[i - 1];
+			end
+
+			q <= $c("taller::fp_add(", a_pipeline[`FP_ADD_STAGES - 2], ", ", b_pipeline[`FP_ADD_STAGES - 2], ")");
+		end
 `endif
 
 endmodule
diff --git a/rtl/gfx/fp_mul.sv b/rtl/gfx/fp_mul.sv
index 90d30fb..af5e09c 100644
--- a/rtl/gfx/fp_mul.sv
+++ b/rtl/gfx/fp_mul.sv
@@ -18,6 +18,23 @@ module fp_mul
 		.areset(0),
 		.*
 	);
+`else
+	fp a_pipeline[`FP_MUL_STAGES - 1], b_pipeline[`FP_MUL_STAGES - 1];
+
+	integer i;
+
+	always @(posedge clk)
+		if (!stall) begin
+			a_pipeline[0] <= a;
+			b_pipeline[0] <= b;
+
+			for (i = 1; i < `FP_MUL_STAGES - 1; ++i) begin
+				a_pipeline[i] <= a_pipeline[i - 1];
+				b_pipeline[i] <= b_pipeline[i - 1];
+			end
+
+			q <= $c("taller::fp_mul(", a_pipeline[`FP_MUL_STAGES - 2], ", ", b_pipeline[`FP_MUL_STAGES - 2], ")");
+		end
 `endif
 
 endmodule
diff --git a/tb/verilator.hpp b/tb/verilator.hpp
new file mode 100644
index 0000000..ff2e9c0
--- /dev/null
+++ b/tb/verilator.hpp
@@ -0,0 +1,35 @@
+#ifndef TALLER_VERILATOR_HPP
+#define TALLER_VERILATOR_HPP
+
+#include <cstdint>
+
+namespace taller
+{
+	union fp16_bits
+	{
+		std::uint16_t u16;
+		_Float16      fp16;
+	};
+
+	static inline std::uint16_t fp_add(std::uint16_t a, std::uint16_t b) noexcept
+	{
+		fp16_bits a_bits, b_bits, q_bits;
+		a_bits.u16 = a;
+		b_bits.u16 = b;
+
+		q_bits.fp16 = a_bits.fp16 + b_bits.fp16;
+		return q_bits.u16;
+	}
+
+	static inline std::uint16_t fp_mul(std::uint16_t a, std::uint16_t b) noexcept
+	{
+		fp16_bits a_bits, b_bits, q_bits;
+		a_bits.u16 = a;
+		b_bits.u16 = b;
+
+		q_bits.fp16 = a_bits.fp16 * b_bits.fp16;
+		return q_bits.u16;
+	}
+}
+
+#endif