diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-16 01:38:33 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-16 01:38:33 -0600 |
| commit | 2e6ce7931b690ccec1e41fa6847dfc1351c59d75 (patch) | |
| tree | 81759ffd1e61465a26e03414f25fbbb918308350 | |
| parent | f0b38daac3a2f987deb79fcca763f3b84b0f2b73 (diff) | |
Rename cycles as control
Diffstat (limited to '')
| -rw-r--r-- | conspiracion.qsf | 4 | ||||
| -rw-r--r-- | rtl/core/arm810.sv | 2 | ||||
| -rw-r--r-- | rtl/core/control/control.sv (renamed from rtl/core/cycles.sv) | 5 | ||||
| -rw-r--r-- | rtl/core/control/ldst/pop.sv (renamed from rtl/core/cycles/ldst/pop.sv) | 2 |
4 files changed, 6 insertions, 7 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index 7945383..b6b7587 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -136,8 +136,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/orr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cycles.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cycles/ldst/pop.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/control.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/pop.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index c43a832..c49600f 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -59,7 +59,7 @@ module arm810 word alu_a, alu_b, wr_value; logic[7:0] shifter_shift; - core_cycles cycles + core_control control ( .branch(explicit_branch), .alu(alu_ctrl), diff --git a/rtl/core/cycles.sv b/rtl/core/control/control.sv index ad35762..398c8c7 100644 --- a/rtl/core/cycles.sv +++ b/rtl/core/control/control.sv @@ -1,6 +1,6 @@ `include "core/uarch.sv" -module core_cycles +module core_control ( input logic clk, dec_execute, @@ -76,7 +76,7 @@ module core_cycles ((dec_update_flags || dec_conditional) && (final_update_flags || update_flags)) || (final_writeback && (final_rd == dec_data.rn || final_rd == dec_snd.r)); - core_cycles_ldst_pop ldst_pop + core_control_ldst_pop ldst_pop ( .regs(mem_regs), .valid(pop_valid), @@ -171,7 +171,6 @@ module core_cycles data_imm <= dec_snd.imm; data_shift_imm <= dec_snd.shift_imm; - shifter.shl <= dec_snd.shl; shifter.shr <= dec_snd.shr; shifter.ror <= dec_snd.ror; shifter.put_carry <= dec_snd.put_carry; diff --git a/rtl/core/cycles/ldst/pop.sv b/rtl/core/control/ldst/pop.sv index a4078d1..64dc04d 100644 --- a/rtl/core/cycles/ldst/pop.sv +++ b/rtl/core/control/ldst/pop.sv @@ -1,6 +1,6 @@ `include "core/uarch.sv" -module core_cycles_ldst_pop +module core_control_ldst_pop ( input reg_list regs, |