Improve mult sim

3 files changed, 28 insertions, 10 deletions

diff --git a/tb/sim/mult.c b/tb/sim/mult.c
index 531a824..67158f0 100644
--- a/tb/sim/mult.c
+++ b/tb/sim/mult.c
@@ -1,4 +1,10 @@
-int reset(int a, int b, int c)
+long long __attribute__((noinline)) mla(long long a, long long b, long long c)
 {
 	return a * b + c;
 }
+
+long long reset(int a, int b, int c)
+{
+	long long la = a, lb = b;
+	return mla(la * la, la + 2 * lb, c);
+}
diff --git a/tb/sim/mult.py b/tb/sim/mult.py
index 70e7490..b422b6a 100644
--- a/tb/sim/mult.py
+++ b/tb/sim/mult.py
@@ -1,7 +1,11 @@
+A, B, C = -123456, 7890, -98765
+
 def init():
-    init_reg(r0, -10)
-    init_reg(r1, 23)
-    init_reg(r2, -1234)
+    init_reg(r0, A)
+    init_reg(r1, B)
+    init_reg(r2, C)
 
 def final():
-    assert_reg(r0, -10 * 23 - 1234)
+    hi, lo = split_dword(A * A * (A + 2 * B) + C)
+    assert_reg(r0, lo)
+    assert_reg(r1, hi)
diff --git a/tb/sim/sim.py b/tb/sim/sim.py
index 9a31bee..cc1f205 100755
--- a/tb/sim/sim.py
+++ b/tb/sim/sim.py
@@ -176,6 +176,13 @@ def unsigned(n):
     assert -0x8000_0000 <= n <= 0xffff_ffff
     return n + 0x1_0000_0000 if n < 0 else n
 
+def split_dword(n):
+    assert -0x8000_0000_0000_0000 <= n <= 0xffff_ffff_ffff_ffff
+    if n < 0:
+        n += 0x1_0000_0000_0000_0000
+
+    return (n >> 32, n & 0xffff_ffff)
+
 def int_bytes(n):
     return n.to_bytes(4, 'little', signed=n < 0) if type(n) is int else n
 
@@ -218,11 +225,12 @@ spec = importlib.util.spec_from_file_location('sim', module_path)
 module = importlib.util.module_from_spec(spec)
 
 prelude = {
-    'read_reg':   read_reg,
-    'read_mem':   read_mem,
-    'assert_reg': assert_reg,
-    'assert_mem': assert_mem,
-    'init_reg':   init_reg
+    'read_reg':    read_reg,
+    'read_mem':    read_mem,
+    'assert_reg':  assert_reg,
+    'assert_mem':  assert_mem,
+    'init_reg':    init_reg,
+    'split_dword': split_dword,
     }
 
 prelude.update({k: v for k, v in all_regs})