Add CPUID register

3 files changed, 46 insertions, 0 deletions

diff --git a/conspiracion.qsf b/conspiracion.qsf
index ae0bfd9..e601adc 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -142,6 +142,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/mux.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/pop.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/stall.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cp15.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cpuid.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/map.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv
diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/cp15/cp15.sv
index b31ccb7..3855e13 100644
--- a/rtl/core/cp15/cp15.sv
+++ b/rtl/core/cp15/cp15.sv
@@ -1,4 +1,5 @@
 `include "core/uarch.sv"
+`include "core/cp15/map.sv"
 
 module core_cp15
 (
@@ -10,4 +11,30 @@ module core_cp15
 	output word          read
 );
 
+	logic load;
+	reg_num crm;
+	cp_opcode op1, op2;
+
+	assign load = dec.load;
+	assign crm = dec.crm;
+	assign op1 = dec.op1;
+	assign op2 = dec.op2;
+
+	word read_cpuid;
+
+	core_cp15_cpuid cpuid
+	(
+		.read(read_cpuid),
+		.*
+	);
+
+	always_comb
+		unique case(dec.crn)
+			`CP15_CRN_CPUID:
+				read = read_cpuid;
+
+			default:
+				read = {$bits(read){1'bx}};
+		endcase
+
 endmodule
diff --git a/rtl/core/cp15/cpuid.sv b/rtl/core/cp15/cpuid.sv
new file mode 100644
index 0000000..fd24631
--- /dev/null
+++ b/rtl/core/cp15/cpuid.sv
@@ -0,0 +1,18 @@
+`include "core/uarch.sv"
+`include "core/cp15/map.sv"
+
+module core_cp15_cpuid
+(
+	output word read
+);
+
+	/* If an <opcode2> value corresponding to an unimplemented or
+	 * reserved ID register is encountered, the System Control
+	 * coprocessor returns the value of the main ID register.
+	 *
+	 * ARM810.pdf, p. 104: Reading from CP15 register 0 returns
+	 * the value 0x4101810x.
+	 */
+	assign read = 32'h41018100;
+
+endmodule