Refactor decode signals into unified insn_decode struct

13 files changed, 184 insertions, 192 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index d66ac72..3f2a53c 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -29,25 +29,10 @@ module arm810
 		.*
 	);
 
-	datapath_decode dec;
-	psr_decode dec_psr;
-	branch_decode dec_branch;
-	snd_decode dec_snd;
-	data_decode dec_data;
-	ldst_decode dec_ldst;
-	mul_decode dec_mul;
-	coproc_decode dec_coproc;
+	insn_decode dec;
 
 	core_decode decode
 	(
-		.ctrl(dec),
-		.psr_ctrl(dec_psr),
-		.branch_ctrl(dec_branch),
-		.snd_ctrl(dec_snd),
-		.data_ctrl(dec_data),
-		.ldst_ctrl(dec_ldst),
-		.mul_ctrl(dec_mul),
-		.coproc_ctrl(dec_coproc),
 		.*
 	);
 
@@ -170,7 +155,7 @@ module arm810
 	core_cp15 cp15
 	(
 		.transfer(coproc),
-		.dec(dec_coproc),
+		.dec(dec.coproc),
 		.read(coproc_read),
 		.write(coproc_write),
 		.*
diff --git a/rtl/core/control/branch.sv b/rtl/core/control/branch.sv
index 3f8160e..59a4f54 100644
--- a/rtl/core/control/branch.sv
+++ b/rtl/core/control/branch.sv
@@ -2,24 +2,23 @@
 
 module core_control_branch
 (
-	input  logic           clk,
+	input  logic       clk,
 
-	input  datapath_decode dec,
-	input  branch_decode   dec_branch,
+	input  insn_decode dec,
 
-	input  ctrl_cycle      next_cycle,
-	input  logic           issue,
-	input  ptr             next_pc_visible,
+	input  ctrl_cycle  next_cycle,
+	input  logic       issue,
+	input  ptr         next_pc_visible,
 
-	output logic           branch,
-	output ptr             branch_target
+	output logic       branch,
+	output ptr         branch_target
 );
 
 	always_ff @(posedge clk) begin
 		branch <= 0;
 		if(next_cycle == ISSUE && issue) begin
-			branch <= dec.branch;
-			branch_target <= next_pc_visible + dec_branch.offset;
+			branch <= dec.ctrl.branch;
+			branch_target <= next_pc_visible + dec.branch.offset;
 		end
 	end
 
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 06978e6..4ea590a 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -3,13 +3,7 @@
 module core_control
 (
 	input  logic           clk,
-	input  datapath_decode dec,
-	input  psr_decode      dec_psr,
-	input  branch_decode   dec_branch,
-	input  data_decode     dec_data,
-	input  snd_decode      dec_snd,
-	input  ldst_decode     dec_ldst,
-	input  mul_decode      dec_mul,
+	input  insn_decode     dec,
 	input  ptr             fetch_insn_pc,
 	input  psr_flags       flags,
 	                       alu_flags,
diff --git a/rtl/core/control/coproc.sv b/rtl/core/control/coproc.sv
index f0b4169..b0c8bea 100644
--- a/rtl/core/control/coproc.sv
+++ b/rtl/core/control/coproc.sv
@@ -2,19 +2,19 @@
 
 module core_control_coproc
 (
-	input  logic           clk,
+	input  logic       clk,
 
-	input  datapath_decode dec,
+	input  insn_decode dec,
 
-	input  ctrl_cycle      next_cycle,
-	input  logic           issue,
+	input  ctrl_cycle  next_cycle,
+	input  logic       issue,
 
-	output logic           coproc
+	output logic       coproc
 );
 
 	always_ff @(posedge clk)
 		if(next_cycle == ISSUE && issue)
-			coproc <= dec.coproc;
+			coproc <= dec.ctrl.coproc;
 
 	initial
 		coproc = 0;
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv
index 320747f..0d87b02 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/control/data.sv
@@ -4,8 +4,7 @@ module core_control_data
 (
 	input  logic           clk,
 
-	input  data_decode     dec_data,
-	input  snd_decode      dec_snd,
+	input  insn_decode     dec,
 	input  word            rd_value_a,
 	                       rd_value_b,
 	input  logic           mem_ready,
@@ -66,18 +65,18 @@ module core_control_data
 	always_ff @(posedge clk)
 		unique case(next_cycle)
 			ISSUE: begin
-				alu <= dec_data.op;
+				alu <= dec.data.op;
 				c_in <= flags.c;
 
-				data_snd_is_imm <= dec_snd.is_imm;
-				data_snd_shift_by_reg <= dec_snd.shift_by_reg;
-				data_imm <= dec_snd.imm;
-				data_shift_imm <= dec_snd.shift_imm;
+				data_snd_is_imm <= dec.snd.is_imm;
+				data_snd_shift_by_reg <= dec.snd.shift_by_reg;
+				data_imm <= dec.snd.imm;
+				data_shift_imm <= dec.snd.shift_imm;
 
-				shifter.shr <= dec_snd.shr;
-				shifter.ror <= dec_snd.ror;
-				shifter.put_carry <= dec_snd.put_carry;
-				shifter.sign_extend <= dec_snd.sign_extend;
+				shifter.shr <= dec.snd.shr;
+				shifter.ror <= dec.snd.ror;
+				shifter.put_carry <= dec.snd.put_carry;
+				shifter.sign_extend <= dec.snd.sign_extend;
 			end
 
 			RD_INDIRECT_SHIFT: begin
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index 6ad27f7..5ed03f0 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -2,34 +2,34 @@
 
 module core_control_issue
 (
-	input  logic           clk,
+	input  logic       clk,
 
-	input  datapath_decode dec,
-	input  ptr             fetch_insn_pc,
+	input  insn_decode dec,
+	input  ptr         fetch_insn_pc,
 
-	input  ctrl_cycle      next_cycle,
-	input  logic           next_bubble,
+	input  ctrl_cycle  next_cycle,
+	input  logic       next_bubble,
 
 `ifdef VERILATOR
-	input  word            insn,
+	input  word        insn,
 `endif
 
-	output logic           issue,
-	                       undefined,
-	output ptr             pc,
-	                       pc_visible,
-	                       next_pc_visible
+	output logic       issue,
+	                   undefined,
+	output ptr         pc,
+	                   pc_visible,
+	                   next_pc_visible
 );
 
-	assign issue = next_cycle == ISSUE && dec.execute && !next_bubble;
+	assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble;
 	assign next_pc_visible = fetch_insn_pc + 2;
 
 	always_ff @(posedge clk)
 		if(next_cycle == ISSUE) begin
-			undefined <= dec.undefined;
+			undefined <= dec.ctrl.undefined;
 
 `ifdef VERILATOR
-			if(dec.undefined)
+			if(dec.ctrl.undefined)
 				$display("[core] undefined insn: [0x%08x] %08x", fetch_insn_pc << 2, insn);
 `endif
 
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index c8dac7c..2a295c8 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -2,29 +2,28 @@
 
 module core_control_ldst
 (
-	input  logic           clk,
-
-	input  datapath_decode dec,
-	input  ldst_decode     dec_ldst,
-	input  logic           issue,
-	                       mem_ready,
-	input  word            rd_value_b,
-	                       q_alu,
-
-	input  ctrl_cycle      cycle,
-	                       next_cycle,
-	input  word            alu_a,
-	                       alu_b,
-
-	output ptr             mem_addr,
-	output word            mem_data_wr,
-	                       mem_offset,
-	output logic           mem_start,
-	                       mem_write,
-	                       pop_valid,
-	                       ldst,
-	                       ldst_writeback,
-	output reg_num         popped
+	input  logic       clk,
+
+	input  insn_decode dec,
+	input  logic       issue,
+	                   mem_ready,
+	input  word        rd_value_b,
+	                   q_alu,
+
+	input  ctrl_cycle  cycle,
+	                   next_cycle,
+	input  word        alu_a,
+	                   alu_b,
+
+	output ptr         mem_addr,
+	output word        mem_data_wr,
+	                   mem_offset,
+	output logic       mem_start,
+	                   mem_write,
+	                   pop_valid,
+	                   ldst,
+	                   ldst_writeback,
+	output reg_num     popped
 );
 
 	logic ldst_pre, ldst_increment;
@@ -47,17 +46,17 @@ module core_control_ldst
 	always_ff @(posedge clk)
 		unique case(next_cycle)
 			ISSUE: begin
-				// TODO: dec_ldst.unprivileged/user_regs
+				// TODO: dec.ldst.unprivileged/user_regs
 				// TODO: byte/halfword sizes
 				if(issue)
-					ldst <= dec.ldst;
+					ldst <= dec.ctrl.ldst;
 
-				ldst_pre <= dec_ldst.pre_indexed;
-				ldst_increment <= dec_ldst.increment;
-				ldst_writeback <= dec_ldst.writeback;
+				ldst_pre <= dec.ldst.pre_indexed;
+				ldst_increment <= dec.ldst.increment;
+				ldst_writeback <= dec.ldst.writeback;
 
-				mem_regs <= dec_ldst.regs;
-				mem_write <= !dec_ldst.load;
+				mem_regs <= dec.ldst.regs;
+				mem_write <= !dec.ldst.load;
 			end
 
 			TRANSFER: begin
diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv
index 5377045..8f7cd91 100644
--- a/rtl/core/control/mul.sv
+++ b/rtl/core/control/mul.sv
@@ -2,29 +2,28 @@
 
 module core_control_mul
 (
-	input  logic           clk,
+	input  logic       clk,
 
-	input  datapath_decode dec,
-	input  mul_decode      dec_mul,
-	input  logic           mul_ready,
-	input  word            rd_value_a,
-	                       rd_value_b,
+	input  insn_decode dec,
+	input  logic       mul_ready,
+	input  word        rd_value_a,
+	                   rd_value_b,
 
-	input  ctrl_cycle      cycle,
-	                       next_cycle,
-	input  logic           issue,
+	input  ctrl_cycle  cycle,
+	                   next_cycle,
+	input  logic       issue,
 
-	output word            mul_a,
-	                       mul_b,
-	                       mul_c_hi,
-	                       mul_c_lo,
-	output reg_num         mul_r_add_hi,
-	                       mul_r_add_lo,
-	output logic           mul,
-	                       mul_add,
-	                       mul_long,
-	                       mul_start,
-	                       mul_signed
+	output word        mul_a,
+	                   mul_b,
+	                   mul_c_hi,
+	                   mul_c_lo,
+	output reg_num     mul_r_add_hi,
+	                   mul_r_add_lo,
+	output logic       mul,
+	                   mul_add,
+	                   mul_long,
+	                   mul_start,
+	                   mul_signed
 );
 
 	word hold_a, hold_b;
@@ -37,12 +36,12 @@ module core_control_mul
 
 		unique case(next_cycle)
 			ISSUE: begin
-				mul <= issue && dec.mul;
-				mul_add <= dec_mul.add;
-				mul_long <= dec_mul.long_mul;
-				mul_signed <= dec_mul.signed_mul;
-				mul_r_add_hi <= dec_mul.r_add_hi;
-				mul_r_add_lo <= dec_mul.r_add_lo;
+				mul <= issue && dec.ctrl.mul;
+				mul_add <= dec.mul.add;
+				mul_long <= dec.mul.long_mul;
+				mul_signed <= dec.mul.signed_mul;
+				mul_r_add_hi <= dec.mul.r_add_hi;
+				mul_r_add_lo <= dec.mul.r_add_lo;
 			end
 
 			MUL:
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index 62ad503..09fb144 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -4,8 +4,7 @@ module core_control_select
 (
 	input  logic       clk,
 
-	input  data_decode dec_data,
-	input  snd_decode  dec_snd,
+	input  insn_decode dec,
 
 	input  ctrl_cycle  cycle,
 	                   next_cycle,
@@ -31,13 +30,13 @@ module core_control_select
 
 		unique case(next_cycle)
 			ISSUE: begin
-				ra = dec_data.rn;
-				rb = dec_snd.r;
+				ra = dec.data.rn;
+				rb = dec.snd.r;
 			end
 
 			TRANSFER:
 				if(cycle != TRANSFER || mem_ready)
-					// final_rd viene de dec_ldst.rd
+					// final_rd viene de dec.ldst.rd
 					rb = pop_valid ? popped : final_rd;
 
 			MUL_ACC_LD: begin
@@ -52,7 +51,7 @@ module core_control_select
 		last_rb <= rb;
 
 		if(next_cycle == ISSUE)
-			r_shift <= dec_snd.r_shift;
+			r_shift <= dec.snd.r_shift;
 	end
 
 	initial begin
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index edf9265..223fecb 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -2,23 +2,20 @@
 
 module core_control_stall
 (
-	input  logic           clk,
-
-	input  datapath_decode dec,
-	input  psr_decode      dec_psr,
-	input  data_decode     dec_data,
-	input  snd_decode      dec_snd,
-
-	input  ctrl_cycle      next_cycle,
-	input  logic           final_update_flags,
-	                       update_flags,
-	                       final_writeback,
-	                       writeback,
-	input  reg_num         final_rd,
-
-	output logic           stall,
-	                       bubble,
-	                       next_bubble
+	input  logic       clk,
+
+	input  insn_decode dec,
+
+	input  ctrl_cycle  next_cycle,
+	input  logic       final_update_flags,
+	                   update_flags,
+	                   final_writeback,
+	                   writeback,
+	input  reg_num     final_rd,
+
+	output logic       stall,
+	                   bubble,
+	                   next_bubble
 );
 
 	logic pc_writeback_hazard, flags_hazard, data_hazard, rn_hazard,
@@ -30,10 +27,10 @@ module core_control_stall
 	assign pc_writeback_hazard = final_writeback && final_rd == `R15;
 	assign flags_hazard = flags_dependency && updating_flags;
 	assign data_hazard = final_writeback && (rn_hazard || snd_hazard);
-	assign rn_hazard = dec_data.uses_rn && (final_rd == dec_data.rn || dec_data.rn == `R15);
-	assign snd_hazard = !dec_snd.is_imm && (dec_snd.r == final_rd || dec_snd.r == `R15);
+	assign rn_hazard = dec.data.uses_rn && (final_rd == dec.data.rn || dec.data.rn == `R15);
+	assign snd_hazard = !dec.snd.is_imm && (dec.snd.r == final_rd || dec.snd.r == `R15);
 
-	assign flags_dependency = dec_psr.update_flags || dec.conditional;
+	assign flags_dependency = dec.psr.update_flags || dec.ctrl.conditional;
 	assign updating_flags = final_update_flags || update_flags;
 
 	always_ff @(posedge clk)
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 6506ae5..73a8a4c 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -2,37 +2,35 @@
 
 module core_control_writeback
 (
-	input  logic           clk,
-
-	input  datapath_decode dec,
-	input  psr_decode      dec_psr,
-	input  data_decode     dec_data,
-	input  psr_flags       alu_flags,
-	input  word            q_alu,
-	                       mem_data_rd,
-	input  logic           mem_ready,
-	                       mem_write,
-	input  word            mul_q_hi,
-	                       mul_q_lo,
-
-	input  ctrl_cycle      cycle,
-	                       next_cycle,
-	input  word            saved_base,
-	                       vector,
-	input  reg_num         ra,
-	                       popped,
-	                       mul_r_add_hi,
-	input  logic           issue,
-	                       pop_valid,
-
-	output reg_num         rd,
-	                       final_rd,
-	output logic           writeback,
-	                       final_writeback,
-	                       update_flags,
-	                       final_update_flags,
-	output word            wr_value,
-	output psr_flags       wb_alu_flags
+	input  logic       clk,
+
+	input  insn_decode dec,
+	input  psr_flags   alu_flags,
+	input  word        q_alu,
+	                   mem_data_rd,
+	input  logic       mem_ready,
+	                   mem_write,
+	input  word        mul_q_hi,
+	                   mul_q_lo,
+
+	input  ctrl_cycle  cycle,
+	                   next_cycle,
+	input  word        saved_base,
+	                   vector,
+	input  reg_num     ra,
+	                   popped,
+	                   mul_r_add_hi,
+	input  logic       issue,
+	                   pop_valid,
+
+	output reg_num     rd,
+	                   final_rd,
+	output logic       writeback,
+	                   final_writeback,
+	                   update_flags,
+	                   final_update_flags,
+	output word        wr_value,
+	output psr_flags   wb_alu_flags
 );
 
 	reg_num last_rd;
@@ -108,7 +106,7 @@ module core_control_writeback
 
 		unique case(next_cycle)
 			ISSUE:
-				final_rd <= dec_data.rd;
+				final_rd <= dec.data.rd;
 
 			TRANSFER:
 				if((cycle != TRANSFER || mem_ready) && pop_valid)
@@ -123,7 +121,7 @@ module core_control_writeback
 
 		unique case(next_cycle)
 			ISSUE:
-				final_writeback <= issue && dec.writeback;
+				final_writeback <= issue && dec.ctrl.writeback;
 
 			EXCEPTION:
 				final_writeback <= 1;
@@ -140,7 +138,7 @@ module core_control_writeback
 
 		unique case(next_cycle)
 			ISSUE:
-				final_update_flags <= issue && dec_psr.update_flags;
+				final_update_flags <= issue && dec.psr.update_flags;
 
 			EXCEPTION:
 				final_update_flags <= 0;
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index 3096c7a..1e27878 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -3,19 +3,30 @@
 
 module core_decode
 (
-	input  word            insn,
-	input  psr_flags       flags,
-
-	output datapath_decode ctrl,
-	output psr_decode      psr_ctrl,
-	output branch_decode   branch_ctrl,
-	output snd_decode      snd_ctrl,
-	output data_decode     data_ctrl,
-	output ldst_decode     ldst_ctrl,
-	output mul_decode      mul_ctrl,
-	output coproc_decode   coproc_ctrl
+	input  word        insn,
+	input  psr_flags   flags,
+
+	output insn_decode dec
 );
 
+	mul_decode mul_ctrl;
+	psr_decode psr_ctrl;
+	snd_decode snd_ctrl;
+	data_decode data_ctrl;
+	ldst_decode ldst_ctrl;
+	branch_decode branch_ctrl;
+	coproc_decode coproc_ctrl;
+	datapath_decode ctrl;
+
+	assign dec.mul = mul_ctrl;
+	assign dec.psr = psr_ctrl;
+	assign dec.snd = snd_ctrl;
+	assign dec.ctrl = ctrl;
+	assign dec.data = data_ctrl;
+	assign dec.ldst = ldst_ctrl;
+	assign dec.branch = branch_ctrl;
+	assign dec.coproc = coproc_ctrl;
+
 	assign ctrl.execute = execute;
 	assign ctrl.undefined = undefined;
 	assign ctrl.conditional = conditional;
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv
index d4654a7..1d43caf 100644
--- a/rtl/core/uarch.sv
+++ b/rtl/core/uarch.sv
@@ -169,6 +169,18 @@ typedef struct packed
 	reg_num   crn, crm;
 } coproc_decode;
 
+typedef struct packed
+{
+	datapath_decode ctrl;
+	psr_decode      psr;
+	branch_decode   branch;
+	snd_decode      snd;
+	data_decode     data;
+	ldst_decode     ldst;
+	mul_decode      mul;
+	coproc_decode   coproc;
+} insn_decode;
+
 typedef enum
 {
 	ISSUE,