conspiracion/tb/sim, branch master

conspiracion/tb/sim, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. tb/sim: update constant in hazards test 2024-02-20T17:12:23+00:00 Alejandro Soto alejandro@34project.org 2024-02-19T14:36:55+00:00 a9ba2e1d3e0bee4f7534b29f266d122567d6dd42

tb/sim/sdram: lower max cycles 2023-10-05T19:07:57+00:00 Alejandro Soto alejandro@34project.org 2023-10-05T12:47:22+00:00 dc705df98037bfd9db8efded025651b676e87754

app, doc, image_processing, tb/sim/descifrador: remove;5D 2023-10-04T22:46:57+00:00 Alejandro Soto alejandro@34project.org 2023-10-04T22:46:57+00:00 865a1e8ca820da17a9f9c034677a7a959ddaee36

tb/sim/strex: test monitor after exception 2023-10-04T00:56:36+00:00 Alejandro Soto alejandro@34project.org 2023-10-04T00:56:36+00:00 1094451235282af6a9daba2b2a460577f82d289c

tb/sim: add test: strex 2023-10-03T13:46:10+00:00 Alejandro Soto alejandro@34project.org 2023-10-03T13:46:10+00:00 d9e89db78284fc1a9f0aa1ed86d076f50c58c1f2

tb/sim: add test: smp_boot 2023-10-03T05:29:46+00:00 Alejandro Soto alejandro@34project.org 2023-10-03T04:54:55+00:00 548187dfc392d0beef4cc86e7d3d22d885276e5d

rtl/cache: fix writeback corruption 2023-09-25T22:56:06+00:00 Alejandro Soto alejandro@34project.org 2023-09-25T22:47:45+00:00 cd02f821525b8710dd37e2bc39a8a7dbc36ac4b0

tb: implement cache ring 2023-09-25T11:14:25+00:00 Alejandro Soto alejandro@34project.org 2023-09-25T11:14:25+00:00 d18a37a740db37707e5266e5ca6a8fd956737197

Implement privileged ldm/stm of user registers 2022-12-19T00:31:03+00:00 Alejandro Soto alejandro@34project.org 2022-12-19T00:31:03+00:00 e290956adf94dade4c9c4cd057cca08af1c61aeb

Fix datapath of shifter carry-out during adc/sbc/rsc 2022-12-18T06:22:23+00:00 Alejandro Soto alejandro@34project.org 2022-12-18T06:22:13+00:00 6d458ad9629268ecfc69881b4fb10dca0498fbd0