conspiracion/tb/sim/fibonacci.py, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl/cache: fix writeback corruption 2023-09-25T22:56:06+00:00 Alejandro Soto alejandro@34project.org 2023-09-25T22:47:45+00:00 cd02f821525b8710dd37e2bc39a8a7dbc36ac4b0 






Fix handling of multi-cycle Avalon waitrequest states in bus master
2022-11-09T03:33:59+00:00

Alejandro Soto
alejandro@34project.org

2022-11-09T03:33:59+00:00

1ea0519a2b6b81e0ba324cd69f8785735e7cbef5












Break false dependency on r0 for MOV/MVN
2022-10-17T07:25:42+00:00

Alejandro Soto
alejandro@34project.org

2022-10-17T07:25:42+00:00

1ca30fb3de058b9498f6a6bbc646b79978ece846












Add C simulation testbench
2022-10-16T22:02:52+00:00

Alejandro Soto
alejandro@34project.org

2022-10-16T22:02:52+00:00

a5468f968b46707e08eacf79847f1e12a4213ff7