conspiracion/tb/platform.sv, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Makefile, tb: add support for cocotb 2023-10-05T19:07:57+00:00 Alejandro Soto alejandro@34project.org 2023-10-05T06:36:37+00:00 4acd900c4602db0353d11bf6841ddadfd80c57b8 






rtl/cache: implement debug interface
2023-10-04T10:40:48+00:00

Alejandro Soto
alejandro@34project.org

2023-10-04T09:09:13+00:00

3de2c7e7dd214f80b8b9cca575e42e0b1b08034d












tb: implement verilated slaves
2023-10-03T05:29:46+00:00

Alejandro Soto
alejandro@34project.org

2023-10-02T22:47:23+00:00

2c6998db4ad3b663fa32384739bc11930be5afa2












rtl: implement exclusive monitor datapath
2023-10-02T07:46:44+00:00

Alejandro Soto
alejandro@34project.org

2023-10-02T07:46:44+00:00

70d7dc9489f4d5b91d8138e0a341eec4ad7f15b0












tb: implement quad-core SMP
2023-10-01T07:04:19+00:00

Alejandro Soto
alejandro@34project.org

2023-09-30T23:44:26+00:00

cf6ab851183870bca61252a56b274342380d0960












platform: implement SMP controller
2023-09-30T07:20:48+00:00

Alejandro Soto
alejandro@34project.org

2023-09-30T06:07:20+00:00

d1b10aa380578b5af20081dd37f2d36ec111cbd2












rtl/mp: fix design
2023-09-26T08:03:05+00:00

Alejandro Soto
alejandro@34project.org

2023-09-26T08:03:05+00:00

a2f0c253384ec747735b102ccedfae5c96626fbc












rtl/core, tb: replace bus_master with a new top-level module
2023-09-26T03:33:49+00:00

Alejandro Soto
alejandro@34project.org

2023-09-26T01:12:49+00:00

ed0bd705f94f6aea568ec8405534984a37770f21












tb: implement cache ring
2023-09-25T11:14:25+00:00

Alejandro Soto
alejandro@34project.org

2023-09-25T11:14:25+00:00

d18a37a740db37707e5266e5ca6a8fd956737197












Bug fixes
2022-11-17T14:16:14+00:00

JulianCamacho
jjulian.341@gmail.com

2022-11-17T14:16:14+00:00

61bf2100fbd5e0a5f4bd1f013d70d8027604bbba