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<title>conspiracion/tb/mem.cpp, branch ce4302/p2</title>
<subtitle>Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.</subtitle>
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<entry>
<title>tb:  move most C++ source files to tb/top/conspiracion</title>
<updated>2023-10-05T19:07:57+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2023-10-05T12:31:27+00:00</published>
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<entry>
<title>tb: read line-sized reads of word-sized I/O slaves</title>
<updated>2023-09-29T10:53:21+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2023-09-29T10:53:21+00:00</published>
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<entry>
<title>tb: implement support for cache line-sized slaves</title>
<updated>2023-09-25T05:39:17+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2023-09-25T05:39:17+00:00</published>
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<entry>
<title>Implement VGA simulation</title>
<updated>2022-11-15T03:10:40+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-11-15T03:10:40+00:00</published>
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<entry>
<title>Fix handling of multi-cycle Avalon waitrequest states in bus master</title>
<updated>2022-11-09T03:33:59+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-11-09T03:33:59+00:00</published>
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<entry>
<title>Implement Avalon memory module for simulation</title>
<updated>2022-09-18T23:14:54+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-09-18T23:14:54+00:00</published>
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