conspiracion/rtl/top, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Fix clock/reset timing in single-step, dsp_mul 2022-12-21T10:16:46+00:00 Alejandro Soto alejandro@34project.org 2022-12-20T22:16:08+00:00 d2fc80b6d8b4a64efa00c8458ae94f6b44ddf6be 






Implement single-stepping
2022-12-08T01:51:41+00:00

Alejandro Soto
alejandro@34project.org

2022-12-08T01:18:04+00:00

c39552375661e495b344e8386649ade92a4d45b2












Implement breakpoints
2022-12-06T21:27:42+00:00

Alejandro Soto
alejandro@34project.org

2022-12-06T21:27:42+00:00

b1761b8eac5777c09723bbc8cd31cc05d8ec35ae












Implement gdbstub
2022-12-06T19:04:15+00:00

Alejandro Soto
alejandro@34project.org

2022-12-06T19:04:15+00:00

064b72ae4eb22336438288a9664a37c0dd07f4bc












Bug fixes
2022-11-17T14:16:14+00:00

JulianCamacho
jjulian.341@gmail.com

2022-11-17T14:16:14+00:00

61bf2100fbd5e0a5f4bd1f013d70d8027604bbba












Implemente byte-enable signal in stores
2022-11-16T05:31:30+00:00

Alejandro Soto
alejandro@34project.org

2022-11-16T05:18:09+00:00

d9dfa098323bc9ffdc9e976bd4106efc75b2954a












Replace vga_controller with streaming Altera IP
2022-11-15T22:25:49+00:00

Alejandro Soto
alejandro@34project.org

2022-11-15T22:25:41+00:00

044558e53d50ebd053abc76930723c9d7f606569












Fix VRAM clock
2022-11-15T05:32:46+00:00

Alejandro Soto
alejandro@34project.org

2022-11-15T05:32:46+00:00

22ef9a701d58d5e9d965793785241ad4aab29469












Restore clock connections in Platform Designer
2022-11-13T12:53:53+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T12:53:53+00:00

bf746b3ee73081dff0da03a54749d1fd3c0215f6












Implement CPU halt
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T03:47:54+00:00

6cb000adf57d7af2ec4aac8fd93d12f09cc63556