conspiracion/rtl/mod.mk, branch masterLinux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.rtl/vdc: initial commit of video display controller2024-05-26T18:51:51+00:00Alejandro Sotoalejandro@34project.org2024-05-26T17:16:04+00:002e12077e682a27a159122b5676301c8c433a58fe
rtl/if_common: initial commit, moved out of gfx2024-05-06T00:45:11+00:00Alejandro Sotoalejandro@34project.org2024-05-06T00:45:11+00:00638b75fb4c8fdc3c9d3a208f6bd9976841bc0928
rtl/pkt_switch: replace axi_timer example with pkt_switch2024-05-04T20:19:48+00:00Alejandro Sotoalejandro@34project.org2024-05-04T20:19:48+00:00a7d92072c0bdc3a3e1c99de64f353e932846bc2a
rtl/axi_timer: initial commit2024-04-27T18:14:41+00:00Alejandro Sotoalejandro@34project.org2024-04-27T18:14:41+00:0050b71c7f0ea2574eb4802e1a12fe8b0920a4ca7f
This a buggy timer, imported from https://github.com/astrakhov-design/axi_timer.
It will be used for a testbench hello world case
This a buggy timer, imported from https://github.com/astrakhov-design/axi_timer.
It will be used for a testbench hello world case
rtl/fpu: initial commit2024-04-27T17:45:23+00:00Alejandro Sotoalejandro@34project.org2024-04-27T17:45:23+00:0045b5eabe868ac2f8a755379bde07c102caf74afb
Imported from https://github.com/taneroksuz/fpu-sp
Imported from https://github.com/taneroksuz/fpu-sp
rtl/wb2axip: add to version control2024-03-06T08:38:24+00:00Alejandro Sotoalejandro@34project.org2024-03-06T08:38:24+00:003038edc09a2eb15762f2e58533f429489107520b